1 //===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines an instruction selector for the MSP430 target.
11 //===----------------------------------------------------------------------===//
14 #include "MSP430TargetMachine.h"
15 #include "llvm/CodeGen/MachineFrameInfo.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SelectionDAGISel.h"
21 #include "llvm/CodeGen/TargetLowering.h"
22 #include "llvm/Config/llvm-config.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Intrinsics.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
33 #define DEBUG_TYPE "msp430-isel"
36 struct MSP430ISelAddressMode {
42 struct { // This is really a union, discriminated by BaseType!
48 const GlobalValue *GV;
50 const BlockAddress *BlockAddr;
53 unsigned Align; // CP alignment.
55 MSP430ISelAddressMode()
56 : BaseType(RegBase), Disp(0), GV(nullptr), CP(nullptr),
57 BlockAddr(nullptr), ES(nullptr), JT(-1), Align(0) {
60 bool hasSymbolicDisplacement() const {
61 return GV != nullptr || CP != nullptr || ES != nullptr || JT != -1;
64 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
65 LLVM_DUMP_METHOD void dump() {
66 errs() << "MSP430ISelAddressMode " << this << '\n';
67 if (BaseType == RegBase && Base.Reg.getNode() != nullptr) {
68 errs() << "Base.Reg ";
69 Base.Reg.getNode()->dump();
70 } else if (BaseType == FrameIndexBase) {
71 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
73 errs() << " Disp " << Disp << '\n';
80 errs() << " Align" << Align << '\n';
85 errs() << " JT" << JT << " Align" << Align << '\n';
91 /// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
92 /// instructions for SelectionDAG operations.
95 class MSP430DAGToDAGISel : public SelectionDAGISel {
97 MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
98 : SelectionDAGISel(TM, OptLevel) {}
101 StringRef getPassName() const override {
102 return "MSP430 DAG->DAG Pattern Instruction Selection";
105 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
106 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
107 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
109 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
110 std::vector<SDValue> &OutOps) override;
112 // Include the pieces autogenerated from the target description.
113 #include "MSP430GenDAGISel.inc"
115 // Main method to transform nodes into machine nodes.
116 void Select(SDNode *N) override;
118 bool tryIndexedLoad(SDNode *Op);
119 bool tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8,
122 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
124 } // end anonymous namespace
126 /// createMSP430ISelDag - This pass converts a legalized DAG into a
127 /// MSP430-specific DAG, ready for instruction scheduling.
129 FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
130 CodeGenOpt::Level OptLevel) {
131 return new MSP430DAGToDAGISel(TM, OptLevel);
135 /// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode.
136 /// These wrap things that will resolve down into a symbol reference. If no
137 /// match is possible, this returns true, otherwise it returns false.
138 bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) {
139 // If the addressing mode already has a symbol as the displacement, we can
140 // never match another symbol.
141 if (AM.hasSymbolicDisplacement())
144 SDValue N0 = N.getOperand(0);
146 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
147 AM.GV = G->getGlobal();
148 AM.Disp += G->getOffset();
149 //AM.SymbolFlags = G->getTargetFlags();
150 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
151 AM.CP = CP->getConstVal();
152 AM.Align = CP->getAlignment();
153 AM.Disp += CP->getOffset();
154 //AM.SymbolFlags = CP->getTargetFlags();
155 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
156 AM.ES = S->getSymbol();
157 //AM.SymbolFlags = S->getTargetFlags();
158 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
159 AM.JT = J->getIndex();
160 //AM.SymbolFlags = J->getTargetFlags();
162 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
163 //AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
168 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
169 /// specified addressing mode without any further recursion.
170 bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) {
171 // Is the base register already occupied?
172 if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
173 // If so, we cannot select it.
177 // Default, generate it as a register.
178 AM.BaseType = MSP430ISelAddressMode::RegBase;
183 bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
184 LLVM_DEBUG(errs() << "MatchAddress: "; AM.dump());
186 switch (N.getOpcode()) {
188 case ISD::Constant: {
189 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
194 case MSP430ISD::Wrapper:
195 if (!MatchWrapper(N, AM))
199 case ISD::FrameIndex:
200 if (AM.BaseType == MSP430ISelAddressMode::RegBase
201 && AM.Base.Reg.getNode() == nullptr) {
202 AM.BaseType = MSP430ISelAddressMode::FrameIndexBase;
203 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
209 MSP430ISelAddressMode Backup = AM;
210 if (!MatchAddress(N.getNode()->getOperand(0), AM) &&
211 !MatchAddress(N.getNode()->getOperand(1), AM))
214 if (!MatchAddress(N.getNode()->getOperand(1), AM) &&
215 !MatchAddress(N.getNode()->getOperand(0), AM))
223 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
224 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
225 MSP430ISelAddressMode Backup = AM;
226 uint64_t Offset = CN->getSExtValue();
227 // Start with the LHS as an addr mode.
228 if (!MatchAddress(N.getOperand(0), AM) &&
229 // Address could not have picked a GV address for the displacement.
231 // Check to see if the LHS & C is zero.
232 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
241 return MatchAddressBase(N, AM);
244 /// SelectAddr - returns true if it is able pattern match an addressing mode.
245 /// It returns the operands which make up the maximal addressing mode it can
246 /// match by reference.
247 bool MSP430DAGToDAGISel::SelectAddr(SDValue N,
248 SDValue &Base, SDValue &Disp) {
249 MSP430ISelAddressMode AM;
251 if (MatchAddress(N, AM))
254 if (AM.BaseType == MSP430ISelAddressMode::RegBase)
255 if (!AM.Base.Reg.getNode())
256 AM.Base.Reg = CurDAG->getRegister(MSP430::SR, MVT::i16);
258 Base = (AM.BaseType == MSP430ISelAddressMode::FrameIndexBase)
259 ? CurDAG->getTargetFrameIndex(
261 getTargetLowering()->getPointerTy(CurDAG->getDataLayout()))
265 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(N),
267 0/*AM.SymbolFlags*/);
269 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16,
270 AM.Align, AM.Disp, 0/*AM.SymbolFlags*/);
272 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/);
273 else if (AM.JT != -1)
274 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/);
275 else if (AM.BlockAddr)
276 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, 0,
277 0/*AM.SymbolFlags*/);
279 Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(N), MVT::i16);
284 bool MSP430DAGToDAGISel::
285 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
286 std::vector<SDValue> &OutOps) {
288 switch (ConstraintID) {
289 default: return true;
290 case InlineAsm::Constraint_m: // memory
291 if (!SelectAddr(Op, Op0, Op1))
296 OutOps.push_back(Op0);
297 OutOps.push_back(Op1);
301 static bool isValidIndexedLoad(const LoadSDNode *LD) {
302 ISD::MemIndexedMode AM = LD->getAddressingMode();
303 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD)
306 EVT VT = LD->getMemoryVT();
308 switch (VT.getSimpleVT().SimpleTy) {
311 if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 1)
317 if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 2)
328 bool MSP430DAGToDAGISel::tryIndexedLoad(SDNode *N) {
329 LoadSDNode *LD = cast<LoadSDNode>(N);
330 if (!isValidIndexedLoad(LD))
333 MVT VT = LD->getMemoryVT().getSimpleVT();
336 switch (VT.SimpleTy) {
338 Opcode = MSP430::MOV8rp;
341 Opcode = MSP430::MOV16rp;
348 CurDAG->getMachineNode(Opcode, SDLoc(N), VT, MVT::i16, MVT::Other,
349 LD->getBasePtr(), LD->getChain()));
353 bool MSP430DAGToDAGISel::tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
354 unsigned Opc8, unsigned Opc16) {
355 if (N1.getOpcode() == ISD::LOAD &&
357 IsLegalToFold(N1, Op, Op, OptLevel)) {
358 LoadSDNode *LD = cast<LoadSDNode>(N1);
359 if (!isValidIndexedLoad(LD))
362 MVT VT = LD->getMemoryVT().getSimpleVT();
363 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
364 MachineMemOperand *MemRef = cast<MemSDNode>(N1)->getMemOperand();
365 SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() };
367 CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0);
368 CurDAG->setNodeMemRefs(cast<MachineSDNode>(ResNode), {MemRef});
370 ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2));
371 // Transfer writeback.
372 ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
380 void MSP430DAGToDAGISel::Select(SDNode *Node) {
383 // If we have a custom node, we already have selected!
384 if (Node->isMachineOpcode()) {
385 LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
390 // Few custom selection stuff.
391 switch (Node->getOpcode()) {
393 case ISD::FrameIndex: {
394 assert(Node->getValueType(0) == MVT::i16);
395 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
396 SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
397 if (Node->hasOneUse()) {
398 CurDAG->SelectNodeTo(Node, MSP430::ADDframe, MVT::i16, TFI,
399 CurDAG->getTargetConstant(0, dl, MVT::i16));
402 ReplaceNode(Node, CurDAG->getMachineNode(
403 MSP430::ADDframe, dl, MVT::i16, TFI,
404 CurDAG->getTargetConstant(0, dl, MVT::i16)));
408 if (tryIndexedLoad(Node))
410 // Other cases are autogenerated.
413 if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
414 MSP430::ADD8rp, MSP430::ADD16rp))
416 else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
417 MSP430::ADD8rp, MSP430::ADD16rp))
420 // Other cases are autogenerated.
423 if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
424 MSP430::SUB8rp, MSP430::SUB16rp))
427 // Other cases are autogenerated.
430 if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
431 MSP430::AND8rp, MSP430::AND16rp))
433 else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
434 MSP430::AND8rp, MSP430::AND16rp))
437 // Other cases are autogenerated.
440 if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
441 MSP430::BIS8rp, MSP430::BIS16rp))
443 else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
444 MSP430::BIS8rp, MSP430::BIS16rp))
447 // Other cases are autogenerated.
450 if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
451 MSP430::XOR8rp, MSP430::XOR16rp))
453 else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
454 MSP430::XOR8rp, MSP430::XOR16rp))
457 // Other cases are autogenerated.
461 // Select the default instruction