1 //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This class prints an Mips MCInst to a .s file.
11 //===----------------------------------------------------------------------===//
13 #include "MipsInstPrinter.h"
14 #include "MipsInstrInfo.h"
15 #include "MipsMCExpr.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCSymbol.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define DEBUG_TYPE "asm-printer"
27 #define PRINT_ALIAS_INSTR
28 #include "MipsGenAsmWriter.inc"
31 static bool isReg(const MCInst &MI, unsigned OpNo) {
32 assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
33 return MI.getOperand(OpNo).getReg() == R;
36 const char* Mips::MipsFCCToString(Mips::CondCode CC) {
39 case FCOND_T: return "f";
41 case FCOND_OR: return "un";
43 case FCOND_UNE: return "eq";
45 case FCOND_ONE: return "ueq";
47 case FCOND_UGE: return "olt";
49 case FCOND_OGE: return "ult";
51 case FCOND_UGT: return "ole";
53 case FCOND_OGT: return "ule";
55 case FCOND_ST: return "sf";
57 case FCOND_GLE: return "ngle";
59 case FCOND_SNE: return "seq";
61 case FCOND_GL: return "ngl";
63 case FCOND_NLT: return "lt";
65 case FCOND_GE: return "nge";
67 case FCOND_NLE: return "le";
69 case FCOND_GT: return "ngt";
71 llvm_unreachable("Impossible condition code!");
74 void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
75 OS << '$' << StringRef(getRegisterName(RegNo)).lower();
78 void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
79 StringRef Annot, const MCSubtargetInfo &STI) {
80 switch (MI->getOpcode()) {
85 O << "\t.set\tpush\n";
86 O << "\t.set\tmips32r2\n";
90 printSaveRestore(MI, O);
91 O << " # 16 bit inst\n";
95 printSaveRestore(MI, O);
100 printSaveRestore(MI, O);
101 O << " # 16 bit inst\n";
103 case Mips::RestoreX16:
105 printSaveRestore(MI, O);
110 // Try to print any aliases first.
111 if (!printAliasInstr(MI, O) && !printAlias(*MI, O))
112 printInstruction(MI, O);
113 printAnnotation(O, Annot);
115 switch (MI->getOpcode()) {
120 O << "\n\t.set\tpop";
124 void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
126 const MCOperand &Op = MI->getOperand(OpNo);
128 printRegName(O, Op.getReg());
133 O << formatImm(Op.getImm());
137 assert(Op.isExpr() && "unknown operand kind in printOperand");
138 Op.getExpr()->print(O, &MAI, true);
141 template <unsigned Bits, unsigned Offset>
142 void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
143 const MCOperand &MO = MI->getOperand(opNum);
145 uint64_t Imm = MO.getImm();
147 Imm &= (1 << Bits) - 1;
153 printOperand(MI, opNum, O);
156 void MipsInstPrinter::
157 printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) {
158 // Load/Store memory operands -- imm($reg)
159 // If PIC target the target is loaded as the
160 // pattern lw $25,%call16($28)
162 // opNum can be invalid if instruction had reglist as operand.
163 // MemOperand is always last operand of instruction (base + offset).
164 switch (MI->getOpcode()) {
170 case Mips::SWM16_MMR6:
172 case Mips::LWM16_MMR6:
173 opNum = MI->getNumOperands() - 2;
177 printOperand(MI, opNum+1, O);
179 printOperand(MI, opNum, O);
183 void MipsInstPrinter::
184 printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) {
185 // when using stack locations for not load/store instructions
186 // print the same way as all normal 3 operand instructions.
187 printOperand(MI, opNum, O);
189 printOperand(MI, opNum+1, O);
192 void MipsInstPrinter::
193 printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) {
194 const MCOperand& MO = MI->getOperand(opNum);
195 O << MipsFCCToString((Mips::CondCode)MO.getImm());
198 void MipsInstPrinter::
199 printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) {
200 llvm_unreachable("TODO");
203 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
204 unsigned OpNo, raw_ostream &OS) {
205 OS << "\t" << Str << "\t";
206 printOperand(&MI, OpNo, OS);
210 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
211 unsigned OpNo0, unsigned OpNo1,
213 printAlias(Str, MI, OpNo0, OS);
215 printOperand(&MI, OpNo1, OS);
219 bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
220 switch (MI.getOpcode()) {
223 // beq $zero, $zero, $L2 => b $L2
224 // beq $r0, $zero, $L2 => beqz $r0, $L2
225 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
226 printAlias("b", MI, 2, OS)) ||
227 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
229 // beq $r0, $zero, $L2 => beqz $r0, $L2
230 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
233 // bne $r0, $zero, $L2 => bnez $r0, $L2
234 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
236 // bne $r0, $zero, $L2 => bnez $r0, $L2
237 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
239 // bgezal $zero, $L1 => bal $L1
240 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS);
242 // bc1t $fcc0, $L1 => bc1t $L1
243 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS);
245 // bc1f $fcc0, $L1 => bc1f $L1
246 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS);
248 // jalr $ra, $r1 => jalr $r1
249 return isReg<Mips::RA>(MI, 0) && printAlias("jalr", MI, 1, OS);
251 // jalr $ra, $r1 => jalr $r1
252 return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS);
256 // nor $r0, $r1, $zero => not $r0, $r1
257 return isReg<Mips::ZERO>(MI, 2) && printAlias("not", MI, 0, 1, OS);
259 // nor $r0, $r1, $zero => not $r0, $r1
260 return isReg<Mips::ZERO_64>(MI, 2) && printAlias("not", MI, 0, 1, OS);
262 // or $r0, $r1, $zero => move $r0, $r1
263 return isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS);
264 default: return false;
268 void MipsInstPrinter::printSaveRestore(const MCInst *MI, raw_ostream &O) {
269 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
270 if (i != 0) O << ", ";
271 if (MI->getOperand(i).isReg())
272 printRegName(O, MI->getOperand(i).getReg());
274 printUImm<16>(MI, i, O);
278 void MipsInstPrinter::
279 printRegisterList(const MCInst *MI, int opNum, raw_ostream &O) {
280 // - 2 because register List is always first operand of instruction and it is
281 // always followed by memory operand (base + offset).
282 for (int i = opNum, e = MI->getNumOperands() - 2; i != e; ++i) {
285 printRegName(O, MI->getOperand(i).getReg());