1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements the MipsMCCodeEmitter class.
11 //===----------------------------------------------------------------------===//
13 #include "MipsMCCodeEmitter.h"
14 #include "MCTargetDesc/MipsFixupKinds.h"
15 #include "MCTargetDesc/MipsMCExpr.h"
16 #include "MCTargetDesc/MipsMCTargetDesc.h"
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCFixup.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrDesc.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Support/Casting.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
36 #define DEBUG_TYPE "mccodeemitter"
38 #define GET_INSTRMAP_INFO
39 #include "MipsGenInstrInfo.inc"
40 #undef GET_INSTRMAP_INFO
44 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
45 const MCRegisterInfo &MRI,
47 return new MipsMCCodeEmitter(MCII, Ctx, false);
50 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
51 const MCRegisterInfo &MRI,
53 return new MipsMCCodeEmitter(MCII, Ctx, true);
56 } // end namespace llvm
58 // If the D<shift> instruction has a shift amount that is greater
59 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
60 static void LowerLargeShift(MCInst& Inst) {
61 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
62 assert(Inst.getOperand(2).isImm());
64 int64_t Shift = Inst.getOperand(2).getImm();
70 Inst.getOperand(2).setImm(Shift);
72 switch (Inst.getOpcode()) {
74 // Calling function is not synchronized
75 llvm_unreachable("Unexpected shift instruction");
77 Inst.setOpcode(Mips::DSLL32);
80 Inst.setOpcode(Mips::DSRL32);
83 Inst.setOpcode(Mips::DSRA32);
86 Inst.setOpcode(Mips::DROTR32);
91 // Fix a bad compact branch encoding for beqc/bnec.
92 void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
93 // Encoding may be illegal !(rs < rt), but this situation is
95 unsigned RegOp0 = Inst.getOperand(0).getReg();
96 unsigned RegOp1 = Inst.getOperand(1).getReg();
98 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0);
99 unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1);
101 if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC ||
102 Inst.getOpcode() == Mips::BNEC64 || Inst.getOpcode() == Mips::BEQC64) {
103 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!");
106 } else if (Inst.getOpcode() == Mips::BNVC || Inst.getOpcode() == Mips::BOVC) {
109 } else if (Inst.getOpcode() == Mips::BNVC_MMR6 ||
110 Inst.getOpcode() == Mips::BOVC_MMR6) {
114 llvm_unreachable("Cannot rewrite unknown branch!");
116 Inst.getOperand(0).setReg(RegOp1);
117 Inst.getOperand(1).setReg(RegOp0);
120 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
121 return STI.getFeatureBits()[Mips::FeatureMicroMips];
124 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
125 return STI.getFeatureBits()[Mips::FeatureMips32r6];
128 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
132 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
133 const MCSubtargetInfo &STI,
134 raw_ostream &OS) const {
135 // Output the instruction encoding in little endian byte order.
136 // Little-endian byte ordering:
137 // mips32r2: 4 | 3 | 2 | 1
138 // microMIPS: 2 | 1 | 4 | 3
139 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
140 EmitInstruction(Val >> 16, 2, STI, OS);
141 EmitInstruction(Val, 2, STI, OS);
143 for (unsigned i = 0; i < Size; ++i) {
144 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
145 EmitByte((Val >> Shift) & 0xff, OS);
150 /// encodeInstruction - Emit the instruction.
151 /// Size the instruction with Desc.getSize().
152 void MipsMCCodeEmitter::
153 encodeInstruction(const MCInst &MI, raw_ostream &OS,
154 SmallVectorImpl<MCFixup> &Fixups,
155 const MCSubtargetInfo &STI) const
157 // Non-pseudo instructions that get changed for direct object
158 // only based on operand values.
159 // If this list of instructions get much longer we will move
160 // the check to a function call. Until then, this is more efficient.
162 switch (MI.getOpcode()) {
163 // If shift amount is >= 32 it the inst needs to be lowered further
168 LowerLargeShift(TmpInst);
170 // Compact branches, enforce encoding restrictions.
176 case Mips::BOVC_MMR6:
178 case Mips::BNVC_MMR6:
179 LowerCompactBranch(TmpInst);
182 unsigned long N = Fixups.size();
183 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
185 // Check for unimplemented opcodes.
186 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
187 // so we have to special check for them.
188 const unsigned Opcode = TmpInst.getOpcode();
189 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
190 (Opcode != Mips::SLL_MM) && (Opcode != Mips::SLL_MMR6) && !Binary)
191 llvm_unreachable("unimplemented opcode in encodeInstruction()");
194 if (isMicroMips(STI)) {
195 if (isMips32r6(STI)) {
196 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
198 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
201 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
203 // Check whether it is Dsp instruction.
205 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp);
207 if (NewOpcode != -1) {
208 if (Fixups.size() > N)
211 TmpInst.setOpcode (NewOpcode);
212 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
215 if (((MI.getOpcode() == Mips::MOVEP_MM) ||
216 (MI.getOpcode() == Mips::MOVEP_MMR6))) {
217 unsigned RegPair = getMovePRegPairOpValue(MI, 0, Fixups, STI);
218 Binary = (Binary & 0xFFFFFC7F) | (RegPair << 7);
222 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
224 // Get byte count of instruction
225 unsigned Size = Desc.getSize();
227 llvm_unreachable("Desc.getSize() returns 0");
229 EmitInstruction(Binary, Size, STI, OS);
232 /// getBranchTargetOpValue - Return binary encoding of the branch
233 /// target operand. If the machine operand requires relocation,
234 /// record the relocation and return zero.
235 unsigned MipsMCCodeEmitter::
236 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
237 SmallVectorImpl<MCFixup> &Fixups,
238 const MCSubtargetInfo &STI) const {
239 const MCOperand &MO = MI.getOperand(OpNo);
241 // If the destination is an immediate, divide by 4.
242 if (MO.isImm()) return MO.getImm() >> 2;
244 assert(MO.isExpr() &&
245 "getBranchTargetOpValue expects only expressions or immediates");
247 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
248 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
249 Fixups.push_back(MCFixup::create(0, FixupExpression,
250 MCFixupKind(Mips::fixup_Mips_PC16)));
254 /// getBranchTargetOpValue1SImm16 - Return binary encoding of the branch
255 /// target operand. If the machine operand requires relocation,
256 /// record the relocation and return zero.
257 unsigned MipsMCCodeEmitter::
258 getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo,
259 SmallVectorImpl<MCFixup> &Fixups,
260 const MCSubtargetInfo &STI) const {
261 const MCOperand &MO = MI.getOperand(OpNo);
263 // If the destination is an immediate, divide by 2.
264 if (MO.isImm()) return MO.getImm() >> 1;
266 assert(MO.isExpr() &&
267 "getBranchTargetOpValue expects only expressions or immediates");
269 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
270 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
271 Fixups.push_back(MCFixup::create(0, FixupExpression,
272 MCFixupKind(Mips::fixup_Mips_PC16)));
276 /// getBranchTargetOpValueMMR6 - Return binary encoding of the branch
277 /// target operand. If the machine operand requires relocation,
278 /// record the relocation and return zero.
279 unsigned MipsMCCodeEmitter::
280 getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo,
281 SmallVectorImpl<MCFixup> &Fixups,
282 const MCSubtargetInfo &STI) const {
283 const MCOperand &MO = MI.getOperand(OpNo);
285 // If the destination is an immediate, divide by 2.
287 return MO.getImm() >> 1;
289 assert(MO.isExpr() &&
290 "getBranchTargetOpValueMMR6 expects only expressions or immediates");
292 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
293 MO.getExpr(), MCConstantExpr::create(-2, Ctx), Ctx);
294 Fixups.push_back(MCFixup::create(0, FixupExpression,
295 MCFixupKind(Mips::fixup_Mips_PC16)));
299 /// getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch
300 /// target operand. If the machine operand requires relocation,
301 /// record the relocation and return zero.
302 unsigned MipsMCCodeEmitter::
303 getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo,
304 SmallVectorImpl<MCFixup> &Fixups,
305 const MCSubtargetInfo &STI) const {
306 const MCOperand &MO = MI.getOperand(OpNo);
308 // If the destination is an immediate, divide by 4.
310 return MO.getImm() >> 2;
312 assert(MO.isExpr() &&
313 "getBranchTargetOpValueLsl2MMR6 expects only expressions or immediates");
315 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
316 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
317 Fixups.push_back(MCFixup::create(0, FixupExpression,
318 MCFixupKind(Mips::fixup_Mips_PC16)));
322 /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch
323 /// target operand. If the machine operand requires relocation,
324 /// record the relocation and return zero.
325 unsigned MipsMCCodeEmitter::
326 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
327 SmallVectorImpl<MCFixup> &Fixups,
328 const MCSubtargetInfo &STI) const {
329 const MCOperand &MO = MI.getOperand(OpNo);
331 // If the destination is an immediate, divide by 2.
332 if (MO.isImm()) return MO.getImm() >> 1;
334 assert(MO.isExpr() &&
335 "getBranchTargetOpValueMM expects only expressions or immediates");
337 const MCExpr *Expr = MO.getExpr();
338 Fixups.push_back(MCFixup::create(0, Expr,
339 MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
343 /// getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS
344 /// 10-bit branch target operand. If the machine operand requires relocation,
345 /// record the relocation and return zero.
346 unsigned MipsMCCodeEmitter::
347 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
348 SmallVectorImpl<MCFixup> &Fixups,
349 const MCSubtargetInfo &STI) const {
350 const MCOperand &MO = MI.getOperand(OpNo);
352 // If the destination is an immediate, divide by 2.
353 if (MO.isImm()) return MO.getImm() >> 1;
355 assert(MO.isExpr() &&
356 "getBranchTargetOpValuePC10 expects only expressions or immediates");
358 const MCExpr *Expr = MO.getExpr();
359 Fixups.push_back(MCFixup::create(0, Expr,
360 MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
364 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
365 /// target operand. If the machine operand requires relocation,
366 /// record the relocation and return zero.
367 unsigned MipsMCCodeEmitter::
368 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
369 SmallVectorImpl<MCFixup> &Fixups,
370 const MCSubtargetInfo &STI) const {
371 const MCOperand &MO = MI.getOperand(OpNo);
373 // If the destination is an immediate, divide by 2.
374 if (MO.isImm()) return MO.getImm() >> 1;
376 assert(MO.isExpr() &&
377 "getBranchTargetOpValueMM expects only expressions or immediates");
379 const MCExpr *Expr = MO.getExpr();
380 Fixups.push_back(MCFixup::create(0, Expr,
382 fixup_MICROMIPS_PC16_S1)));
386 /// getBranchTarget21OpValue - Return binary encoding of the branch
387 /// target operand. If the machine operand requires relocation,
388 /// record the relocation and return zero.
389 unsigned MipsMCCodeEmitter::
390 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
391 SmallVectorImpl<MCFixup> &Fixups,
392 const MCSubtargetInfo &STI) const {
393 const MCOperand &MO = MI.getOperand(OpNo);
395 // If the destination is an immediate, divide by 4.
396 if (MO.isImm()) return MO.getImm() >> 2;
398 assert(MO.isExpr() &&
399 "getBranchTarget21OpValue expects only expressions or immediates");
401 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
402 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
403 Fixups.push_back(MCFixup::create(0, FixupExpression,
404 MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
408 /// getBranchTarget21OpValueMM - Return binary encoding of the branch
409 /// target operand for microMIPS. If the machine operand requires
410 /// relocation, record the relocation and return zero.
411 unsigned MipsMCCodeEmitter::
412 getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
413 SmallVectorImpl<MCFixup> &Fixups,
414 const MCSubtargetInfo &STI) const {
415 const MCOperand &MO = MI.getOperand(OpNo);
417 // If the destination is an immediate, divide by 4.
418 if (MO.isImm()) return MO.getImm() >> 2;
420 assert(MO.isExpr() &&
421 "getBranchTarget21OpValueMM expects only expressions or immediates");
423 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
424 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
425 Fixups.push_back(MCFixup::create(0, FixupExpression,
426 MCFixupKind(Mips::fixup_MICROMIPS_PC21_S1)));
430 /// getBranchTarget26OpValue - Return binary encoding of the branch
431 /// target operand. If the machine operand requires relocation,
432 /// record the relocation and return zero.
433 unsigned MipsMCCodeEmitter::
434 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
435 SmallVectorImpl<MCFixup> &Fixups,
436 const MCSubtargetInfo &STI) const {
437 const MCOperand &MO = MI.getOperand(OpNo);
439 // If the destination is an immediate, divide by 4.
440 if (MO.isImm()) return MO.getImm() >> 2;
442 assert(MO.isExpr() &&
443 "getBranchTarget26OpValue expects only expressions or immediates");
445 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
446 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
447 Fixups.push_back(MCFixup::create(0, FixupExpression,
448 MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
452 /// getBranchTarget26OpValueMM - Return binary encoding of the branch
453 /// target operand. If the machine operand requires relocation,
454 /// record the relocation and return zero.
455 unsigned MipsMCCodeEmitter::getBranchTarget26OpValueMM(
456 const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
457 const MCSubtargetInfo &STI) const {
458 const MCOperand &MO = MI.getOperand(OpNo);
460 // If the destination is an immediate, divide by 2.
462 return MO.getImm() >> 1;
464 assert(MO.isExpr() &&
465 "getBranchTarget26OpValueMM expects only expressions or immediates");
467 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
468 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
469 Fixups.push_back(MCFixup::create(0, FixupExpression,
470 MCFixupKind(Mips::fixup_MICROMIPS_PC26_S1)));
474 /// getJumpOffset16OpValue - Return binary encoding of the jump
475 /// target operand. If the machine operand requires relocation,
476 /// record the relocation and return zero.
477 unsigned MipsMCCodeEmitter::
478 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
479 SmallVectorImpl<MCFixup> &Fixups,
480 const MCSubtargetInfo &STI) const {
481 const MCOperand &MO = MI.getOperand(OpNo);
483 if (MO.isImm()) return MO.getImm();
485 assert(MO.isExpr() &&
486 "getJumpOffset16OpValue expects only expressions or an immediate");
488 const MCExpr *Expr = MO.getExpr();
489 Mips::Fixups FixupKind =
490 isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16 : Mips::fixup_Mips_LO16;
491 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
495 /// getJumpTargetOpValue - Return binary encoding of the jump
496 /// target operand. If the machine operand requires relocation,
497 /// record the relocation and return zero.
498 unsigned MipsMCCodeEmitter::
499 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
500 SmallVectorImpl<MCFixup> &Fixups,
501 const MCSubtargetInfo &STI) const {
502 const MCOperand &MO = MI.getOperand(OpNo);
503 // If the destination is an immediate, divide by 4.
504 if (MO.isImm()) return MO.getImm()>>2;
506 assert(MO.isExpr() &&
507 "getJumpTargetOpValue expects only expressions or an immediate");
509 const MCExpr *Expr = MO.getExpr();
510 Fixups.push_back(MCFixup::create(0, Expr,
511 MCFixupKind(Mips::fixup_Mips_26)));
515 unsigned MipsMCCodeEmitter::
516 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
517 SmallVectorImpl<MCFixup> &Fixups,
518 const MCSubtargetInfo &STI) const {
519 const MCOperand &MO = MI.getOperand(OpNo);
520 // If the destination is an immediate, divide by 2.
521 if (MO.isImm()) return MO.getImm() >> 1;
523 assert(MO.isExpr() &&
524 "getJumpTargetOpValueMM expects only expressions or an immediate");
526 const MCExpr *Expr = MO.getExpr();
527 Fixups.push_back(MCFixup::create(0, Expr,
528 MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
532 unsigned MipsMCCodeEmitter::
533 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
534 SmallVectorImpl<MCFixup> &Fixups,
535 const MCSubtargetInfo &STI) const {
536 const MCOperand &MO = MI.getOperand(OpNo);
538 // The immediate is encoded as 'immediate << 2'.
539 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
540 assert((Res & 3) == 0);
544 assert(MO.isExpr() &&
545 "getUImm5Lsl2Encoding expects only expressions or an immediate");
550 unsigned MipsMCCodeEmitter::
551 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
552 SmallVectorImpl<MCFixup> &Fixups,
553 const MCSubtargetInfo &STI) const {
554 const MCOperand &MO = MI.getOperand(OpNo);
556 int Value = MO.getImm();
563 unsigned MipsMCCodeEmitter::
564 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
565 SmallVectorImpl<MCFixup> &Fixups,
566 const MCSubtargetInfo &STI) const {
567 const MCOperand &MO = MI.getOperand(OpNo);
569 unsigned Value = MO.getImm();
576 unsigned MipsMCCodeEmitter::
577 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
578 SmallVectorImpl<MCFixup> &Fixups,
579 const MCSubtargetInfo &STI) const {
580 const MCOperand &MO = MI.getOperand(OpNo);
582 unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
583 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
589 unsigned MipsMCCodeEmitter::
590 getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
591 const MCSubtargetInfo &STI) const {
594 if (Expr->evaluateAsAbsolute(Res))
597 MCExpr::ExprKind Kind = Expr->getKind();
598 if (Kind == MCExpr::Constant) {
599 return cast<MCConstantExpr>(Expr)->getValue();
602 if (Kind == MCExpr::Binary) {
604 getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
605 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
609 if (Kind == MCExpr::Target) {
610 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
612 Mips::Fixups FixupKind = Mips::Fixups(0);
613 switch (MipsExpr->getKind()) {
614 case MipsMCExpr::MEK_None:
615 case MipsMCExpr::MEK_Special:
616 llvm_unreachable("Unhandled fixup kind!");
618 case MipsMCExpr::MEK_DTPREL:
619 // MEK_DTPREL is used for marking TLS DIEExpr only
620 // and contains a regular sub-expression.
621 return getExprOpValue(MipsExpr->getSubExpr(), Fixups, STI);
622 case MipsMCExpr::MEK_CALL_HI16:
623 FixupKind = Mips::fixup_Mips_CALL_HI16;
625 case MipsMCExpr::MEK_CALL_LO16:
626 FixupKind = Mips::fixup_Mips_CALL_LO16;
628 case MipsMCExpr::MEK_DTPREL_HI:
629 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
630 : Mips::fixup_Mips_DTPREL_HI;
632 case MipsMCExpr::MEK_DTPREL_LO:
633 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
634 : Mips::fixup_Mips_DTPREL_LO;
636 case MipsMCExpr::MEK_GOTTPREL:
637 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOTTPREL
638 : Mips::fixup_Mips_GOTTPREL;
640 case MipsMCExpr::MEK_GOT:
641 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
642 : Mips::fixup_Mips_GOT;
644 case MipsMCExpr::MEK_GOT_CALL:
645 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
646 : Mips::fixup_Mips_CALL16;
648 case MipsMCExpr::MEK_GOT_DISP:
649 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
650 : Mips::fixup_Mips_GOT_DISP;
652 case MipsMCExpr::MEK_GOT_HI16:
653 FixupKind = Mips::fixup_Mips_GOT_HI16;
655 case MipsMCExpr::MEK_GOT_LO16:
656 FixupKind = Mips::fixup_Mips_GOT_LO16;
658 case MipsMCExpr::MEK_GOT_PAGE:
659 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
660 : Mips::fixup_Mips_GOT_PAGE;
662 case MipsMCExpr::MEK_GOT_OFST:
663 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
664 : Mips::fixup_Mips_GOT_OFST;
666 case MipsMCExpr::MEK_GPREL:
667 FixupKind = Mips::fixup_Mips_GPREL16;
669 case MipsMCExpr::MEK_LO:
670 // Check for %lo(%neg(%gp_rel(X)))
671 if (MipsExpr->isGpOff())
672 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GPOFF_LO
673 : Mips::fixup_Mips_GPOFF_LO;
675 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
676 : Mips::fixup_Mips_LO16;
678 case MipsMCExpr::MEK_HIGHEST:
679 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HIGHEST
680 : Mips::fixup_Mips_HIGHEST;
682 case MipsMCExpr::MEK_HIGHER:
683 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HIGHER
684 : Mips::fixup_Mips_HIGHER;
686 case MipsMCExpr::MEK_HI:
687 // Check for %hi(%neg(%gp_rel(X)))
688 if (MipsExpr->isGpOff())
689 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GPOFF_HI
690 : Mips::fixup_Mips_GPOFF_HI;
692 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
693 : Mips::fixup_Mips_HI16;
695 case MipsMCExpr::MEK_PCREL_HI16:
696 FixupKind = Mips::fixup_MIPS_PCHI16;
698 case MipsMCExpr::MEK_PCREL_LO16:
699 FixupKind = Mips::fixup_MIPS_PCLO16;
701 case MipsMCExpr::MEK_TLSGD:
702 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
703 : Mips::fixup_Mips_TLSGD;
705 case MipsMCExpr::MEK_TLSLDM:
706 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
707 : Mips::fixup_Mips_TLSLDM;
709 case MipsMCExpr::MEK_TPREL_HI:
710 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
711 : Mips::fixup_Mips_TPREL_HI;
713 case MipsMCExpr::MEK_TPREL_LO:
714 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
715 : Mips::fixup_Mips_TPREL_LO;
717 case MipsMCExpr::MEK_NEG:
719 isMicroMips(STI) ? Mips::fixup_MICROMIPS_SUB : Mips::fixup_Mips_SUB;
722 Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind)));
726 if (Kind == MCExpr::SymbolRef) {
727 Mips::Fixups FixupKind = Mips::Fixups(0);
729 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
730 default: llvm_unreachable("Unknown fixup kind!");
732 case MCSymbolRefExpr::VK_None:
733 // FIXME: This is ok for O32/N32 but not N64.
734 FixupKind = Mips::fixup_Mips_32;
738 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
744 /// getMachineOpValue - Return binary encoding of operand. If the machine
745 /// operand requires relocation, record the relocation and return zero.
746 unsigned MipsMCCodeEmitter::
747 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
748 SmallVectorImpl<MCFixup> &Fixups,
749 const MCSubtargetInfo &STI) const {
751 unsigned Reg = MO.getReg();
752 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
754 } else if (MO.isImm()) {
755 return static_cast<unsigned>(MO.getImm());
756 } else if (MO.isFPImm()) {
757 return static_cast<unsigned>(APFloat(MO.getFPImm())
758 .bitcastToAPInt().getHiBits(32).getLimitedValue());
760 // MO must be an Expr.
762 return getExprOpValue(MO.getExpr(),Fixups, STI);
765 /// Return binary encoding of memory related operand.
766 /// If the offset operand requires relocation, record the relocation.
767 template <unsigned ShiftAmount>
768 unsigned MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
769 SmallVectorImpl<MCFixup> &Fixups,
770 const MCSubtargetInfo &STI) const {
771 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
772 assert(MI.getOperand(OpNo).isReg());
773 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)
775 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
777 // Apply the scale factor if there is one.
778 OffBits >>= ShiftAmount;
780 return (OffBits & 0xFFFF) | RegBits;
783 unsigned MipsMCCodeEmitter::
784 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
785 SmallVectorImpl<MCFixup> &Fixups,
786 const MCSubtargetInfo &STI) const {
787 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
788 assert(MI.getOperand(OpNo).isReg());
789 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
791 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
794 return (OffBits & 0xF) | RegBits;
797 unsigned MipsMCCodeEmitter::
798 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
799 SmallVectorImpl<MCFixup> &Fixups,
800 const MCSubtargetInfo &STI) const {
801 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
802 assert(MI.getOperand(OpNo).isReg());
803 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
805 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
808 return (OffBits & 0xF) | RegBits;
811 unsigned MipsMCCodeEmitter::
812 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
813 SmallVectorImpl<MCFixup> &Fixups,
814 const MCSubtargetInfo &STI) const {
815 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
816 assert(MI.getOperand(OpNo).isReg());
817 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
819 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
822 return (OffBits & 0xF) | RegBits;
825 unsigned MipsMCCodeEmitter::
826 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
827 SmallVectorImpl<MCFixup> &Fixups,
828 const MCSubtargetInfo &STI) const {
829 // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
830 assert(MI.getOperand(OpNo).isReg() &&
831 (MI.getOperand(OpNo).getReg() == Mips::SP ||
832 MI.getOperand(OpNo).getReg() == Mips::SP_64) &&
833 "Unexpected base register!");
834 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
837 return OffBits & 0x1F;
840 unsigned MipsMCCodeEmitter::
841 getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
842 SmallVectorImpl<MCFixup> &Fixups,
843 const MCSubtargetInfo &STI) const {
844 // Register is encoded in bits 9-7, offset is encoded in bits 6-0.
845 assert(MI.getOperand(OpNo).isReg() &&
846 MI.getOperand(OpNo).getReg() == Mips::GP &&
847 "Unexpected base register!");
849 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
852 return OffBits & 0x7F;
855 unsigned MipsMCCodeEmitter::
856 getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
857 SmallVectorImpl<MCFixup> &Fixups,
858 const MCSubtargetInfo &STI) const {
859 // Base register is encoded in bits 20-16, offset is encoded in bits 8-0.
860 assert(MI.getOperand(OpNo).isReg());
861 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
864 getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI);
866 return (OffBits & 0x1FF) | RegBits;
869 unsigned MipsMCCodeEmitter::
870 getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo,
871 SmallVectorImpl<MCFixup> &Fixups,
872 const MCSubtargetInfo &STI) const {
873 // Base register is encoded in bits 20-16, offset is encoded in bits 10-0.
874 assert(MI.getOperand(OpNo).isReg());
875 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
877 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
879 return (OffBits & 0x07FF) | RegBits;
882 unsigned MipsMCCodeEmitter::
883 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
884 SmallVectorImpl<MCFixup> &Fixups,
885 const MCSubtargetInfo &STI) const {
886 // opNum can be invalid if instruction had reglist as operand.
887 // MemOperand is always last operand of instruction (base + offset).
888 switch (MI.getOpcode()) {
893 OpNo = MI.getNumOperands() - 2;
897 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
898 assert(MI.getOperand(OpNo).isReg());
899 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)
901 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
903 return (OffBits & 0x0FFF) | RegBits;
906 unsigned MipsMCCodeEmitter::
907 getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo,
908 SmallVectorImpl<MCFixup> &Fixups,
909 const MCSubtargetInfo &STI) const {
910 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
911 assert(MI.getOperand(OpNo).isReg());
912 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
914 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
916 return (OffBits & 0xFFFF) | RegBits;
919 unsigned MipsMCCodeEmitter::
920 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
921 SmallVectorImpl<MCFixup> &Fixups,
922 const MCSubtargetInfo &STI) const {
923 // opNum can be invalid if instruction had reglist as operand
924 // MemOperand is always last operand of instruction (base + offset)
925 switch (MI.getOpcode()) {
929 case Mips::SWM16_MMR6:
931 case Mips::LWM16_MMR6:
932 OpNo = MI.getNumOperands() - 2;
936 // Offset is encoded in bits 4-0.
937 assert(MI.getOperand(OpNo).isReg());
938 // Base register is always SP - thus it is not encoded.
939 assert(MI.getOperand(OpNo+1).isImm());
940 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
942 return ((OffBits >> 2) & 0x0F);
945 // FIXME: should be called getMSBEncoding
948 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
949 SmallVectorImpl<MCFixup> &Fixups,
950 const MCSubtargetInfo &STI) const {
951 assert(MI.getOperand(OpNo-1).isImm());
952 assert(MI.getOperand(OpNo).isImm());
953 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
954 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
956 return Position + Size - 1;
959 template <unsigned Bits, int Offset>
961 MipsMCCodeEmitter::getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo,
962 SmallVectorImpl<MCFixup> &Fixups,
963 const MCSubtargetInfo &STI) const {
964 assert(MI.getOperand(OpNo).isImm());
965 unsigned Value = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
971 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
972 SmallVectorImpl<MCFixup> &Fixups,
973 const MCSubtargetInfo &STI) const {
974 const MCOperand &MO = MI.getOperand(OpNo);
976 // The immediate is encoded as 'immediate << 2'.
977 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
978 assert((Res & 3) == 0);
982 assert(MO.isExpr() &&
983 "getSimm19Lsl2Encoding expects only expressions or an immediate");
985 const MCExpr *Expr = MO.getExpr();
986 Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC19_S2
987 : Mips::fixup_MIPS_PC19_S2;
988 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
993 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
994 SmallVectorImpl<MCFixup> &Fixups,
995 const MCSubtargetInfo &STI) const {
996 const MCOperand &MO = MI.getOperand(OpNo);
998 // The immediate is encoded as 'immediate << 3'.
999 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
1000 assert((Res & 7) == 0);
1004 assert(MO.isExpr() &&
1005 "getSimm18Lsl2Encoding expects only expressions or an immediate");
1007 const MCExpr *Expr = MO.getExpr();
1008 Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC18_S3
1009 : Mips::fixup_MIPS_PC18_S3;
1010 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
1015 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
1016 SmallVectorImpl<MCFixup> &Fixups,
1017 const MCSubtargetInfo &STI) const {
1018 assert(MI.getOperand(OpNo).isImm());
1019 const MCOperand &MO = MI.getOperand(OpNo);
1020 return MO.getImm() % 8;
1024 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
1025 SmallVectorImpl<MCFixup> &Fixups,
1026 const MCSubtargetInfo &STI) const {
1027 assert(MI.getOperand(OpNo).isImm());
1028 const MCOperand &MO = MI.getOperand(OpNo);
1029 unsigned Value = MO.getImm();
1031 case 128: return 0x0;
1038 case 15: return 0x7;
1039 case 16: return 0x8;
1040 case 31: return 0x9;
1041 case 32: return 0xa;
1042 case 63: return 0xb;
1043 case 64: return 0xc;
1044 case 255: return 0xd;
1045 case 32768: return 0xe;
1046 case 65535: return 0xf;
1048 llvm_unreachable("Unexpected value");
1052 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
1053 SmallVectorImpl<MCFixup> &Fixups,
1054 const MCSubtargetInfo &STI) const {
1057 // Register list operand is always first operand of instruction and it is
1058 // placed before memory operand (register + imm).
1060 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
1061 unsigned Reg = MI.getOperand(I).getReg();
1062 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
1072 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
1073 SmallVectorImpl<MCFixup> &Fixups,
1074 const MCSubtargetInfo &STI) const {
1075 return (MI.getNumOperands() - 4);
1079 MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
1080 SmallVectorImpl<MCFixup> &Fixups,
1081 const MCSubtargetInfo &STI) const {
1084 if (MI.getOperand(0).getReg() == Mips::A1 &&
1085 MI.getOperand(1).getReg() == Mips::A2)
1087 else if (MI.getOperand(0).getReg() == Mips::A1 &&
1088 MI.getOperand(1).getReg() == Mips::A3)
1090 else if (MI.getOperand(0).getReg() == Mips::A2 &&
1091 MI.getOperand(1).getReg() == Mips::A3)
1093 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1094 MI.getOperand(1).getReg() == Mips::S5)
1096 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1097 MI.getOperand(1).getReg() == Mips::S6)
1099 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1100 MI.getOperand(1).getReg() == Mips::A1)
1102 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1103 MI.getOperand(1).getReg() == Mips::A2)
1105 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1106 MI.getOperand(1).getReg() == Mips::A3)
1113 MipsMCCodeEmitter::getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo,
1114 SmallVectorImpl<MCFixup> &Fixups,
1115 const MCSubtargetInfo &STI) const {
1116 assert(((OpNo == 2) || (OpNo == 3)) &&
1117 "Unexpected OpNo for movep operand encoding!");
1119 MCOperand Op = MI.getOperand(OpNo);
1120 assert(Op.isReg() && "Operand of movep is not a register!");
1121 switch (Op.getReg()) {
1123 llvm_unreachable("Unknown register for movep!");
1124 case Mips::ZERO: return 0;
1125 case Mips::S1: return 1;
1126 case Mips::V0: return 2;
1127 case Mips::V1: return 3;
1128 case Mips::S0: return 4;
1129 case Mips::S2: return 5;
1130 case Mips::S3: return 6;
1131 case Mips::S4: return 7;
1136 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
1137 SmallVectorImpl<MCFixup> &Fixups,
1138 const MCSubtargetInfo &STI) const {
1139 const MCOperand &MO = MI.getOperand(OpNo);
1140 assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate");
1141 // The immediate is encoded as 'immediate >> 2'.
1142 unsigned Res = static_cast<unsigned>(MO.getImm());
1143 assert((Res & 3) == 0);
1147 #include "MipsGenMCCodeEmitter.inc"