contrib/llvm-project/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td

   1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file describes microMIPSr6 instructions.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 def brtarget21_mm : Operand<OtherVT> {
  14   let EncoderMethod = "getBranchTarget21OpValueMM";
  15   let OperandType = "OPERAND_PCREL";
  16   let DecoderMethod = "DecodeBranchTarget21MM";
  17   let ParserMatchClass = MipsJumpTargetAsmOperand;
  18 }
  19
  20 def brtarget26_mm : Operand<OtherVT> {
  21   let EncoderMethod = "getBranchTarget26OpValueMM";
  22   let OperandType = "OPERAND_PCREL";
  23   let DecoderMethod = "DecodeBranchTarget26MM";
  24   let ParserMatchClass = MipsJumpTargetAsmOperand;
  25 }
  26
  27 def brtargetr6 : Operand<OtherVT> {
  28   let EncoderMethod = "getBranchTargetOpValueMMR6";
  29   let OperandType = "OPERAND_PCREL";
  30   let DecoderMethod = "DecodeBranchTargetMM";
  31   let ParserMatchClass = MipsJumpTargetAsmOperand;
  32 }
  33
  34 def brtarget_lsl2_mm : Operand<OtherVT> {
  35   let EncoderMethod = "getBranchTargetOpValueLsl2MMR6";
  36   let OperandType = "OPERAND_PCREL";
  37   // Instructions that use this operand have their decoder method
  38   // set with DecodeDisambiguates
  39   let DecoderMethod = "";
  40   let ParserMatchClass = MipsJumpTargetAsmOperand;
  41 }
  42
  43 //===----------------------------------------------------------------------===//
  44 //
  45 // Instruction Encodings
  46 //
  47 //===----------------------------------------------------------------------===//
  48 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
  49 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
  50 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
  51 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
  52 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
  53 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
  54 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
  55 class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
  56 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
  57 class AUI_MMR6_ENC : AUI_FM_MMR6;
  58 class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
  59 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
  60 class BC16_MMR6_ENC : BC16_FM_MM16R6;
  61 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
  62 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
  63 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
  64 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
  65 class BEQZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"beqzc", 0b100000>;
  66 class BNEZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"bnezc", 0b101000>;
  67 class BGEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgec", 0b111101>,
  68                       DecodeDisambiguates<"POP75GroupBranchMMR6">;
  69 class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>,
  70                        DecodeDisambiguates<"BlezGroupBranchMMR6">;
  71 class BLTC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltc", 0b110101>,
  72                       DecodeDisambiguates<"POP65GroupBranchMMR6">;
  73 class BLTUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltuc", 0b111000>,
  74                        DecodeDisambiguates<"BgtzGroupBranchMMR6">;
  75 class BEQC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"beqc", 0b011101>;
  76 class BNEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bnec", 0b011111>;
  77 class BLTZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzc", 0b110101>,
  78                        DecodeDisambiguates<"POP65GroupBranchMMR6">;
  79 class BLEZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezc", 0b111101>,
  80                        DecodeDisambiguates<"POP75GroupBranchMMR6">;
  81 class BGEZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezc", 0b111101>,
  82                        DecodeDisambiguates<"POP75GroupBranchMMR6">;
  83 class BGTZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzc", 0b110101>,
  84                        DecodeDisambiguates<"POP65GroupBranchMMR6">;
  85 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"beqzalc", 0b011101>,
  86                          DecodeDisambiguates<"POP35GroupBranchMMR6">;
  87 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bnezalc", 0b011111>,
  88                          DecodeDisambiguates<"POP37GroupBranchMMR6">;
  89 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzalc", 0b111000>,
  90                          MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
  91 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzalc", 0b111000>,
  92                          MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
  93 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezalc", 0b110000>,
  94                          MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
  95 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezalc", 0b110000>,
  96                          MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
  97 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
  98 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
  99 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
 100 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
 101 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
 102 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
 103 class EI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"ei", 0x15d>;
 104 class DI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"di", 0b0100011101>;
 105 class ERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0x3cd>;
 106 class DERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0b1110001101>;
 107 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
 108 class GINVI_MMR6_ENC : POOL32A_GINV_FM_MMR6<"ginvi", 0b00>;
 109 class GINVT_MMR6_ENC : POOL32A_GINV_FM_MMR6<"ginvt", 0b10>;
 110 class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
 111 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
 112 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
 113 class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
 114 class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
 115 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
 116 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
 117 class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>;
 118 class MFC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfc0", 0b00011, 0b111100>;
 119 class MFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfc1", 0b10000000>;
 120 class MFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfc2", 0b0100110100>;
 121 class MFHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfhc0", 0b00011, 0b110100>;
 122 class MFHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfhc2", 0b1000110100>;
 123 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
 124 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
 125 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
 126 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
 127 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
 128 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
 129 class MTC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mtc0", 0b01011, 0b111100>;
 130 class MTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mtc1", 0b10100000>;
 131 class MTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mtc2", 0b0101110100>;
 132 class MTHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mthc0", 0b01011, 0b110100>;
 133 class MTHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mthc2", 0b1001110100>;
 134 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
 135 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
 136 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
 137 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
 138 class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>;
 139 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
 140 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
 141 class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>;
 142 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
 143 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
 144 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
 145 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
 146 class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>;
 147 class SWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0xa>;
 148 class SWSP_MMR6_ENC : LOAD_STORE_SP_FM_MM16<0x32>;
 149 class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<"wrpgpr", 0x3c5>;
 150 class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<"wsbh", 0x1ec>;
 151 class LB_MMR6_ENC : LB32_FM_MMR6;
 152 class LBU_MMR6_ENC : LBU32_FM_MMR6;
 153 class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>;
 154 class RDHWR_MMR6_ENC : POOL32A_RDHWR_FM_MMR6;
 155 class WAIT_MMR6_ENC : WAIT_FM_MM, MMR6Arch<"wait">;
 156 class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">;
 157 class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
 158 class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
 159 class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
 160 class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
 161 class SIGRIE_MMR6_ENC : SIGRIE_FM_MM, MMR6Arch<"sigrie">;
 162 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
 163 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
 164 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
 165 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
 166 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
 167 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
 168 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
 169 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
 170 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
 171 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
 172 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
 173 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
 174 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
 175 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
 176 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
 177 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
 178 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
 179 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
 180 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
 181 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
 182 class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>;
 183 class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
 184 class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
 185 class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
 186                                                        0b11001100>;
 187 class ROUND_L_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1,
 188                                                        0b11001100>;
 189 class ROUND_W_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.s", 0,
 190                                                        0b11101100>;
 191 class ROUND_W_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.d", 1,
 192                                                        0b11101100>;
 193 class SEL_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.s", 0, 0b010111000>;
 194 class SEL_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.d", 1, 0b010111000>;
 195 class SELEQZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.s", 0, 0b000111000>;
 196 class SELEQZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.d", 1, 0b000111000>;
 197 class SELNEZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.s", 0, 0b001111000>;
 198 class SELNEZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.d", 1, 0b001111000>;
 199 class CLASS_S_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.s", 0, 0b001100000>;
 200 class CLASS_D_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.d", 1, 0b001100000>;
 201 class EXT_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ext", 0b101100>;
 202 class INS_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ins", 0b001100>;
 203 class JALRC_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc", 0b0000111100>;
 204 class BOVC_MMR6_ENC : POP35_BOVC_FM_MMR6<"bovc">;
 205 class BNVC_MMR6_ENC : POP37_BNVC_FM_MMR6<"bnvc">;
 206 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
 207 class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
 208 class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>;
 209 class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
 210 class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
 211 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>;
 212 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>;
 213 class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
 214 class LI16_MMR6_ENC : LI_FM_MM16;
 215 class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
 216 class MOVEP_MMR6_ENC  : POOL16C_MOVEP16_FM_MMR6;
 217 class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
 218 class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
 219 class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
 220 class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>;
 221 class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>;
 222 class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>;
 223 class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>;
 224 class BC1EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1eqzc", 0b01000>;
 225 class BC1NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1nezc", 0b01001>;
 226 class BC2EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2eqzc", 0b01010>;
 227 class BC2NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2nezc", 0b01011>;
 228 class LDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"ldc1", 0b101111>;
 229 class SDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"sdc1", 0b101110>;
 230 class LDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"ldc2", 0b0010>;
 231 class SDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"sdc2", 0b1010>;
 232 class LWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"lwc2", 0b0000>;
 233 class SWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"swc2", 0b1000>;
 234
 235 class LL_MMR6_ENC  : POOL32C_LL_E_SC_E_FM_MMR6<"ll", 0b0011, 0b000>;
 236 class SC_MMR6_ENC  : POOL32C_LL_E_SC_E_FM_MMR6<"sc", 0b1011, 0b000>;
 237
 238 /// Floating Point Instructions
 239 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
 240 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
 241 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
 242 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
 243 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
 244 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
 245 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
 246 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
 247 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
 248 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
 249 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
 250 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
 251 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
 252 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
 253 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
 254 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
 255 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
 256 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
 257 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
 258
 259 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
 260 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
 261 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
 262 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
 263 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
 264 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
 265
 266 //===----------------------------------------------------------------------===//
 267 //
 268 // Instruction Descriptions
 269 //
 270 //===----------------------------------------------------------------------===//
 271
 272 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
 273                                   RegisterOperand GPROpnd>
 274     : BRANCH_DESC_BASE {
 275   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 276   dag OutOperandList = (outs);
 277   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
 278   list<Register> Defs = [AT];
 279   InstrItinClass Itinerary = II_BCCZC;
 280 }
 281
 282 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
 283                                                       GPR32Opnd> {
 284   list<Register> Defs = [RA];
 285 }
 286
 287 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
 288                                                       GPR32Opnd> {
 289   list<Register> Defs = [RA];
 290 }
 291
 292 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
 293                                                       GPR32Opnd> {
 294   list<Register> Defs = [RA];
 295 }
 296
 297 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
 298                                                       GPR32Opnd> {
 299   list<Register> Defs = [RA];
 300 }
 301
 302 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
 303                                                       GPR32Opnd> {
 304   list<Register> Defs = [RA];
 305 }
 306
 307 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
 308                                                       GPR32Opnd> {
 309   list<Register> Defs = [RA];
 310 }
 311
 312 class BLTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzc", brtarget_lsl2_mm,
 313                                                     GPR32Opnd>;
 314 class BLEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezc", brtarget_lsl2_mm,
 315                                                     GPR32Opnd>;
 316 class BGEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezc", brtarget_lsl2_mm,
 317                                                     GPR32Opnd>;
 318 class BGTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzc", brtarget_lsl2_mm,
 319                                                     GPR32Opnd>;
 320
 321 class CMP_CBR_2R_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
 322                                 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
 323   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
 324   dag OutOperandList = (outs);
 325   string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
 326   list<Register> Defs = [AT];
 327   InstrItinClass Itinerary = II_BCCC;
 328 }
 329
 330 class BGEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgec", brtarget_lsl2_mm,
 331                                                  GPR32Opnd>;
 332 class BGEUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgeuc", brtarget_lsl2_mm,
 333                                                  GPR32Opnd>;
 334 class BLTC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltc", brtarget_lsl2_mm,
 335                                                  GPR32Opnd>;
 336 class BLTUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltuc", brtarget_lsl2_mm,
 337                                                  GPR32Opnd>;
 338 class BEQC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"beqc", brtarget_lsl2_mm,
 339                                                  GPR32Opnd>;
 340 class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_lsl2_mm,
 341                                                  GPR32Opnd>;
 342
 343 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd, 1, II_ADD>;
 344 class ADDIU_MMR6_DESC
 345     : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
 346 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU>;
 347 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>;
 348 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUH, mulhs>;
 349 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd, 1, II_MULU>;
 350 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>;
 351
 352 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, InstrItinClass Itin>
 353     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 354   dag InOperandList = (ins opnd:$offset);
 355   dag OutOperandList = (outs);
 356   string AsmString = !strconcat(instr_asm, "\t$offset");
 357   bit isBarrier = 1;
 358   InstrItinClass Itinerary = Itin;
 359 }
 360
 361 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm, II_BALC> {
 362   bit isCall = 1;
 363   list<Register> Defs = [RA];
 364 }
 365 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm, II_BC> {
 366   list<dag> Pattern = [(br bb:$offset)];
 367 }
 368
 369 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
 370                                        !strconcat("bc16", "\t$offset"), [],
 371                                        II_BC, FrmI>,
 372                        MMR6Arch<"bc16"> {
 373   let isBranch = 1;
 374   let isTerminator = 1;
 375   let isBarrier = 1;
 376   let hasDelaySlot = 0;
 377   let AdditionalPredicates = [RelocPIC];
 378   let Defs = [AT];
 379 }
 380
 381 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
 382     : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>,
 383       MMR6Arch<instr_asm> {
 384   let isBranch = 1;
 385   let isTerminator = 1;
 386   let hasDelaySlot = 0;
 387   let Defs = [AT];
 388 }
 389 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
 390 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
 391
 392 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>;
 393 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd, 0,II_SUBU>;
 394
 395 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 396     : MMR6Arch<instr_asm> {
 397   dag OutOperandList = (outs GPROpnd:$rd);
 398   dag InOperandList = (ins GPROpnd:$rt);
 399   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 400   list<dag> Pattern = [];
 401   InstrItinClass Itinerary = II_BITSWAP;
 402 }
 403
 404 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
 405
 406 class BRK_MMR6_DESC : BRK_FT<"break">;
 407
 408 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
 409                            RegisterOperand GPROpnd, InstrItinClass Itin>
 410       : MMR6Arch<instr_asm> {
 411   dag OutOperandList = (outs);
 412   dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
 413   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
 414   list<dag> Pattern = [];
 415   string DecoderMethod = "DecodeCacheOpMM";
 416   InstrItinClass Itinerary = Itin;
 417 }
 418
 419 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd,
 420                                              II_CACHE>;
 421 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd,
 422                                              II_PREF>;
 423
 424 class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 425                             RegisterOperand GPROpnd, InstrItinClass Itin>
 426     : MMR6Arch<instr_asm> {
 427   dag OutOperandList = (outs GPROpnd:$rt);
 428   dag InOperandList = (ins MemOpnd:$addr);
 429   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 430   string DecoderMethod = "DecodeLoadByte15";
 431   bit mayLoad = 1;
 432   InstrItinClass Itinerary = Itin;
 433 }
 434 class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd, II_LB>;
 435 class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd,
 436                                             II_LBU>;
 437
 438 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 439                              InstrItinClass Itin> : MMR6Arch<instr_asm> {
 440   dag OutOperandList = (outs GPROpnd:$rt);
 441   dag InOperandList = (ins GPROpnd:$rs);
 442   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 443   InstrItinClass Itinerary = Itin;
 444 }
 445
 446 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd, II_CLO>;
 447 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>;
 448
 449 class EHB_MMR6_DESC : Barrier<"ehb", II_EHB>;
 450 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd, II_EI>;
 451 class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd, II_DI>;
 452
 453 class ERET_MMR6_DESC : ER_FT<"eret", II_ERET>;
 454 class DERET_MMR6_DESC : ER_FT<"deret", II_DERET>;
 455 class ERETNC_MMR6_DESC : ER_FT<"eretnc", II_ERETNC>;
 456
 457 class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
 458     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
 459                       [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
 460       MMR6Arch<opstr> {
 461   let isCall = 1;
 462   let hasDelaySlot = 0;
 463   let Defs = [RA];
 464   let hasPostISelHook = 1;
 465 }
 466 class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
 467
 468 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
 469                                      RegisterOperand GPROpnd,
 470                                      InstrItinClass Itin>
 471     : MMR6Arch<opstr> {
 472   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 473   string AsmString = !strconcat(opstr, "\t$rt, $offset");
 474   list<dag> Pattern = [];
 475   bit isTerminator = 1;
 476   bit hasDelaySlot = 0;
 477   InstrItinClass Itinerary = Itin;
 478 }
 479
 480 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
 481                                                        GPR32Opnd, II_JIALC> {
 482   bit isCall = 1;
 483   list<Register> Defs = [RA];
 484 }
 485
 486 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
 487                                                      GPR32Opnd, II_JIC> {
 488   bit isBarrier = 1;
 489   list<Register> Defs = [AT];
 490 }
 491
 492 class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
 493     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
 494                       [], II_JR, FrmR>,
 495       MMR6Arch<opstr> {
 496   let hasDelaySlot = 0;
 497   let isBranch = 1;
 498   let isIndirectBranch = 1;
 499 }
 500 class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>;
 501
 502 class JRCADDIUSP_MMR6_DESC
 503     : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
 504                       [], II_JRADDIUSP, FrmR>,
 505       MMR6Arch<"jrcaddiusp"> {
 506   let hasDelaySlot = 0;
 507   let isTerminator = 1;
 508   let isBarrier = 1;
 509   let isBranch = 1;
 510   let isIndirectBranch = 1;
 511 }
 512
 513 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 514                       Operand ImmOpnd, InstrItinClass Itin>
 515     : MMR6Arch<instr_asm> {
 516   dag OutOperandList = (outs GPROpnd:$rd);
 517   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
 518   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
 519   list<dag> Pattern = [];
 520   InstrItinClass Itinerary = Itin;
 521 }
 522
 523 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2,
 524                                              II_ALIGN>;
 525
 526 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 527                          InstrItinClass Itin> : MMR6Arch<instr_asm> {
 528   dag OutOperandList = (outs GPROpnd:$rt);
 529   dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
 530   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
 531   list<dag> Pattern = [];
 532   InstrItinClass Itinerary = Itin;
 533 }
 534
 535 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
 536
 537 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 538                             InstrItinClass Itin> : MMR6Arch<instr_asm> {
 539   dag OutOperandList = (outs GPROpnd:$rt);
 540   dag InOperandList = (ins simm16:$imm);
 541   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 542   list<dag> Pattern = [];
 543   InstrItinClass Itinerary = Itin;
 544 }
 545
 546 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>;
 547 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>;
 548
 549 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 550                          Operand ImmOpnd, InstrItinClass Itin>
 551     : MMR6Arch<instr_asm> {
 552   dag OutOperandList = (outs GPROpnd:$rd);
 553   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
 554   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
 555   list<dag> Pattern = [];
 556   InstrItinClass Itinerary = Itin;
 557 }
 558
 559 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;
 560
 561 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 562                            Operand ImmOpnd, InstrItinClass Itin>
 563     : MMR6Arch<instr_asm> {
 564   dag OutOperandList = (outs GPROpnd:$rt);
 565   dag InOperandList = (ins ImmOpnd:$imm);
 566   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 567   list<dag> Pattern = [];
 568   InstrItinClass Itinerary = Itin;
 569 }
 570
 571 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd,
 572                                                simm19_lsl2, II_ADDIUPC>;
 573 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2,
 574                                            II_LWPC>;
 575
 576 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 577                                InstrItinClass Itin> : MMR6Arch<instr_asm> {
 578   dag OutOperandList = (outs GPROpnd:$rd);
 579   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
 580   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 581   list<dag> Pattern = [];
 582   InstrItinClass Itinerary = Itin;
 583 }
 584
 585 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd,
 586                                                   II_SELCCZ>;
 587 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd,
 588                                                   II_SELCCZ>;
 589 class PAUSE_MMR6_DESC : Barrier<"pause", II_PAUSE>;
 590 class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
 591   dag OutOperandList = (outs GPR32Opnd:$rt);
 592   dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel);
 593   string AsmString = !strconcat("rdhwr", "\t$rt, $rs, $sel");
 594   list<dag> Pattern = [];
 595   InstrItinClass Itinerary = II_RDHWR;
 596   Format Form = FrmR;
 597 }
 598
 599 class WAIT_MMR6_DESC : WaitMM<"wait">;
 600 // FIXME: ssnop should not be defined for R6. Per MD000582 microMIPS32 6.03:
 601 //        Assemblers targeting specifically Release 6 should reject the SSNOP
 602 //        instruction with an error.
 603 class SSNOP_MMR6_DESC : Barrier<"ssnop", II_SSNOP>;
 604 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
 605
 606 class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
 607                             InstrItinClass Itin,
 608                             SDPatternOperator OpNode=null_frag>
 609     : MipsR6Inst {
 610   dag OutOperandList = (outs GPROpnd:$rd);
 611   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
 612   string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
 613   list<dag> Pattern = [(set GPROpnd:$rd, (OpNode GPROpnd:$rs, GPROpnd:$rt))];
 614   string BaseOpcode = opstr;
 615   Format f = FrmR;
 616   let isCommutable = 0;
 617   let isReMaterializable = 1;
 618   InstrItinClass Itinerary = Itin;
 619
 620   // This instruction doesn't trap division by zero itself. We must insert
 621   // teq instructions as well.
 622   bit usesCustomInserter = 1;
 623 }
 624 class DIV_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>;
 625 class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>;
 626 class MOD_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>;
 627 class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>;
 628 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>;
 629 class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>;
 630 class NOR_MMR6_DESC : LogicNOR<"nor", GPR32Opnd>;
 631 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>;
 632 class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
 633                                   or> {
 634   int AddedComplexity = 1;
 635 }
 636 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>;
 637 class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
 638                                    immZExt16, xor>;
 639 class SW_MMR6_DESC : Store<"sw", GPR32Opnd> {
 640   InstrItinClass Itinerary = II_SW;
 641 }
 642 class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
 643                                  InstrItinClass Itin> {
 644   dag InOperandList = (ins RO:$rs);
 645   dag OutOperandList = (outs RO:$rt);
 646   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 647   list<dag> Pattern = [];
 648   Format f = FrmR;
 649   string BaseOpcode = instr_asm;
 650   bit hasSideEffects = 0;
 651   InstrItinClass Itinerary = Itin;
 652 }
 653 class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd,
 654                                                     II_WRPGPR>;
 655 class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd, II_WSBH>;
 656
 657 class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 658                          RegisterOperand SrcRC, InstrItinClass Itin> {
 659   dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
 660   dag OutOperandList = (outs DstRC:$rs);
 661   string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
 662   list<dag> Pattern = [];
 663   Format f = FrmFR;
 664   string BaseOpcode = opstr;
 665   InstrItinClass Itinerary = Itin;
 666 }
 667 class MTC1_MMR6_DESC_BASE<
 668       string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
 669       InstrItinClass Itin = NoItinerary, SDPatternOperator OpNode = null_frag>
 670       : MipsR6Inst {
 671   dag InOperandList = (ins SrcRC:$rt);
 672   dag OutOperandList = (outs DstRC:$fs);
 673   string AsmString = !strconcat(opstr, "\t$rt, $fs");
 674   list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
 675   Format f = FrmFR;
 676   InstrItinClass Itinerary = Itin;
 677   string BaseOpcode = opstr;
 678 }
 679 class MTC1_64_MMR6_DESC_BASE<
 680       string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
 681       InstrItinClass Itin = NoItinerary> : MipsR6Inst {
 682   dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
 683   dag OutOperandList = (outs DstRC:$fs);
 684   string AsmString = !strconcat(opstr, "\t$rt, $fs");
 685   list<dag> Pattern = [];
 686   Format f = FrmFR;
 687   InstrItinClass Itinerary = Itin;
 688   string BaseOpcode = opstr;
 689   // $fs_in is part of a white lie to work around a widespread bug in the FPU
 690   // implementation. See expandBuildPairF64 for details.
 691   let Constraints = "$fs = $fs_in";
 692 }
 693 class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 694                          RegisterOperand SrcRC, InstrItinClass Itin> {
 695   dag InOperandList = (ins SrcRC:$rt);
 696   dag OutOperandList = (outs DstRC:$impl);
 697   string AsmString = !strconcat(opstr, "\t$rt, $impl");
 698   list<dag> Pattern = [];
 699   Format f = FrmFR;
 700   string BaseOpcode = opstr;
 701   InstrItinClass Itinerary = Itin;
 702 }
 703
 704 class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd,
 705                                            II_MTC0>;
 706 class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd,
 707                                            II_MTC1, bitconvert>, HARDFLOAT;
 708 class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd,
 709                                            II_MTC2>;
 710 class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd,
 711                                             II_MTHC0>;
 712 class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd,
 713                                             II_MTC2>;
 714
 715 class MFC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 716                           RegisterOperand SrcRC, InstrItinClass Itin> {
 717   dag InOperandList = (ins SrcRC:$rs, uimm3:$sel);
 718   dag OutOperandList = (outs DstRC:$rt);
 719   string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
 720   list<dag> Pattern = [];
 721   Format f = FrmFR;
 722   string BaseOpcode = opstr;
 723   InstrItinClass Itinerary = Itin;
 724 }
 725 class MFC1_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 726                           RegisterOperand SrcRC,
 727                           InstrItinClass Itin = NoItinerary,
 728                           SDPatternOperator OpNode = null_frag> : MipsR6Inst {
 729   dag InOperandList = (ins SrcRC:$fs);
 730   dag OutOperandList = (outs DstRC:$rt);
 731   string AsmString = !strconcat(opstr, "\t$rt, $fs");
 732   list<dag> Pattern = [(set DstRC:$rt, (OpNode SrcRC:$fs))];
 733   Format f = FrmFR;
 734   InstrItinClass Itinerary = Itin;
 735   string BaseOpcode = opstr;
 736 }
 737 class MFC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 738                           RegisterOperand SrcRC, InstrItinClass Itin> {
 739   dag InOperandList = (ins SrcRC:$impl);
 740   dag OutOperandList = (outs DstRC:$rt);
 741   string AsmString = !strconcat(opstr, "\t$rt, $impl");
 742   list<dag> Pattern = [];
 743   Format f = FrmFR;
 744   string BaseOpcode = opstr;
 745   InstrItinClass Itinerary = Itin;
 746 }
 747 class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd,
 748                                            II_MFC0>;
 749 class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd,
 750                                            II_MFC1, bitconvert>, HARDFLOAT;
 751 class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd,
 752                                            II_MFC2>;
 753 class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd,
 754                                             II_MFHC0>;
 755 class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd,
 756                                             II_MFC2>;
 757
 758 class LDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
 759   dag InOperandList = (ins mem_mm_16:$addr);
 760   dag OutOperandList = (outs FGR64Opnd:$ft);
 761   string AsmString = !strconcat("ldc1", "\t$ft, $addr");
 762   list<dag> Pattern = [(set FGR64Opnd:$ft, (load addrimm16:$addr))];
 763   Format f = FrmFI;
 764   InstrItinClass Itinerary = II_LDC1;
 765   string BaseOpcode = "ldc1";
 766   bit mayLoad = 1;
 767   let DecoderMethod = "DecodeFMemMMR2";
 768 }
 769
 770 class SDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
 771   dag InOperandList = (ins FGR64Opnd:$ft, mem_mm_16:$addr);
 772   dag OutOperandList = (outs);
 773   string AsmString = !strconcat("sdc1", "\t$ft, $addr");
 774   list<dag> Pattern = [(store FGR64Opnd:$ft, addrimm16:$addr)];
 775   Format f = FrmFI;
 776   InstrItinClass Itinerary = II_SDC1;
 777   string BaseOpcode = "sdc1";
 778   bit mayStore = 1;
 779   let DecoderMethod = "DecodeFMemMMR2";
 780 }
 781
 782 class LDC2_LWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
 783   dag OutOperandList = (outs COP2Opnd:$rt);
 784   dag InOperandList = (ins mem_mm_11:$addr);
 785   string AsmString = !strconcat(opstr, "\t$rt, $addr");
 786   list<dag> Pattern = [(set COP2Opnd:$rt, (load addrimm11:$addr))];
 787   Format f = FrmFI;
 788   InstrItinClass Itinerary = itin;
 789   string BaseOpcode = opstr;
 790   bit mayLoad = 1;
 791   string DecoderMethod = "DecodeFMemCop2MMR6";
 792 }
 793 class LDC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"ldc2", II_LDC2>;
 794 class LWC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"lwc2", II_LWC2>;
 795
 796 class SDC2_SWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
 797   dag OutOperandList = (outs);
 798   dag InOperandList = (ins COP2Opnd:$rt, mem_mm_11:$addr);
 799   string AsmString = !strconcat(opstr, "\t$rt, $addr");
 800   list<dag> Pattern = [(store COP2Opnd:$rt, addrimm11:$addr)];
 801   Format f = FrmFI;
 802   InstrItinClass Itinerary = itin;
 803   string BaseOpcode = opstr;
 804   bit mayStore = 1;
 805   string DecoderMethod = "DecodeFMemCop2MMR6";
 806 }
 807 class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2", II_SDC2>;
 808 class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2", II_SWC2>;
 809
 810 class GINV_MMR6_DESC_BASE<string opstr,
 811                           RegisterOperand SrcRC, InstrItinClass Itin> {
 812   dag InOperandList = (ins SrcRC:$rs, uimm2:$type);
 813   dag OutOperandList = (outs);
 814   string AsmString = !strconcat(opstr, "\t$rs, $type");
 815   list<dag> Pattern = [];
 816   Format f = FrmFR;
 817   string BaseOpcode = opstr;
 818   InstrItinClass Itinerary = Itin;
 819 }
 820
 821 class GINVI_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvi", GPR32Opnd,
 822                                             II_GINVI> {
 823   dag InOperandList = (ins GPR32Opnd:$rs);
 824   string AsmString = "ginvi\t$rs";
 825 }
 826 class GINVT_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvt", GPR32Opnd,
 827                                             II_GINVT>;
 828
 829 class SC_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
 830   dag OutOperandList = (outs GPR32Opnd:$dst);
 831   dag InOperandList = (ins GPR32Opnd:$rt, mem_mm_9:$addr);
 832   string AsmString = !strconcat(opstr, "\t$rt, $addr");
 833   InstrItinClass Itinerary = itin;
 834   string BaseOpcode = opstr;
 835   bit mayStore = 1;
 836   string Constraints = "$rt = $dst";
 837   string DecoderMethod = "DecodeMemMMImm9";
 838 }
 839
 840 class LL_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
 841   dag OutOperandList = (outs GPR32Opnd:$rt);
 842   dag InOperandList = (ins mem_mm_9:$addr);
 843   string AsmString = !strconcat(opstr, "\t$rt, $addr");
 844   InstrItinClass Itinerary = itin;
 845   string BaseOpcode = opstr;
 846   bit mayLoad = 1;
 847   string DecoderMethod = "DecodeMemMMImm9";
 848 }
 849
 850 class SC_MMR6_DESC : SC_MMR6_DESC_BASE<"sc", II_SC>;
 851 class LL_MMR6_DESC : LL_MMR6_DESC_BASE<"ll", II_LL>;
 852
 853 /// Floating Point Instructions
 854 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
 855                             InstrItinClass Itin, bit isComm,
 856                             SDPatternOperator OpNode = null_frag> : HARDFLOAT {
 857   dag OutOperandList = (outs RC:$fd);
 858   dag InOperandList = (ins RC:$ft, RC:$fs);
 859   string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
 860   list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
 861   InstrItinClass Itinerary = Itin;
 862   bit isCommutable = isComm;
 863 }
 864 class FADD_S_MMR6_DESC
 865   : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
 866 class FSUB_S_MMR6_DESC
 867   : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
 868 class FMUL_S_MMR6_DESC
 869   : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
 870 class FDIV_S_MMR6_DESC
 871   : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
 872 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd,
 873                                             II_MADDF_S>, HARDFLOAT;
 874 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd,
 875                                             II_MADDF_D>, HARDFLOAT;
 876 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd,
 877                                             II_MSUBF_S>, HARDFLOAT;
 878 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd,
 879                                             II_MSUBF_D>, HARDFLOAT;
 880
 881 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 882                                RegisterOperand SrcRC, InstrItinClass Itin,
 883                                SDPatternOperator OpNode = null_frag>
 884                                : HARDFLOAT, NeverHasSideEffects {
 885   dag OutOperandList = (outs DstRC:$ft);
 886   dag InOperandList = (ins SrcRC:$fs);
 887   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 888   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 889   InstrItinClass Itinerary = Itin;
 890   Format Form = FrmFR;
 891 }
 892 class FMOV_S_MMR6_DESC
 893   : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
 894 class FMOV_D_MMR6_DESC
 895   : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>;
 896 class FNEG_S_MMR6_DESC
 897   : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
 898
 899 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>,
 900                         HARDFLOAT;
 901 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>,
 902                         HARDFLOAT;
 903 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>,
 904                         HARDFLOAT;
 905 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>,
 906                         HARDFLOAT;
 907
 908 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAXA_S>,
 909                          HARDFLOAT;
 910 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAXA_D>,
 911                          HARDFLOAT;
 912 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MINA_S>,
 913                          HARDFLOAT;
 914 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MINA_D>,
 915                          HARDFLOAT;
 916
 917 class CVT_MMR6_DESC_BASE<
 918     string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
 919     InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
 920     : HARDFLOAT, NeverHasSideEffects {
 921   dag OutOperandList = (outs DstRC:$ft);
 922   dag InOperandList = (ins SrcRC:$fs);
 923   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 924   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 925   InstrItinClass Itinerary = Itin;
 926   Format Form = FrmFR;
 927 }
 928
 929 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
 930                                              II_CVT>;
 931 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
 932                                              II_CVT>;
 933 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
 934                                              II_CVT>;
 935 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
 936                                              II_CVT>, FGR_64;
 937 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
 938                                              II_CVT>;
 939 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
 940                                              II_CVT>, FGR_64;
 941
 942 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
 943                        RegisterOperand FGROpnd, InstrItinClass Itin> {
 944   def CMP_AF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 945       !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
 946       CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, Itin>, HARDFLOAT,
 947       ISA_MICROMIPS32R6;
 948   def CMP_UN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 949       !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
 950       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, Itin, setuo>, HARDFLOAT,
 951       ISA_MICROMIPS32R6;
 952   def CMP_EQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 953       !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
 954       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, Itin, setoeq>, HARDFLOAT,
 955       ISA_MICROMIPS32R6;
 956   def CMP_UEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 957       !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
 958       CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, Itin, setueq>, HARDFLOAT,
 959       ISA_MICROMIPS32R6;
 960   def CMP_LT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 961       !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
 962       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, Itin, setolt>, HARDFLOAT,
 963       ISA_MICROMIPS32R6;
 964   def CMP_ULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 965       !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
 966       CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, Itin, setult>, HARDFLOAT,
 967       ISA_MICROMIPS32R6;
 968   def CMP_LE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 969       !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
 970       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, Itin, setole>, HARDFLOAT,
 971       ISA_MICROMIPS32R6;
 972   def CMP_ULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 973       !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
 974       CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, Itin, setule>, HARDFLOAT,
 975       ISA_MICROMIPS32R6;
 976   def CMP_SAF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 977       !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
 978       CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, Itin>, HARDFLOAT,
 979       ISA_MICROMIPS32R6;
 980   def CMP_SUN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 981       !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
 982       CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, Itin>, HARDFLOAT,
 983       ISA_MICROMIPS32R6;
 984   def CMP_SEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 985       !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
 986       CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, Itin>, HARDFLOAT,
 987       ISA_MICROMIPS32R6;
 988   def CMP_SUEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 989       !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
 990       CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, Itin>, HARDFLOAT,
 991       ISA_MICROMIPS32R6;
 992   def CMP_SLT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 993       !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
 994       CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, Itin>, HARDFLOAT,
 995       ISA_MICROMIPS32R6;
 996   def CMP_SULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 997       !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
 998       CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, Itin>, HARDFLOAT,
 999       ISA_MICROMIPS32R6;
1000   def CMP_SLE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1001       !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
1002       CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, Itin>, HARDFLOAT,
1003       ISA_MICROMIPS32R6;
1004   def CMP_SULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1005       !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
1006       CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, Itin>, HARDFLOAT,
1007       ISA_MICROMIPS32R6;
1008 }
1009
1010 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
1011                              RegisterOperand SrcRC, InstrItinClass Itin,
1012                              SDPatternOperator OpNode = null_frag>
1013     : HARDFLOAT, NeverHasSideEffects {
1014   dag OutOperandList = (outs DstRC:$ft);
1015   dag InOperandList  = (ins SrcRC:$fs);
1016   string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
1017   list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
1018   InstrItinClass Itinerary = Itin;
1019   Format Form = FrmFR;
1020   list<Predicate> EncodingPredicates = [HasStdEnc];
1021 }
1022
1023 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
1024                                                     FGR32Opnd, II_FLOOR>;
1025 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
1026                                                     FGR64Opnd, II_FLOOR>;
1027 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
1028                                                     FGR32Opnd, II_FLOOR>;
1029 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
1030                                                     AFGR64Opnd, II_FLOOR>;
1031 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
1032                                                    FGR32Opnd, II_CEIL>;
1033 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
1034                                                    FGR64Opnd, II_CEIL>;
1035 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
1036                                                    FGR32Opnd, II_CEIL>;
1037 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
1038                                                    AFGR64Opnd, II_CEIL>;
1039 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
1040                                                     FGR32Opnd, II_TRUNC>;
1041 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
1042                                                     FGR64Opnd, II_TRUNC>;
1043 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
1044                                                     FGR32Opnd, II_TRUNC>;
1045 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
1046                                                     FGR64Opnd, II_TRUNC>;
1047 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
1048                                                  II_SQRT_S, fsqrt>;
1049 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd,
1050                                                 AFGR64Opnd, II_SQRT_D, fsqrt>;
1051 class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
1052                                                    FGR32Opnd, II_ROUND>;
1053 class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
1054                                                    FGR64Opnd, II_ROUND>;
1055 class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
1056                                                    FGR32Opnd, II_ROUND>;
1057 class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
1058                                                    FGR64Opnd, II_ROUND>;
1059
1060 class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>;
1061 class SEL_D_MMR6_DESC : COP1_SEL_D_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D>;
1062
1063 class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd,
1064                                               II_SELCCZ_S>;
1065 class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd,
1066                                               II_SELCCZ_D>;
1067 class SELNEZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd,
1068                                               II_SELCCZ_S>;
1069 class SELNEZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd,
1070                                               II_SELCCZ_D>;
1071 class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd,
1072                                               II_RINT_S>;
1073 class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd,
1074                                               II_RINT_S>;
1075 class CLASS_S_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd,
1076                                               II_CLASS_S>;
1077 class CLASS_D_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd,
1078                                               II_CLASS_S>;
1079
1080 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO,
1081                            InstrItinClass Itin>
1082     : Store<opstr, RO>, MMR6Arch<opstr> {
1083   let DecoderMethod = "DecodeMemMMImm16";
1084   InstrItinClass Itinerary = Itin;
1085 }
1086 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd, II_SB>;
1087
1088 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd, II_SH>;
1089 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
1090       MMR6Arch<"addu16"> {
1091   int AddedComplexity = 1;
1092 }
1093 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND>,
1094       MMR6Arch<"and16">;
1095 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
1096       MMR6Arch<"andi16">;
1097 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16"> {
1098   int AddedComplexity = 1;
1099 }
1100 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR>, MMR6Arch<"or16">;
1101 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
1102       MMR6Arch<"sll16">;
1103 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
1104       MMR6Arch<"srl16">;
1105 class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>,
1106                           MMR6Arch<"break16">;
1107 class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>,
1108       MMR6Arch<"li16">, IsAsCheapAsAMove;
1109 class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">;
1110 class MOVEP_MMR6_DESC : MovePMM16<"movep", GPRMM16OpndMovePPairFirst,
1111                                   GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP>,
1112                         MMR6Arch<"movep">;
1113 class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>,
1114                           MMR6Arch<"sdbbp16">;
1115 class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
1116       MMR6Arch<"subu16"> {
1117   int AddedComplexity = 1;
1118 }
1119 class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR>,
1120       MMR6Arch<"xor16">;
1121
1122 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
1123   dag OutOperandList = (outs GPR32Opnd:$rt);
1124   dag InOperandList = (ins mem:$addr);
1125   string AsmString = "lw\t$rt, $addr";
1126   let DecoderMethod = "DecodeMemMMImm16";
1127   let canFoldAsLoad = 1;
1128   let mayLoad = 1;
1129   list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
1130   InstrItinClass Itinerary = II_LW;
1131 }
1132
1133 class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
1134   dag OutOperandList = (outs GPR32Opnd:$rt);
1135   dag InOperandList = (ins uimm16:$imm16);
1136   string AsmString = "lui\t$rt, $imm16";
1137   list<dag> Pattern = [];
1138   bit hasSideEffects = 0;
1139   bit isReMaterializable = 1;
1140   InstrItinClass Itinerary = II_LUI;
1141   Format Form = FrmI;
1142 }
1143
1144 class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
1145   dag OutOperandList = (outs);
1146   dag InOperandList = (ins uimm5:$stype);
1147   string AsmString = !strconcat("sync", "\t$stype");
1148   list<dag> Pattern = [(MipsSync immZExt5:$stype)];
1149   InstrItinClass Itinerary = II_SYNC;
1150   bit HasSideEffects = 1;
1151 }
1152
1153 class SYNCI_MMR6_DESC : SYNCI_FT<"synci", mem_mm_16> {
1154   let DecoderMethod = "DecodeSynciR6";
1155 }
1156
1157 class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
1158   dag OutOperandList = (outs GPR32Opnd:$rt);
1159   dag InOperandList = (ins GPR32Opnd:$rd);
1160   string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
1161   InstrItinClass Itinerary = II_RDPGPR;
1162 }
1163
1164 class SDBBP_MMR6_DESC : MipsR6Inst {
1165   dag OutOperandList = (outs);
1166   dag InOperandList = (ins uimm20:$code_);
1167   string AsmString = !strconcat("sdbbp", "\t$code_");
1168   list<dag> Pattern = [];
1169   InstrItinClass Itinerary = II_SDBBP;
1170 }
1171
1172 class SIGRIE_MMR6_DESC : MipsR6Inst {
1173   dag OutOperandList = (outs);
1174   dag InOperandList = (ins uimm16:$code_);
1175   string AsmString = !strconcat("sigrie", "\t$code_");
1176   list<dag> Pattern = [];
1177   InstrItinClass Itinerary = II_SIGRIE;
1178 }
1179
1180 class LWM16_MMR6_DESC
1181     : MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
1182                       !strconcat("lwm16", "\t$rt, $addr"), [],
1183                       II_LWM, FrmI>,
1184       MMR6Arch<"lwm16"> {
1185   let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
1186   let mayLoad = 1;
1187   ComplexPattern Addr = addr;
1188 }
1189
1190 class SWM16_MMR6_DESC
1191     : MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
1192                       !strconcat("swm16", "\t$rt, $addr"), [],
1193                       II_SWM, FrmI>,
1194       MMR6Arch<"swm16"> {
1195   let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
1196   let mayStore = 1;
1197   ComplexPattern Addr = addr;
1198 }
1199
1200 class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd, DAGOperand RO,
1201                           SDPatternOperator OpNode, InstrItinClass Itin,
1202                           Operand MemOpnd>
1203     : MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
1204                       !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>,
1205       MMR6Arch<opstr> {
1206   let DecoderMethod = "DecodeMemMMImm4";
1207   let mayStore = 1;
1208 }
1209 class SB16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, GPRMM16Opnd,
1210                                            truncstorei8, II_SB, mem_mm_4>;
1211 class SH16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, GPRMM16Opnd,
1212                                            truncstorei16, II_SH, mem_mm_4_lsl1>;
1213 class SW16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, GPRMM16Opnd,
1214                                            store, II_SW, mem_mm_4_lsl2>;
1215
1216 class SWSP_MMR6_DESC
1217     : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
1218                       !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
1219       MMR6Arch<"swsp"> {
1220   let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
1221   let mayStore = 1;
1222 }
1223
1224 class JALRC_HB_MMR6_DESC {
1225   dag OutOperandList = (outs GPR32Opnd:$rt);
1226   dag InOperandList = (ins GPR32Opnd:$rs);
1227   string AsmString = !strconcat("jalrc.hb", "\t$rt, $rs");
1228   list<dag> Pattern = [];
1229   InstrItinClass Itinerary = II_JALR_HB;
1230   Format Form = FrmJ;
1231   bit isIndirectBranch = 1;
1232   bit hasDelaySlot = 0;
1233 }
1234
1235 class TLBINV_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
1236   dag OutOperandList = (outs);
1237   dag InOperandList = (ins);
1238   string AsmString = opstr;
1239   list<dag> Pattern = [];
1240   InstrItinClass Itinerary = Itin;
1241 }
1242
1243 class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv", II_TLBINV>;
1244 class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf", II_TLBINVF>;
1245
1246 class DVPEVP_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
1247   dag OutOperandList = (outs GPR32Opnd:$rs);
1248   dag InOperandList = (ins);
1249   string AsmString = !strconcat(opstr, "\t$rs");
1250   list<dag> Pattern = [];
1251   InstrItinClass Itinerary = Itin;
1252   bit hasUnModeledSideEffects = 1;
1253 }
1254
1255 class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp", II_DVP>;
1256 class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp", II_EVP>;
1257
1258 class BEQZC_MMR6_DESC
1259     : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>,
1260       MMR6Arch<"beqzc">;
1261 class BNEZC_MMR6_DESC
1262     : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21_mm, GPR32Opnd>,
1263       MMR6Arch<"bnezc">;
1264
1265 class BRANCH_COP1_MMR6_DESC_BASE<string opstr> :
1266     InstSE<(outs), (ins FGR64Opnd:$rt, brtarget_mm:$offset),
1267            !strconcat(opstr, "\t$rt, $offset"), [], II_BC1CCZ, FrmI>,
1268     HARDFLOAT, BRANCH_DESC_BASE {
1269   list<Register> Defs = [AT];
1270 }
1271
1272 class BC1EQZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1eqzc">;
1273 class BC1NEZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1nezc">;
1274
1275 class BRANCH_COP2_MMR6_DESC_BASE<string opstr, InstrItinClass Itin>
1276     : BRANCH_DESC_BASE {
1277   dag InOperandList = (ins COP2Opnd:$rt, brtarget_mm:$offset);
1278   dag OutOperandList = (outs);
1279   string AsmString = !strconcat(opstr, "\t$rt, $offset");
1280   list<Register> Defs = [AT];
1281   InstrItinClass Itinerary = Itin;
1282 }
1283
1284 class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc", II_BC2CCZ>;
1285 class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc", II_BC2CCZ>;
1286
1287 class EXT_MMR6_DESC {
1288   dag OutOperandList = (outs GPR32Opnd:$rt);
1289   dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_plus1:$size);
1290   string AsmString = !strconcat("ext", "\t$rt, $rs, $pos, $size");
1291   list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsExt GPR32Opnd:$rs, imm:$pos,
1292                        imm:$size))];
1293   InstrItinClass Itinerary = II_EXT;
1294   Format Form = FrmR;
1295   string BaseOpcode = "ext";
1296 }
1297
1298 class INS_MMR6_DESC {
1299   dag OutOperandList = (outs GPR32Opnd:$rt);
1300   dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_inssize_plus1:$size,
1301                        GPR32Opnd:$src);
1302   string AsmString = !strconcat("ins", "\t$rt, $rs, $pos, $size");
1303   list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsIns GPR32Opnd:$rs, imm:$pos,
1304                        imm:$size, GPR32Opnd:$src))];
1305   InstrItinClass Itinerary = II_INS;
1306   Format Form = FrmR;
1307   string BaseOpcode = "ins";
1308   string Constraints = "$src = $rt";
1309 }
1310
1311 class JALRC_MMR6_DESC {
1312   dag OutOperandList = (outs GPR32Opnd:$rt);
1313   dag InOperandList = (ins GPR32Opnd:$rs);
1314   string AsmString = !strconcat("jalrc", "\t$rt, $rs");
1315   list<dag> Pattern = [];
1316   InstrItinClass Itinerary = II_JALRC;
1317   bit isCall = 1;
1318   bit hasDelaySlot = 0;
1319   list<Register> Defs = [RA];
1320 }
1321
1322 class BOVC_BNVC_MMR6_DESC_BASE<string instr_asm, Operand opnd,
1323                                RegisterOperand GPROpnd>
1324     : BRANCH_DESC_BASE {
1325   dag InOperandList = (ins GPROpnd:$rt, GPROpnd:$rs, opnd:$offset);
1326   dag OutOperandList = (outs);
1327   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $offset");
1328   list<Register> Defs = [AT];
1329   InstrItinClass Itinerary = II_BCCC;
1330 }
1331
1332 class BOVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bovc", brtargetr6, GPR32Opnd>;
1333 class BNVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bnvc", brtargetr6, GPR32Opnd>;
1334
1335 //===----------------------------------------------------------------------===//
1336 //
1337 // Instruction Definitions
1338 //
1339 //===----------------------------------------------------------------------===//
1340
1341 let DecoderNamespace = "MicroMipsR6" in {
1342 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
1343 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
1344 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
1345 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
1346                    ISA_MICROMIPS32R6;
1347 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
1348                   ISA_MICROMIPS32R6;
1349 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
1350 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
1351 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
1352 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
1353 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
1354 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
1355 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
1356 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
1357 def BEQZC_MMR6 : R6MMR6Rel, BEQZC_MMR6_ENC, BEQZC_MMR6_DESC,
1358                  ISA_MICROMIPS32R6;
1359 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
1360                    ISA_MICROMIPS32R6;
1361 def BNEZC_MMR6 : R6MMR6Rel, BNEZC_MMR6_ENC, BNEZC_MMR6_DESC,
1362                  ISA_MICROMIPS32R6;
1363 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
1364                    ISA_MICROMIPS32R6;
1365 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
1366                    ISA_MICROMIPS32R6;
1367 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
1368                    ISA_MICROMIPS32R6;
1369 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
1370                    ISA_MICROMIPS32R6;
1371 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
1372 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
1373 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
1374 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
1375 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
1376 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
1377 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
1378 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
1379 def DI_MMR6 : StdMMR6Rel, DI_MMR6_DESC, DI_MMR6_ENC, ISA_MICROMIPS32R6;
1380 def ERET_MMR6 : StdMMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
1381 def DERET_MMR6 : StdMMR6Rel, DERET_MMR6_DESC, DERET_MMR6_ENC, ISA_MICROMIPS32R6;
1382 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
1383                   ISA_MICROMIPS32R6;
1384 def GINVI_MMR6 : R6MMR6Rel, GINVI_MMR6_ENC, GINVI_MMR6_DESC,
1385                  ISA_MICROMIPS32R6, ASE_GINV;
1386 def GINVT_MMR6 : R6MMR6Rel, GINVT_MMR6_ENC, GINVT_MMR6_DESC,
1387                  ISA_MICROMIPS32R6, ASE_GINV;
1388 let FastISelShouldIgnore = 1 in
1389 def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
1390                    ISA_MICROMIPS32R6;
1391 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
1392 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
1393 def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
1394 def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
1395                       ISA_MICROMIPS32R6;
1396 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
1397 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
1398 def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1399 def MTC0_MMR6 : StdMMR6Rel, MTC0_MMR6_ENC, MTC0_MMR6_DESC, ISA_MICROMIPS32R6;
1400 def MTC1_MMR6 : StdMMR6Rel, MTC1_MMR6_DESC, MTC1_MMR6_ENC, ISA_MICROMIPS32R6;
1401 def MTC2_MMR6 : StdMMR6Rel, MTC2_MMR6_ENC, MTC2_MMR6_DESC, ISA_MICROMIPS32R6;
1402 def MTHC0_MMR6 : R6MMR6Rel, MTHC0_MMR6_ENC, MTHC0_MMR6_DESC, ISA_MICROMIPS32R6;
1403 def MTHC2_MMR6 : StdMMR6Rel, MTHC2_MMR6_ENC, MTHC2_MMR6_DESC, ISA_MICROMIPS32R6;
1404 def MFC0_MMR6 : StdMMR6Rel, MFC0_MMR6_ENC, MFC0_MMR6_DESC, ISA_MICROMIPS32R6;
1405 def MFC1_MMR6 : StdMMR6Rel, MFC1_MMR6_DESC, MFC1_MMR6_ENC, ISA_MICROMIPS32R6;
1406 def MFC2_MMR6 : StdMMR6Rel, MFC2_MMR6_ENC, MFC2_MMR6_DESC, ISA_MICROMIPS32R6;
1407 def MFHC0_MMR6 : R6MMR6Rel, MFHC0_MMR6_ENC, MFHC0_MMR6_DESC, ISA_MICROMIPS32R6;
1408 def MFHC2_MMR6 : StdMMR6Rel, MFHC2_MMR6_ENC, MFHC2_MMR6_DESC, ISA_MICROMIPS32R6;
1409 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
1410 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
1411 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
1412 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
1413 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
1414 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
1415 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
1416 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
1417 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
1418 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
1419 def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6;
1420 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
1421                   ISA_MICROMIPS32R6;
1422 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
1423                   ISA_MICROMIPS32R6;
1424 def SH16_MMR6 : StdMMR6Rel, SH16_MMR6_DESC, SH16_MMR6_ENC, ISA_MICROMIPS32R6;
1425 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
1426 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
1427 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
1428 def SW16_MMR6 : StdMMR6Rel, SW16_MMR6_DESC, SW16_MMR6_ENC, ISA_MICROMIPS32R6;
1429 def SWM16_MMR6 : StdMMR6Rel, SWM16_MMR6_DESC, SWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1430 def SWSP_MMR6 : StdMMR6Rel, SWSP_MMR6_DESC, SWSP_MMR6_ENC, ISA_MICROMIPS32R6;
1431 def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC,
1432                   ISA_MICROMIPS32R6;
1433 def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6;
1434 def LB_MMR6 : R6MMR6Rel, LB_MMR6_ENC, LB_MMR6_DESC, ISA_MICROMIPS32R6;
1435 def LBU_MMR6 : R6MMR6Rel, LBU_MMR6_ENC, LBU_MMR6_DESC, ISA_MICROMIPS32R6;
1436 def PAUSE_MMR6 : StdMMR6Rel, PAUSE_MMR6_DESC, PAUSE_MMR6_ENC, ISA_MICROMIPS32R6;
1437 def RDHWR_MMR6 : R6MMR6Rel, RDHWR_MMR6_DESC, RDHWR_MMR6_ENC, ISA_MICROMIPS32R6;
1438 def WAIT_MMR6 : StdMMR6Rel, WAIT_MMR6_DESC, WAIT_MMR6_ENC, ISA_MICROMIPS32R6;
1439 def SSNOP_MMR6 : StdMMR6Rel, SSNOP_MMR6_DESC, SSNOP_MMR6_ENC, ISA_MICROMIPS32R6;
1440 def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6;
1441 def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
1442 def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
1443                   ISA_MICROMIPS32R6;
1444 def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
1445 def SIGRIE_MMR6 : R6MMR6Rel, SIGRIE_MMR6_DESC, SIGRIE_MMR6_ENC,
1446                   ISA_MICROMIPS32R6;
1447 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
1448 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
1449 let DecoderMethod = "DecodeMemMMImm16" in {
1450   def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
1451 }
1452 /// Floating Point Instructions
1453 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
1454                   ISA_MICROMIPS32R6;
1455 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
1456                   ISA_MICROMIPS32R6;
1457 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
1458                   ISA_MICROMIPS32R6;
1459 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
1460                   ISA_MICROMIPS32R6;
1461 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
1462                    ISA_MICROMIPS32R6;
1463 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
1464                    ISA_MICROMIPS32R6;
1465 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
1466                    ISA_MICROMIPS32R6;
1467 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
1468                    ISA_MICROMIPS32R6;
1469 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
1470                   ISA_MICROMIPS32R6;
1471 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
1472                   ISA_MICROMIPS32R6;
1473 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
1474                   ISA_MICROMIPS32R6;
1475 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
1476 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
1477 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
1478 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
1479 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
1480                   ISA_MICROMIPS32R6;
1481 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
1482                   ISA_MICROMIPS32R6;
1483 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
1484                   ISA_MICROMIPS32R6;
1485 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
1486                   ISA_MICROMIPS32R6;
1487 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
1488                    ISA_MICROMIPS32R6;
1489 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
1490                    ISA_MICROMIPS32R6;
1491 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
1492                    ISA_MICROMIPS32R6;
1493 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
1494                    ISA_MICROMIPS32R6;
1495 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
1496                    ISA_MICROMIPS32R6;
1497 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
1498                    ISA_MICROMIPS32R6;
1499 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, II_CMP_CC_S>;
1500 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, II_CMP_CC_D>;
1501 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
1502                      ISA_MICROMIPS32R6;
1503 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
1504                      ISA_MICROMIPS32R6;
1505 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
1506                      ISA_MICROMIPS32R6;
1507 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
1508                      ISA_MICROMIPS32R6;
1509 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
1510                     ISA_MICROMIPS32R6;
1511 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
1512                     ISA_MICROMIPS32R6;
1513 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
1514                     ISA_MICROMIPS32R6;
1515 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
1516                     ISA_MICROMIPS32R6;
1517 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
1518                      ISA_MICROMIPS32R6;
1519 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
1520                      ISA_MICROMIPS32R6;
1521 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
1522                      ISA_MICROMIPS32R6;
1523 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
1524                      ISA_MICROMIPS32R6;
1525 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
1526 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
1527 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
1528 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
1529 def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
1530                   ISA_MICROMIPS32R6;
1531 def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
1532                   ISA_MICROMIPS32R6;
1533 def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
1534                   ISA_MICROMIPS32R6;
1535 def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
1536                   ISA_MICROMIPS32R6;
1537 def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
1538                   ISA_MICROMIPS32R6;
1539 def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
1540                   ISA_MICROMIPS32R6;
1541 def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
1542                   ISA_MICROMIPS32R6;
1543 def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
1544                    ISA_MICROMIPS32R6;
1545 def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
1546                 ISA_MICROMIPS32R6;
1547 def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
1548                   ISA_MICROMIPS32R6;
1549 def MOVEP_MMR6  : StdMMR6Rel, MOVEP_MMR6_DESC, MOVEP_MMR6_ENC,
1550                   ISA_MICROMIPS32R6;
1551 def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
1552                    ISA_MICROMIPS32R6;
1553 def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
1554                   ISA_MICROMIPS32R6;
1555 def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
1556                  ISA_MICROMIPS32R6;
1557 def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC,
1558                     ISA_MICROMIPS32R6;
1559 def EXT_MMR6 : StdMMR6Rel, EXT_MMR6_ENC, EXT_MMR6_DESC, ISA_MICROMIPS32R6;
1560 def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6;
1561 def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6;
1562 def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
1563                   ISA_MICROMIPS32R6;
1564 def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC,
1565                   ISA_MICROMIPS32R6;
1566 def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
1567                      ISA_MICROMIPS32R6;
1568 def ROUND_L_D_MMR6 : StdMMR6Rel, ROUND_L_D_MMR6_ENC, ROUND_L_D_MMR6_DESC,
1569                      ISA_MICROMIPS32R6;
1570 def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W_S_MMR6_ENC, ROUND_W_S_MMR6_DESC,
1571                      ISA_MICROMIPS32R6;
1572 def ROUND_W_D_MMR6 : StdMMR6Rel, ROUND_W_D_MMR6_ENC, ROUND_W_D_MMR6_DESC,
1573                      ISA_MICROMIPS32R6;
1574 def SEL_S_MMR6 : R6MMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6;
1575 def SEL_D_MMR6 : R6MMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6;
1576 def SELEQZ_S_MMR6 : R6MMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC,
1577                     ISA_MICROMIPS32R6;
1578 def SELEQZ_D_MMR6 : R6MMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC,
1579                     ISA_MICROMIPS32R6;
1580 def SELNEZ_S_MMR6 : R6MMR6Rel, SELNEZ_S_MMR6_ENC, SELNEZ_S_MMR6_DESC,
1581                     ISA_MICROMIPS32R6;
1582 def SELNEZ_D_MMR6 : R6MMR6Rel, SELNEZ_D_MMR6_ENC, SELNEZ_D_MMR6_DESC,
1583                     ISA_MICROMIPS32R6;
1584 def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC,
1585                    ISA_MICROMIPS32R6;
1586 def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC,
1587                    ISA_MICROMIPS32R6;
1588 def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC,
1589                   ISA_MICROMIPS32R6;
1590 def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC,
1591                    ISA_MICROMIPS32R6;
1592 def DVP_MMR6 : R6MMR6Rel, DVP_MMR6_ENC, DVP_MMR6_DESC, ISA_MICROMIPS32R6;
1593 def EVP_MMR6 : R6MMR6Rel, EVP_MMR6_ENC, EVP_MMR6_DESC, ISA_MICROMIPS32R6;
1594 def BC1EQZC_MMR6 : R6MMR6Rel, BC1EQZC_MMR6_DESC, BC1EQZC_MMR6_ENC,
1595                    ISA_MICROMIPS32R6;
1596 def BC1NEZC_MMR6 : R6MMR6Rel, BC1NEZC_MMR6_DESC, BC1NEZC_MMR6_ENC,
1597                    ISA_MICROMIPS32R6;
1598 def BC2EQZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2EQZC_MMR6_ENC, BC2EQZC_MMR6_DESC,
1599                    ISA_MICROMIPS32R6;
1600 def BC2NEZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2NEZC_MMR6_ENC, BC2NEZC_MMR6_DESC,
1601                    ISA_MICROMIPS32R6;
1602 let DecoderNamespace = "MicroMipsFP64" in {
1603   def LDC1_D64_MMR6 : StdMMR6Rel, LDC1_D64_MMR6_DESC, LDC1_MMR6_ENC,
1604                       ISA_MICROMIPS32R6 {
1605     let BaseOpcode = "LDC164";
1606   }
1607   def SDC1_D64_MMR6 : StdMMR6Rel, SDC1_D64_MMR6_DESC, SDC1_MMR6_ENC,
1608                       ISA_MICROMIPS32R6;
1609 }
1610 def LDC2_MMR6 : StdMMR6Rel, LDC2_MMR6_ENC, LDC2_MMR6_DESC, ISA_MICROMIPS32R6;
1611 def SDC2_MMR6 : StdMMR6Rel, SDC2_MMR6_ENC, SDC2_MMR6_DESC, ISA_MICROMIPS32R6;
1612 def LWC2_MMR6 : StdMMR6Rel, LWC2_MMR6_ENC, LWC2_MMR6_DESC, ISA_MICROMIPS32R6;
1613 def SWC2_MMR6 : StdMMR6Rel, SWC2_MMR6_ENC, SWC2_MMR6_DESC, ISA_MICROMIPS32R6;
1614 def LL_MMR6   : R6MMR6Rel, LL_MMR6_ENC, LL_MMR6_DESC, ISA_MICROMIPS32R6;
1615 def SC_MMR6   : R6MMR6Rel, SC_MMR6_ENC, SC_MMR6_DESC, ISA_MICROMIPS32R6;
1616 }
1617
1618 def BOVC_MMR6 : R6MMR6Rel, BOVC_MMR6_ENC, BOVC_MMR6_DESC, ISA_MICROMIPS32R6,
1619                 MMDecodeDisambiguatedBy<"POP35GroupBranchMMR6">;
1620 def BNVC_MMR6 : R6MMR6Rel, BNVC_MMR6_ENC, BNVC_MMR6_DESC, ISA_MICROMIPS32R6,
1621                 MMDecodeDisambiguatedBy<"POP37GroupBranchMMR6">;
1622 def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6;
1623 def BGEUC_MMR6 : R6MMR6Rel, BGEUC_MMR6_ENC, BGEUC_MMR6_DESC, ISA_MICROMIPS32R6;
1624 def BLTC_MMR6 : R6MMR6Rel, BLTC_MMR6_ENC, BLTC_MMR6_DESC, ISA_MICROMIPS32R6;
1625 def BLTUC_MMR6 : R6MMR6Rel, BLTUC_MMR6_ENC, BLTUC_MMR6_DESC, ISA_MICROMIPS32R6;
1626 def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6,
1627                 DecodeDisambiguates<"POP35GroupBranchMMR6">;
1628 def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6,
1629                 DecodeDisambiguates<"POP37GroupBranchMMR6">;
1630 def BLTZC_MMR6 : R6MMR6Rel, BLTZC_MMR6_ENC, BLTZC_MMR6_DESC, ISA_MICROMIPS32R6;
1631 def BLEZC_MMR6 : R6MMR6Rel, BLEZC_MMR6_ENC, BLEZC_MMR6_DESC, ISA_MICROMIPS32R6;
1632 def BGEZC_MMR6 : R6MMR6Rel, BGEZC_MMR6_ENC, BGEZC_MMR6_DESC, ISA_MICROMIPS32R6;
1633 def BGTZC_MMR6 : R6MMR6Rel, BGTZC_MMR6_ENC, BGTZC_MMR6_DESC, ISA_MICROMIPS32R6;
1634 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
1635                    ISA_MICROMIPS32R6;
1636 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
1637                    ISA_MICROMIPS32R6;
1638 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
1639                    ISA_MICROMIPS32R6;
1640 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
1641                    ISA_MICROMIPS32R6;
1642
1643 //===----------------------------------------------------------------------===//
1644 //
1645 // MicroMips instruction aliases
1646 //
1647 //===----------------------------------------------------------------------===//
1648
1649 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1650 def : MipsInstAlias<"di", (DI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1651 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
1652 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1653                                       !strconcat("b", "\t$offset")> {
1654   string DecoderNamespace = "MicroMipsR6";
1655 }
1656 def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6;
1657 def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
1658 def : MipsInstAlias<"sigrie", (SIGRIE_MMR6 0), 1>, ISA_MICROMIPS32R6;
1659 def : MipsInstAlias<"rdhwr $rt, $rs",
1660                     (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
1661                     ISA_MICROMIPS32R6;
1662 def : MipsInstAlias<"mtc0 $rt, $rs",
1663                     (MTC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1664                     ISA_MICROMIPS32R6;
1665 def : MipsInstAlias<"mthc0 $rt, $rs",
1666                     (MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1667                     ISA_MICROMIPS32R6;
1668 def : MipsInstAlias<"mfc0 $rt, $rs",
1669                     (MFC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1670                     ISA_MICROMIPS32R6;
1671 def : MipsInstAlias<"mfhc0 $rt, $rs",
1672                     (MFHC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1673                     ISA_MICROMIPS32R6;
1674 def : MipsInstAlias<"jalrc.hb $rs", (JALRC_HB_MMR6 RA, GPR32Opnd:$rs), 1>,
1675                     ISA_MICROMIPS32R6;
1676 def : MipsInstAlias<"jal $offset", (BALC_MMR6 brtarget26_mm:$offset), 0>,
1677                     ISA_MICROMIPS32R6;
1678 def : MipsInstAlias<"dvp", (DVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
1679 def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
1680 def : MipsInstAlias<"jalrc $rs", (JALRC_MMR6 RA, GPR32Opnd:$rs), 1>,
1681       ISA_MICROMIPS32R6;
1682 def : MipsInstAlias<"and $rs, $rt, $imm",
1683                     (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1684                     ISA_MICROMIPS32R6;
1685 def : MipsInstAlias<"and $rs, $imm",
1686                     (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1687                     ISA_MICROMIPS32R6;
1688 def : MipsInstAlias<"or $rs, $rt, $imm",
1689                     (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1690                     ISA_MICROMIPS32R6;
1691 def : MipsInstAlias<"or $rs, $imm",
1692                     (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1693                     ISA_MICROMIPS32R6;
1694 def : MipsInstAlias<"xor $rs, $rt, $imm",
1695                     (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1696                     ISA_MICROMIPS32R6;
1697 def : MipsInstAlias<"xor $rs, $imm",
1698                     (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1699                     ISA_MICROMIPS32R6;
1700 def : MipsInstAlias<"not $rt, $rs",
1701                     (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
1702                     ISA_MICROMIPS32R6;
1703 def : MipsInstAlias<"not $rt",
1704                     (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>,
1705                     ISA_MICROMIPS32R6;
1706 def : MipsInstAlias<"lapc $rd, $imm",
1707                     (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
1708                     ISA_MICROMIPS32R6;
1709 def : MipsInstAlias<"neg $rt, $rs",
1710                     (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1711       ISA_MICROMIPS32R6;
1712 def : MipsInstAlias<"neg $rt",
1713                     (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1714       ISA_MICROMIPS32R6;
1715 def : MipsInstAlias<"negu $rt, $rs",
1716                     (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1717       ISA_MICROMIPS32R6;
1718 def : MipsInstAlias<"negu $rt",
1719                     (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1720       ISA_MICROMIPS32R6;
1721 def : MipsInstAlias<"beqz16 $rs, $offset", (BEQZC16_MMR6 GPRMM16Opnd:$rs,
1722                                                          brtarget7_mm:$offset),
1723                     0>, ISA_MICROMIPS32R6;
1724 def : MipsInstAlias<"bnez16 $rs, $offset", (BNEZC16_MMR6 GPRMM16Opnd:$rs,
1725                                                          brtarget7_mm:$offset),
1726                     0>, ISA_MICROMIPS32R6;
1727 def : MipsInstAlias<"b16 $offset", (BC16_MMR6 brtarget10_mm:$offset), 0>,
1728                     ISA_MICROMIPS32R6;
1729
1730 //===----------------------------------------------------------------------===//
1731 //
1732 // MicroMips arbitrary patterns that map to one or more instructions
1733 //
1734 //===----------------------------------------------------------------------===//
1735
1736 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1737               (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;
1738 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1739               (SUBU_MMR6 GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS32R6;
1740
1741 def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
1742               (OR_MM (SELNEZ_MMR6 i32:$t, i32:$cond),
1743                      (SELEQZ_MMR6 i32:$f, i32:$cond))>,
1744               ISA_MICROMIPS32R6;
1745 def : MipsPat<(select i32:$cond, i32:$t, immz),
1746               (SELNEZ_MMR6 i32:$t, i32:$cond)>,
1747               ISA_MICROMIPS32R6;
1748 def : MipsPat<(select i32:$cond, immz, i32:$f),
1749               (SELEQZ_MMR6 i32:$f, i32:$cond)>,
1750               ISA_MICROMIPS32R6;
1751
1752 defm : SelectInt_Pats<i32, OR_MM, XORI_MMR6, SLTi_MM, SLTiu_MM, SELEQZ_MMR6,
1753                       SELNEZ_MMR6, immZExt16, i32>, ISA_MICROMIPS32R6;
1754
1755 defm S_MMR6 : Cmp_Pats<f32, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
1756 defm D_MMR6 : Cmp_Pats<f64, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
1757
1758 def : MipsPat<(f32 fpimm0), (MTC1_MMR6 ZERO)>, ISA_MICROMIPS32R6;
1759 def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6(MTC1_MMR6 ZERO))>,
1760       ISA_MICROMIPS32R6;
1761 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
1762               (TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6;
1763 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
1764               (TRUNC_W_S_MMR6 FGR32Opnd:$src)>, ISA_MICROMIPS32R6;
1765
1766 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
1767               (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>,
1768               ISA_MICROMIPS32R6;
1769 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
1770               (ANDI_MMR6 GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS32R6;
1771 def : MipsPat<(i32 immZExt16:$imm),
1772               (XORI_MMR6 ZERO, immZExt16:$imm)>, ISA_MICROMIPS32R6;
1773 def : MipsPat<(not GPRMM16:$in),
1774               (NOT16_MMR6 GPRMM16:$in)>, ISA_MICROMIPS32R6;
1775 def : MipsPat<(not GPR32:$in),
1776               (NOR_MMR6 GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS32R6;
1777 // Patterns for load with a reg+imm operand.
1778 let AddedComplexity = 41 in {
1779   def : LoadRegImmPat<LDC1_D64_MMR6, f64, load>, FGR_64, ISA_MICROMIPS32R6;
1780   def : StoreRegImmPat<SDC1_D64_MMR6, f64>, FGR_64, ISA_MICROMIPS32R6;
1781 }
1782
1783 let isCall=1, hasDelaySlot=0, isCTI=1, Defs = [RA] in {
1784   class JumpLinkMMR6<Instruction JumpInst, DAGOperand Opnd> :
1785     PseudoSE<(outs), (ins calltarget:$target), [], II_JAL>,
1786     PseudoInstExpansion<(JumpInst Opnd:$target)>;
1787 }
1788
1789 def JAL_MMR6 : JumpLinkMMR6<BALC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
1790
1791 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1792               (JAL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
1793 def : MipsPat<(MipsJmpLink (iPTR tglobaladdr:$dst)),
1794               (JAL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
1795
1796 def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
1797
1798 def TAILCALLREG_MMR6  : TailCallReg<JRC16_MM, GPR32Opnd>, ISA_MICROMIPS32R6;
1799
1800 def PseudoIndirectBranch_MMR6 : PseudoIndirectBranchBase<JRC16_MMR6,
1801                                                          GPR32Opnd>,
1802                                 ISA_MICROMIPS32R6;
1803
1804 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1805               (TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
1806
1807 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1808               (TAILCALL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
1809
1810
1811 def : MipsPat<(brcond (i32 (setne GPR32:$lhs, 0)), bb:$dst),
1812               (BNEZC_MMR6 GPR32:$lhs, bb:$dst)>, ISA_MICROMIPS32R6;
1813 def : MipsPat<(brcond (i32 (seteq GPR32:$lhs, 0)), bb:$dst),
1814               (BEQZC_MMR6 GPR32:$lhs, bb:$dst)>, ISA_MICROMIPS32R6;
1815
1816 def : MipsPat<(brcond (i32 (setge GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1817               (BEQZC_MMR6 (SLT_MM GPR32:$lhs, GPR32:$rhs), bb:$dst)>,
1818       ISA_MICROMIPS32R6;
1819 def : MipsPat<(brcond (i32 (setuge GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1820               (BEQZC_MMR6 (SLTu_MM GPR32:$lhs, GPR32:$rhs), bb:$dst)>,
1821       ISA_MICROMIPS32R6;
1822 def : MipsPat<(brcond (i32 (setge GPR32:$lhs, immSExt16:$rhs)), bb:$dst),
1823               (BEQZC_MMR6 (SLTi_MM GPR32:$lhs, immSExt16:$rhs), bb:$dst)>,
1824       ISA_MICROMIPS32R6;
1825 def : MipsPat<(brcond (i32 (setuge GPR32:$lhs, immSExt16:$rhs)), bb:$dst),
1826               (BEQZC_MMR6 (SLTiu_MM GPR32:$lhs, immSExt16:$rhs), bb:$dst)>,
1827       ISA_MICROMIPS32R6;
1828 def : MipsPat<(brcond (i32 (setgt GPR32:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1829               (BEQZC_MMR6 (SLTi_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>,
1830       ISA_MICROMIPS32R6;
1831 def : MipsPat<(brcond (i32 (setugt GPR32:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1832               (BEQZC_MMR6 (SLTiu_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>,
1833       ISA_MICROMIPS32R6;
1834
1835 def : MipsPat<(brcond (i32 (setle GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1836               (BEQZC_MMR6  (SLT_MM GPR32:$rhs, GPR32:$lhs), bb:$dst)>,
1837       ISA_MICROMIPS32R6;
1838 def : MipsPat<(brcond (i32 (setule GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1839               (BEQZC_MMR6  (SLTu_MM GPR32:$rhs, GPR32:$lhs), bb:$dst)>,
1840       ISA_MICROMIPS32R6;
1841
1842 def : MipsPat<(brcond GPR32:$cond, bb:$dst),
1843               (BNEZC_MMR6 GPR32:$cond, bb:$dst)>, ISA_MICROMIPS32R6;