contrib/llvm-project/llvm/lib/Target/Mips/Mips.td

   1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 // This is the top level entry point for the Mips target.
   9 //===----------------------------------------------------------------------===//
  10
  11 //===----------------------------------------------------------------------===//
  12 // Target-independent interfaces
  13 //===----------------------------------------------------------------------===//
  14
  15 include "llvm/Target/Target.td"
  16
  17 // The overall idea of the PredicateControl class is to chop the Predicates list
  18 // into subsets that are usually overridden independently. This allows
  19 // subclasses to partially override the predicates of their superclasses without
  20 // having to re-add all the existing predicates.
  21 class PredicateControl {
  22   // Predicates for the encoding scheme in use such as HasStdEnc
  23   list<Predicate> EncodingPredicates = [];
  24   // Predicates for the GPR size such as IsGP64bit
  25   list<Predicate> GPRPredicates = [];
  26   // Predicates for the PTR size such as IsPTR64bit
  27   list<Predicate> PTRPredicates = [];
  28   // Predicates for a symbol's size such as hasSym32.
  29   list<Predicate> SYMPredicates = [];
  30   // Predicates for the FGR size and layout such as IsFP64bit
  31   list<Predicate> FGRPredicates = [];
  32   // Predicates for the instruction group membership such as ISA's.
  33   list<Predicate> InsnPredicates = [];
  34   // Predicate for the ASE that an instruction belongs to.
  35   list<Predicate> ASEPredicate = [];
  36   // Predicate for marking the instruction as usable in hard-float mode only.
  37   list<Predicate> HardFloatPredicate = [];
  38   // Predicates for anything else
  39   list<Predicate> AdditionalPredicates = [];
  40   list<Predicate> Predicates = !listconcat(EncodingPredicates,
  41                                            GPRPredicates,
  42                                            PTRPredicates,
  43                                            SYMPredicates,
  44                                            FGRPredicates,
  45                                            InsnPredicates,
  46                                            HardFloatPredicate,
  47                                            ASEPredicate,
  48                                            AdditionalPredicates);
  49 }
  50
  51 // Like Requires<> but for the AdditionalPredicates list
  52 class AdditionalRequires<list<Predicate> preds> {
  53   list<Predicate> AdditionalPredicates = preds;
  54 }
  55
  56 //===----------------------------------------------------------------------===//
  57 // Register File, Calling Conv, Instruction Descriptions
  58 //===----------------------------------------------------------------------===//
  59
  60 include "MipsRegisterInfo.td"
  61 include "MipsSchedule.td"
  62 include "MipsInstrInfo.td"
  63 include "MipsCallingConv.td"
  64 include "MipsRegisterBanks.td"
  65
  66 // Avoid forward declaration issues.
  67 include "MipsScheduleP5600.td"
  68 include "MipsScheduleGeneric.td"
  69
  70 def MipsInstrInfo : InstrInfo;
  71
  72 //===----------------------------------------------------------------------===//
  73 // Mips Subtarget features                                                    //
  74 //===----------------------------------------------------------------------===//
  75
  76 def FeatureNoABICalls  : SubtargetFeature<"noabicalls", "NoABICalls", "true",
  77                                 "Disable SVR4-style position-independent code">;
  78 def FeaturePTR64Bit    : SubtargetFeature<"ptr64", "IsPTR64bit", "true",
  79                                 "Pointers are 64-bit wide">;
  80 def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
  81                                 "General Purpose Registers are 64-bit wide">;
  82 def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
  83                                 "Support 64-bit FP registers">;
  84 def FeatureFPXX        : SubtargetFeature<"fpxx", "IsFPXX", "true",
  85                                 "Support for FPXX">;
  86 def FeatureNaN2008     : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
  87                                 "IEEE 754-2008 NaN encoding">;
  88 def FeatureAbs2008     : SubtargetFeature<"abs2008", "Abs2008", "true",
  89                                           "Disable IEEE 754-2008 abs.fmt mode">;
  90 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
  91                                 "true", "Only supports single precision float">;
  92 def FeatureSoftFloat   : SubtargetFeature<"soft-float", "IsSoftFloat", "true",
  93                                 "Does not support floating point instructions">;
  94 def FeatureNoOddSPReg  : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
  95                               "Disable odd numbered single-precision "
  96                               "registers">;
  97 def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU",
  98                                 "true", "Enable vector FPU instructions">;
  99 def FeatureMips1       : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
 100                                 "Mips I ISA Support [highly experimental]">;
 101 def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
 102                                 "Mips II ISA Support [highly experimental]",
 103                                 [FeatureMips1]>;
 104 def FeatureMips3_32    : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
 105                                 "Subset of MIPS-III that is also in MIPS32 "
 106                                 "[highly experimental]">;
 107 def FeatureMips3_32r2  : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
 108                                 "Subset of MIPS-III that is also in MIPS32r2 "
 109                                 "[highly experimental]">;
 110 def FeatureMips3       : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
 111                                 "MIPS III ISA Support [highly experimental]",
 112                                 [FeatureMips2, FeatureMips3_32,
 113                                  FeatureMips3_32r2, FeatureGP64Bit,
 114                                  FeatureFP64Bit]>;
 115 def FeatureMips4_32    : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
 116                                 "Subset of MIPS-IV that is also in MIPS32 "
 117                                 "[highly experimental]">;
 118 def FeatureMips4_32r2  : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
 119                                 "Subset of MIPS-IV that is also in MIPS32r2 "
 120                                 "[highly experimental]">;
 121 def FeatureMips4       : SubtargetFeature<"mips4", "MipsArchVersion",
 122                                 "Mips4", "MIPS IV ISA Support",
 123                                 [FeatureMips3, FeatureMips4_32,
 124                                  FeatureMips4_32r2]>;
 125 def FeatureMips5_32r2  : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
 126                                 "Subset of MIPS-V that is also in MIPS32r2 "
 127                                 "[highly experimental]">;
 128 def FeatureMips5       : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
 129                                 "MIPS V ISA Support [highly experimental]",
 130                                 [FeatureMips4, FeatureMips5_32r2]>;
 131 def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
 132                                 "Mips32 ISA Support",
 133                                 [FeatureMips2, FeatureMips3_32,
 134                                  FeatureMips4_32]>;
 135 def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
 136                                 "Mips32r2", "Mips32r2 ISA Support",
 137                                 [FeatureMips3_32r2, FeatureMips4_32r2,
 138                                  FeatureMips5_32r2, FeatureMips32]>;
 139 def FeatureMips32r3    : SubtargetFeature<"mips32r3", "MipsArchVersion",
 140                                 "Mips32r3", "Mips32r3 ISA Support",
 141                                 [FeatureMips32r2]>;
 142 def FeatureMips32r5    : SubtargetFeature<"mips32r5", "MipsArchVersion",
 143                                 "Mips32r5", "Mips32r5 ISA Support",
 144                                 [FeatureMips32r3]>;
 145 def FeatureMips32r6    : SubtargetFeature<"mips32r6", "MipsArchVersion",
 146                                 "Mips32r6",
 147                                 "Mips32r6 ISA Support [experimental]",
 148                                 [FeatureMips32r5, FeatureFP64Bit,
 149                                  FeatureNaN2008, FeatureAbs2008]>;
 150 def FeatureMips64      : SubtargetFeature<"mips64", "MipsArchVersion",
 151                                 "Mips64", "Mips64 ISA Support",
 152                                 [FeatureMips5, FeatureMips32]>;
 153 def FeatureMips64r2    : SubtargetFeature<"mips64r2", "MipsArchVersion",
 154                                 "Mips64r2", "Mips64r2 ISA Support",
 155                                 [FeatureMips64, FeatureMips32r2]>;
 156 def FeatureMips64r3    : SubtargetFeature<"mips64r3", "MipsArchVersion",
 157                                 "Mips64r3", "Mips64r3 ISA Support",
 158                                 [FeatureMips64r2, FeatureMips32r3]>;
 159 def FeatureMips64r5    : SubtargetFeature<"mips64r5", "MipsArchVersion",
 160                                 "Mips64r5", "Mips64r5 ISA Support",
 161                                 [FeatureMips64r3, FeatureMips32r5]>;
 162 def FeatureMips64r6    : SubtargetFeature<"mips64r6", "MipsArchVersion",
 163                                 "Mips64r6",
 164                                 "Mips64r6 ISA Support [experimental]",
 165                                 [FeatureMips32r6, FeatureMips64r5,
 166                                  FeatureNaN2008, FeatureAbs2008]>;
 167 def FeatureSym32       : SubtargetFeature<"sym32", "HasSym32", "true",
 168                                           "Symbols are 32 bit on Mips64">;
 169
 170 def FeatureMips16  : SubtargetFeature<"mips16", "InMips16Mode", "true",
 171                                       "Mips16 mode">;
 172
 173 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
 174 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
 175                                     "Mips DSP-R2 ASE", [FeatureDSP]>;
 176 def FeatureDSPR3
 177     : SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE",
 178                        [ FeatureDSP, FeatureDSPR2 ]>;
 179
 180 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
 181
 182 def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">;
 183
 184 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Mips R6 CRC ASE">;
 185
 186 def FeatureVirt : SubtargetFeature<"virt", "HasVirt", "true",
 187                                    "Mips Virtualization ASE">;
 188
 189 def FeatureGINV : SubtargetFeature<"ginv", "HasGINV", "true",
 190                                    "Mips Global Invalidate ASE">;
 191
 192 def FeatureMicroMips  : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
 193                                          "microMips mode">;
 194
 195 def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
 196                                      "true", "Octeon cnMIPS Support",
 197                                      [FeatureMips64r2]>;
 198
 199 def FeatureCnMipsP : SubtargetFeature<"cnmipsp", "HasCnMipsP",
 200                                       "true", "Octeon+ cnMIPS Support",
 201                                       [FeatureCnMips]>;
 202
 203 def FeatureUseTCCInDIV : SubtargetFeature<
 204                                "use-tcc-in-div",
 205                                "UseTCCInDIV", "false",
 206                                "Force the assembler to use trapping">;
 207
 208 def FeatureMadd4
 209     : SubtargetFeature<"nomadd4", "DisableMadd4", "true",
 210                        "Disable 4-operand madd.fmt and related instructions">;
 211
 212 def FeatureMT : SubtargetFeature<"mt", "HasMT", "true", "Mips MT ASE">;
 213
 214 def FeatureLongCalls : SubtargetFeature<"long-calls", "UseLongCalls", "true",
 215                                         "Disable use of the jal instruction">;
 216
 217 def FeatureXGOT
 218     : SubtargetFeature<"xgot", "UseXGOT", "true", "Assume 32-bit GOT">;
 219
 220 def FeatureUseIndirectJumpsHazard : SubtargetFeature<"use-indirect-jump-hazard",
 221                                                     "UseIndirectJumpsHazard",
 222                                                     "true", "Use indirect jump"
 223                         " guards to prevent certain speculation based attacks">;
 224 //===----------------------------------------------------------------------===//
 225 // Mips processors supported.
 226 //===----------------------------------------------------------------------===//
 227
 228 def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
 229                                  "MipsSubtarget::CPU::P5600",
 230                                  "The P5600 Processor", [FeatureMips32r5]>;
 231
 232 class Proc<string Name, list<SubtargetFeature> Features>
 233  : ProcessorModel<Name, MipsGenericModel, Features>;
 234
 235 def : Proc<"generic", [FeatureMips32]>;
 236 def : Proc<"mips1", [FeatureMips1]>;
 237 def : Proc<"mips2", [FeatureMips2]>;
 238 def : Proc<"mips32", [FeatureMips32]>;
 239 def : Proc<"mips32r2", [FeatureMips32r2]>;
 240 def : Proc<"mips32r3", [FeatureMips32r3]>;
 241 def : Proc<"mips32r5", [FeatureMips32r5]>;
 242 def : Proc<"mips32r6", [FeatureMips32r6]>;
 243
 244 def : Proc<"mips3", [FeatureMips3]>;
 245 def : Proc<"mips4", [FeatureMips4]>;
 246 def : Proc<"mips5", [FeatureMips5]>;
 247 def : Proc<"mips64", [FeatureMips64]>;
 248 def : Proc<"mips64r2", [FeatureMips64r2]>;
 249 def : Proc<"mips64r3", [FeatureMips64r3]>;
 250 def : Proc<"mips64r5", [FeatureMips64r5]>;
 251 def : Proc<"mips64r6", [FeatureMips64r6]>;
 252 def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
 253 def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>;
 254 def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
 255
 256 def MipsAsmParser : AsmParser {
 257   let ShouldEmitMatchRegisterName = 0;
 258 }
 259
 260 def MipsAsmParserVariant : AsmParserVariant {
 261   int Variant = 0;
 262
 263   // Recognize hard coded registers.
 264   string RegisterPrefix = "$";
 265 }
 266
 267 def Mips : Target {
 268   let InstructionSet = MipsInstrInfo;
 269   let AssemblyParsers = [MipsAsmParser];
 270   let AssemblyParserVariants = [MipsAsmParserVariant];
 271   let AllowRegisterRenaming = 1;
 272 }
 273
 274 //===----------------------------------------------------------------------===//
 275 // Pfm Counters
 276 //===----------------------------------------------------------------------===//
 277
 278 include "MipsPfmCounters.td"