contrib/llvm-project/llvm/lib/Target/Mips/MipsDSPInstrInfo.td

   1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file describes Mips DSP ASE instructions.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 // ImmLeaf
  14 def immZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}]>;
  15 def timmZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}], NOOP_SDNodeXForm, timm>;
  16 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
  17 def timmZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}], NOOP_SDNodeXForm, timm>;
  18 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
  19 def timmZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}], NOOP_SDNodeXForm, timm>;
  20 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
  21 def timmZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}], NOOP_SDNodeXForm, timm>;
  22 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
  23 def timmZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}], NOOP_SDNodeXForm, timm>;
  24 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
  25 def timmZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}], NOOP_SDNodeXForm, timm>;
  26 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
  27 def timmSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}], NOOP_SDNodeXForm, timm>;
  28 def immSExt10 : ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
  29
  30 // Mips-specific dsp nodes
  31 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
  32                                         SDTCisVT<2, untyped>]>;
  33 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
  34                                          SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
  35 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
  36                                        SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
  37 def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  38                                              SDTCisVT<2, i32>]>;
  39
  40 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
  41   SDNode<!strconcat("MipsISD::", Opc), Prof>;
  42
  43 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
  44   SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
  45
  46 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
  47 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
  48 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
  49 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
  50 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
  51 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
  52
  53 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
  54 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
  55
  56 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
  57 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
  58 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
  59 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
  60 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
  61
  62 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
  63 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
  64 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
  65 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
  66 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
  67 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
  68 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
  69 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
  70
  71 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
  72 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
  73 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
  74 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
  75 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
  76 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
  77 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
  78 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
  79 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
  80
  81 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
  82 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
  83 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
  84 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
  85 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
  86 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
  87 def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
  88 def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
  89 def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
  90 def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>;
  91 def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>;
  92
  93 // Flags.
  94 class Uses<list<Register> Regs> {
  95   list<Register> Uses = Regs;
  96 }
  97
  98 class Defs<list<Register> Regs> {
  99   list<Register> Defs = Regs;
 100 }
 101
 102 // Instruction encoding.
 103 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
 104 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
 105 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
 106 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
 107 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
 108 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
 109 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
 110 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
 111 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
 112 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
 113 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
 114 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
 115 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
 116 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
 117 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
 118 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
 119 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
 120 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
 121 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
 122 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
 123 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
 124 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
 125 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
 126 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
 127 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
 128 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
 129 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
 130 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
 131 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
 132 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
 133 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
 134 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
 135 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
 136 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
 137 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
 138 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
 139 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
 140 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
 141 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
 142 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
 143 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
 144 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
 145 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
 146 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
 147 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
 148 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
 149 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
 150 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
 151 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
 152 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
 153 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
 154 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
 155 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
 156 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
 157 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
 158 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
 159 class MFHI_ENC : MFHI_FMT<0b010000>;
 160 class MFLO_ENC : MFHI_FMT<0b010010>;
 161 class MTHI_ENC : MTHI_FMT<0b010001>;
 162 class MTLO_ENC : MTHI_FMT<0b010011>;
 163 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
 164 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
 165 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
 166 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
 167 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
 168 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
 169 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
 170 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
 171 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
 172 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
 173 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
 174 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
 175 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
 176 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
 177 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
 178 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
 179 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
 180 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
 181 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
 182 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
 183 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
 184 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
 185 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
 186 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
 187 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
 188 class REPL_QB_ENC : REPL_FMT<0b00010>;
 189 class REPL_PH_ENC : REPL_FMT<0b01010>;
 190 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
 191 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
 192 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
 193 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
 194 class LWX_ENC : LX_FMT<0b00000>;
 195 class LHX_ENC : LX_FMT<0b00100>;
 196 class LBUX_ENC : LX_FMT<0b00110>;
 197 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
 198 class INSV_ENC : INSV_FMT<0b001100>;
 199
 200 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
 201 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
 202 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
 203 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
 204 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
 205 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
 206 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
 207 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
 208 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
 209 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
 210 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
 211 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
 212 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
 213 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
 214 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
 215
 216 class RDDSP_ENC : RDDSP_FMT<0b10010>;
 217 class WRDSP_ENC : WRDSP_FMT<0b10011>;
 218 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
 219 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
 220 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
 221 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
 222 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
 223 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
 224 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
 225 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
 226 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
 227 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
 228 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
 229 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
 230 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
 231 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
 232 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
 233 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
 234 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
 235 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
 236 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
 237 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
 238 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
 239 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
 240 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
 241 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
 242 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
 243 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
 244 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
 245 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
 246 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
 247 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
 248 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
 249 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
 250 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
 251 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
 252 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
 253 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
 254 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
 255 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
 256 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
 257 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
 258 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
 259 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
 260 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
 261 class APPEND_ENC : APPEND_FMT<0b00000>;
 262 class BALIGN_ENC : APPEND_FMT<0b10000>;
 263 class PREPEND_ENC : APPEND_FMT<0b00001>;
 264
 265 // Instruction desc.
 266 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 267                         InstrItinClass itin, RegisterOperand ROD,
 268                         RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 269   dag OutOperandList = (outs ROD:$rd);
 270   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 271   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 272   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 273   InstrItinClass Itinerary = itin;
 274   string BaseOpcode = instr_asm;
 275 }
 276
 277 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 278                            InstrItinClass itin, RegisterOperand ROD,
 279                            RegisterOperand ROS = ROD> {
 280   dag OutOperandList = (outs ROD:$rd);
 281   dag InOperandList = (ins ROS:$rs);
 282   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 283   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
 284   InstrItinClass Itinerary = itin;
 285   string BaseOpcode = instr_asm;
 286 }
 287
 288 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 289                              InstrItinClass itin, RegisterOperand ROS,
 290                              RegisterOperand ROT = ROS> {
 291   dag OutOperandList = (outs);
 292   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 293   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
 294   list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
 295   InstrItinClass Itinerary = itin;
 296   string BaseOpcode = instr_asm;
 297 }
 298
 299 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 300                              InstrItinClass itin, RegisterOperand ROD,
 301                              RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 302   dag OutOperandList = (outs ROD:$rd);
 303   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 304   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 305   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 306   InstrItinClass Itinerary = itin;
 307   string BaseOpcode = instr_asm;
 308 }
 309
 310 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 311                                InstrItinClass itin, RegisterOperand ROT,
 312                                RegisterOperand ROS = ROT> {
 313   dag OutOperandList = (outs ROT:$rt);
 314   dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);
 315   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 316   list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, timmZExt5:$sa))];
 317   InstrItinClass Itinerary = itin;
 318   string Constraints = "$src = $rt";
 319   string BaseOpcode = instr_asm;
 320 }
 321
 322 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 323                              InstrItinClass itin, RegisterOperand ROD,
 324                              RegisterOperand ROT = ROD> {
 325   dag OutOperandList = (outs ROD:$rd);
 326   dag InOperandList = (ins ROT:$rt);
 327   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 328   list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
 329   InstrItinClass Itinerary = itin;
 330   string BaseOpcode = instr_asm;
 331 }
 332
 333 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 334                      Operand ImmOp, ImmLeaf immPat, InstrItinClass itin,
 335                      RegisterOperand RO> {
 336   dag OutOperandList = (outs RO:$rd);
 337   dag InOperandList = (ins ImmOp:$imm);
 338   string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
 339   list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
 340   InstrItinClass Itinerary = itin;
 341   string BaseOpcode = instr_asm;
 342 }
 343
 344 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 345                            InstrItinClass itin, RegisterOperand RO> {
 346   dag OutOperandList = (outs RO:$rd);
 347   dag InOperandList =  (ins RO:$rt, GPR32Opnd:$rs_sa);
 348   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 349   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
 350   InstrItinClass Itinerary = itin;
 351   string BaseOpcode = instr_asm;
 352 }
 353
 354 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 355                            SDPatternOperator ImmPat, InstrItinClass itin,
 356                            RegisterOperand RO, Operand ImmOpnd> {
 357   dag OutOperandList = (outs RO:$rd);
 358   dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);
 359   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 360   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
 361   InstrItinClass Itinerary = itin;
 362   bit hasSideEffects = 1;
 363   string BaseOpcode = instr_asm;
 364 }
 365
 366 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 367                    InstrItinClass itin> {
 368   dag OutOperandList = (outs GPR32Opnd:$rd);
 369   dag InOperandList = (ins PtrRC:$base, PtrRC:$index);
 370   string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
 371   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))];
 372   InstrItinClass Itinerary = itin;
 373   bit mayLoad = 1;
 374   string BaseOpcode = instr_asm;
 375 }
 376
 377 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 378                          InstrItinClass itin, RegisterOperand ROD,
 379                          RegisterOperand ROS = ROD, RegisterOperand ROT = ROD> {
 380   dag OutOperandList = (outs ROD:$rd);
 381   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 382   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 383   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 384   InstrItinClass Itinerary = itin;
 385   string BaseOpcode = instr_asm;
 386 }
 387
 388 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 389                        Operand ImmOp, SDPatternOperator Imm,
 390                        InstrItinClass itin> {
 391   dag OutOperandList = (outs GPR32Opnd:$rt);
 392   dag InOperandList = (ins GPR32Opnd:$rs, ImmOp:$sa, GPR32Opnd:$src);
 393   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 394   list<dag> Pattern =  [(set GPR32Opnd:$rt,
 395                         (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, Imm:$sa))];
 396   InstrItinClass Itinerary = itin;
 397   string Constraints = "$src = $rt";
 398   string BaseOpcode = instr_asm;
 399 }
 400
 401 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 402                               InstrItinClass itin> {
 403   dag OutOperandList = (outs GPR32Opnd:$rt);
 404   dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);
 405   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 406   InstrItinClass Itinerary = itin;
 407   string BaseOpcode = instr_asm;
 408 }
 409
 410 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 411                               InstrItinClass itin> {
 412   dag OutOperandList = (outs GPR32Opnd:$rt);
 413   dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm5:$shift_rs);
 414   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 415   InstrItinClass Itinerary = itin;
 416   string BaseOpcode = instr_asm;
 417 }
 418
 419 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 420   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 421   dag InOperandList = (ins simm6:$shift, ACC64DSPOpnd:$acin);
 422   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
 423   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 424                         (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))];
 425   string Constraints = "$acin = $ac";
 426   string BaseOpcode = instr_asm;
 427 }
 428
 429 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 430   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 431   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 432   string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
 433   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 434                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 435   string Constraints = "$acin = $ac";
 436   string BaseOpcode = instr_asm;
 437 }
 438
 439 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 440   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 441   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 442   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 443   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 444                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 445   string Constraints = "$acin = $ac";
 446   string BaseOpcode = instr_asm;
 447 }
 448
 449 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 450                       InstrItinClass itin> {
 451   dag OutOperandList = (outs GPR32Opnd:$rd);
 452   dag InOperandList = (ins uimm10:$mask);
 453   string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
 454   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode timmZExt10:$mask))];
 455   InstrItinClass Itinerary = itin;
 456   string BaseOpcode = instr_asm;
 457   bit isMoveReg = 1;
 458 }
 459
 460 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 461                       InstrItinClass itin> {
 462   dag OutOperandList = (outs);
 463   dag InOperandList = (ins GPR32Opnd:$rs, uimm10:$mask);
 464   string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
 465   list<dag> Pattern = [(OpNode GPR32Opnd:$rs, timmZExt10:$mask)];
 466   InstrItinClass Itinerary = itin;
 467   string BaseOpcode = instr_asm;
 468   bit isMoveReg = 1;
 469 }
 470
 471 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 472   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 473   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 474   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 475   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 476                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 477   string Constraints = "$acin = $ac";
 478   string BaseOpcode = instr_asm;
 479 }
 480
 481 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 482                      InstrItinClass itin> {
 483   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 484   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt);
 485   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 486   list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))];
 487   InstrItinClass Itinerary = itin;
 488   bit isCommutable = 1;
 489   string BaseOpcode = instr_asm;
 490 }
 491
 492 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 493                      InstrItinClass itin> {
 494   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 495   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 496   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 497   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 498                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 499   InstrItinClass Itinerary = itin;
 500   string Constraints = "$acin = $ac";
 501   string BaseOpcode = instr_asm;
 502 }
 503
 504 class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
 505                      InstrItinClass itin> {
 506   dag OutOperandList = (outs GPR32Opnd:$rd);
 507   dag InOperandList = (ins RO:$ac);
 508   string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
 509   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
 510   InstrItinClass Itinerary = itin;
 511   string BaseOpcode = instr_asm;
 512   bit isMoveReg = 1;
 513 }
 514
 515 class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO,
 516                      InstrItinClass itin> {
 517   dag OutOperandList = (outs RO:$ac);
 518   dag InOperandList = (ins GPR32Opnd:$rs);
 519   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 520   InstrItinClass Itinerary = itin;
 521   string BaseOpcode = instr_asm;
 522   bit isMoveReg = 1;
 523 }
 524
 525 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
 526   MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {
 527   bit hasNoSchedulingInfo = 1;
 528   bit usesCustomInserter = 1;
 529 }
 530
 531 class BPOSGE32_DESC_BASE<string instr_asm, DAGOperand opnd,
 532                          InstrItinClass itin> {
 533   dag OutOperandList = (outs);
 534   dag InOperandList = (ins opnd:$offset);
 535   string AsmString = !strconcat(instr_asm, "\t$offset");
 536   InstrItinClass Itinerary = itin;
 537   bit isBranch = 1;
 538   bit isTerminator = 1;
 539   bit hasDelaySlot = 1;
 540   string BaseOpcode = instr_asm;
 541 }
 542
 543 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 544                      InstrItinClass itin> {
 545   dag OutOperandList = (outs GPR32Opnd:$rt);
 546   dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs);
 547   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 548   list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];
 549   InstrItinClass Itinerary = itin;
 550   string Constraints = "$src = $rt";
 551   string BaseOpcode = instr_asm;
 552 }
 553
 554 //===----------------------------------------------------------------------===//
 555 // MIPS DSP Rev 1
 556 //===----------------------------------------------------------------------===//
 557
 558 // Addition/subtraction
 559 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
 560                                        DSPROpnd, DSPROpnd>, IsCommutable,
 561                      Defs<[DSPOutFlag20]>;
 562
 563 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
 564                                          NoItinerary, DSPROpnd, DSPROpnd>,
 565                        IsCommutable, Defs<[DSPOutFlag20]>;
 566
 567 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
 568                                        DSPROpnd, DSPROpnd>,
 569                      Defs<[DSPOutFlag20]>;
 570
 571 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
 572                                          NoItinerary, DSPROpnd, DSPROpnd>,
 573                        Defs<[DSPOutFlag20]>;
 574
 575 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
 576                                        DSPROpnd, DSPROpnd>, IsCommutable,
 577                      Defs<[DSPOutFlag20]>;
 578
 579 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
 580                                          NoItinerary, DSPROpnd, DSPROpnd>,
 581                        IsCommutable, Defs<[DSPOutFlag20]>;
 582
 583 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
 584                                        DSPROpnd, DSPROpnd>,
 585                      Defs<[DSPOutFlag20]>;
 586
 587 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
 588                                          NoItinerary, DSPROpnd, DSPROpnd>,
 589                        Defs<[DSPOutFlag20]>;
 590
 591 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
 592                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 593                       IsCommutable, Defs<[DSPOutFlag20]>;
 594
 595 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
 596                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 597                       Defs<[DSPOutFlag20]>;
 598
 599 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
 600                                      GPR32Opnd, GPR32Opnd>, IsCommutable,
 601                    Defs<[DSPCarry]>;
 602
 603 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
 604                                      GPR32Opnd, GPR32Opnd>,
 605                    IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>;
 606
 607 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
 608                                       GPR32Opnd, GPR32Opnd>;
 609
 610 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
 611                                              NoItinerary, GPR32Opnd, DSPROpnd>;
 612
 613 // Absolute value
 614 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
 615                                               NoItinerary, DSPROpnd>,
 616                        Defs<[DSPOutFlag20]>;
 617
 618 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
 619                                              NoItinerary, GPR32Opnd>,
 620                       Defs<[DSPOutFlag20]>;
 621
 622 // Precision reduce/expand
 623 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
 624                                                  int_mips_precrq_qb_ph,
 625                                                  NoItinerary, DSPROpnd, DSPROpnd>;
 626
 627 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
 628                                                 int_mips_precrq_ph_w,
 629                                                 NoItinerary, DSPROpnd, GPR32Opnd>;
 630
 631 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
 632                                                    int_mips_precrq_rs_ph_w,
 633                                                    NoItinerary, DSPROpnd,
 634                                                    GPR32Opnd>,
 635                             Defs<[DSPOutFlag22]>;
 636
 637 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
 638                                                     int_mips_precrqu_s_qb_ph,
 639                                                     NoItinerary, DSPROpnd,
 640                                                     DSPROpnd>,
 641                              Defs<[DSPOutFlag22]>;
 642
 643 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
 644                                                  int_mips_preceq_w_phl,
 645                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 646
 647 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
 648                                                  int_mips_preceq_w_phr,
 649                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 650
 651 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
 652                                                    int_mips_precequ_ph_qbl,
 653                                                    NoItinerary, DSPROpnd>;
 654
 655 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
 656                                                    int_mips_precequ_ph_qbr,
 657                                                    NoItinerary, DSPROpnd>;
 658
 659 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
 660                                                     int_mips_precequ_ph_qbla,
 661                                                     NoItinerary, DSPROpnd>;
 662
 663 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
 664                                                     int_mips_precequ_ph_qbra,
 665                                                     NoItinerary, DSPROpnd>;
 666
 667 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
 668                                                   int_mips_preceu_ph_qbl,
 669                                                   NoItinerary, DSPROpnd>;
 670
 671 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
 672                                                   int_mips_preceu_ph_qbr,
 673                                                   NoItinerary, DSPROpnd>;
 674
 675 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
 676                                                    int_mips_preceu_ph_qbla,
 677                                                    NoItinerary, DSPROpnd>;
 678
 679 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
 680                                                    int_mips_preceu_ph_qbra,
 681                                                    NoItinerary, DSPROpnd>;
 682
 683 // Shift
 684 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
 685                                           NoItinerary, DSPROpnd, uimm3>,
 686                      Defs<[DSPOutFlag22]>;
 687
 688 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
 689                                            NoItinerary, DSPROpnd>,
 690                       Defs<[DSPOutFlag22]>;
 691
 692 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
 693                                           NoItinerary, DSPROpnd, uimm3>;
 694
 695 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
 696                                            NoItinerary, DSPROpnd>;
 697
 698 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
 699                                           NoItinerary, DSPROpnd, uimm4>,
 700                      Defs<[DSPOutFlag22]>;
 701
 702 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
 703                                            NoItinerary, DSPROpnd>,
 704                       Defs<[DSPOutFlag22]>;
 705
 706 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
 707                                             immZExt4, NoItinerary, DSPROpnd,
 708                                             uimm4>,
 709                        Defs<[DSPOutFlag22]>;
 710
 711 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
 712                                              NoItinerary, DSPROpnd>,
 713                         Defs<[DSPOutFlag22]>;
 714
 715 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
 716                                           NoItinerary, DSPROpnd, uimm4>;
 717
 718 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
 719                                            NoItinerary, DSPROpnd>;
 720
 721 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
 722                                             immZExt4, NoItinerary, DSPROpnd,
 723                                             uimm4>;
 724
 725 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
 726                                              NoItinerary, DSPROpnd>;
 727
 728 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
 729                                            immZExt5, NoItinerary, GPR32Opnd,
 730                                            uimm5>,
 731                       Defs<[DSPOutFlag22]>;
 732
 733 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
 734                                             NoItinerary, GPR32Opnd>,
 735                        Defs<[DSPOutFlag22]>;
 736
 737 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
 738                                            immZExt5, NoItinerary, GPR32Opnd,
 739                                            uimm5>;
 740
 741 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
 742                                             NoItinerary, GPR32Opnd>;
 743
 744 // Multiplication
 745 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
 746                                               int_mips_muleu_s_ph_qbl,
 747                                               NoItinerary, DSPROpnd, DSPROpnd>,
 748                             Defs<[DSPOutFlag21]>;
 749
 750 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
 751                                               int_mips_muleu_s_ph_qbr,
 752                                               NoItinerary, DSPROpnd, DSPROpnd>,
 753                             Defs<[DSPOutFlag21]>;
 754
 755 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
 756                                              int_mips_muleq_s_w_phl,
 757                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 758                            IsCommutable, Defs<[DSPOutFlag21]>;
 759
 760 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
 761                                              int_mips_muleq_s_w_phr,
 762                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 763                            IsCommutable, Defs<[DSPOutFlag21]>;
 764
 765 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
 766                                           NoItinerary, DSPROpnd, DSPROpnd>,
 767                         IsCommutable, Defs<[DSPOutFlag21]>;
 768
 769 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
 770                                               MipsMULSAQ_S_W_PH>,
 771                            Defs<[DSPOutFlag16_19]>;
 772
 773 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>,
 774                          Defs<[DSPOutFlag16_19]>;
 775
 776 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>,
 777                          Defs<[DSPOutFlag16_19]>;
 778
 779 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>,
 780                           Defs<[DSPOutFlag16_19]>;
 781
 782 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>,
 783                           Defs<[DSPOutFlag16_19]>;
 784
 785 // Move from/to hi/lo.
 786 class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, NoItinerary>;
 787 class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, NoItinerary>;
 788 class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>;
 789 class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>;
 790
 791 // Dot product with accumulate/subtract
 792 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
 793
 794 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
 795
 796 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
 797
 798 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
 799
 800 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>,
 801                          Defs<[DSPOutFlag16_19]>;
 802
 803 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>,
 804                          Defs<[DSPOutFlag16_19]>;
 805
 806 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>,
 807                          Defs<[DSPOutFlag16_19]>;
 808
 809 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>,
 810                          Defs<[DSPOutFlag16_19]>;
 811
 812 class MULT_DSP_DESC  : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
 813 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
 814 class MADD_DSP_DESC  : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
 815 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
 816 class MSUB_DSP_DESC  : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
 817 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
 818
 819 // Comparison
 820 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
 821                                                int_mips_cmpu_eq_qb, NoItinerary,
 822                                                DSPROpnd>,
 823                         IsCommutable, Defs<[DSPCCond]>;
 824
 825 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
 826                                                int_mips_cmpu_lt_qb, NoItinerary,
 827                                                DSPROpnd>, Defs<[DSPCCond]>;
 828
 829 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
 830                                                int_mips_cmpu_le_qb, NoItinerary,
 831                                                DSPROpnd>, Defs<[DSPCCond]>;
 832
 833 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
 834                                                 int_mips_cmpgu_eq_qb,
 835                                                 NoItinerary, GPR32Opnd, DSPROpnd>,
 836                          IsCommutable;
 837
 838 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
 839                                                 int_mips_cmpgu_lt_qb,
 840                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 841
 842 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
 843                                                 int_mips_cmpgu_le_qb,
 844                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 845
 846 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
 847                                               NoItinerary, DSPROpnd>,
 848                        IsCommutable, Defs<[DSPCCond]>;
 849
 850 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
 851                                               NoItinerary, DSPROpnd>,
 852                        Defs<[DSPCCond]>;
 853
 854 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
 855                                               NoItinerary, DSPROpnd>,
 856                        Defs<[DSPCCond]>;
 857
 858 // Misc
 859 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 860                                            NoItinerary, GPR32Opnd>;
 861
 862 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
 863                                               NoItinerary, DSPROpnd, DSPROpnd>;
 864
 865 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, uimm8,
 866                                     immZExt8, NoItinerary, DSPROpnd>;
 867
 868 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, simm10,
 869                                     immSExt10, NoItinerary, DSPROpnd>;
 870
 871 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
 872                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 873
 874 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
 875                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 876
 877 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
 878                                             NoItinerary, DSPROpnd, DSPROpnd>,
 879                      Uses<[DSPCCond]>;
 880
 881 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
 882                                             NoItinerary, DSPROpnd, DSPROpnd>,
 883                      Uses<[DSPCCond]>;
 884
 885 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
 886
 887 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
 888
 889 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
 890
 891 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget, NoItinerary>;
 892
 893 // Extr
 894 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
 895                   Uses<[DSPPos]>, Defs<[DSPEFI]>;
 896
 897 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
 898                    Uses<[DSPPos]>, Defs<[DSPEFI]>;
 899
 900 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,
 901                     Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 902
 903 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
 904                                              NoItinerary>,
 905                      Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 906
 907 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
 908                     Defs<[DSPOutFlag23]>;
 909
 910 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
 911                                              NoItinerary>, Defs<[DSPOutFlag23]>;
 912
 913 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
 914                                               NoItinerary>,
 915                       Defs<[DSPOutFlag23]>;
 916
 917 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
 918                                                NoItinerary>,
 919                        Defs<[DSPOutFlag23]>;
 920
 921 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
 922                                                NoItinerary>,
 923                        Defs<[DSPOutFlag23]>;
 924
 925 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
 926                                                 NoItinerary>,
 927                         Defs<[DSPOutFlag23]>;
 928
 929 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
 930                                               NoItinerary>,
 931                       Defs<[DSPOutFlag23]>;
 932
 933 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
 934                                                NoItinerary>,
 935                        Defs<[DSPOutFlag23]>;
 936
 937 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
 938
 939 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
 940
 941 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>;
 942
 943 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
 944
 945 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
 946
 947 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,
 948                   Uses<[DSPPos, DSPSCount]>;
 949
 950 //===----------------------------------------------------------------------===//
 951 // MIPS DSP Rev 2
 952 // Addition/subtraction
 953 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
 954                                        DSPROpnd, DSPROpnd>, IsCommutable,
 955                      Defs<[DSPOutFlag20]>;
 956
 957 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
 958                                          NoItinerary, DSPROpnd, DSPROpnd>,
 959                        IsCommutable, Defs<[DSPOutFlag20]>;
 960
 961 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
 962                                        DSPROpnd, DSPROpnd>,
 963                      Defs<[DSPOutFlag20]>;
 964
 965 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
 966                                          NoItinerary, DSPROpnd, DSPROpnd>,
 967                        Defs<[DSPOutFlag20]>;
 968
 969 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
 970                                          NoItinerary, DSPROpnd>, IsCommutable;
 971
 972 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
 973                                            NoItinerary, DSPROpnd>, IsCommutable;
 974
 975 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
 976                                          NoItinerary, DSPROpnd>;
 977
 978 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
 979                                            NoItinerary, DSPROpnd>;
 980
 981 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
 982                                          NoItinerary, DSPROpnd>, IsCommutable;
 983
 984 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
 985                                            NoItinerary, DSPROpnd>, IsCommutable;
 986
 987 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
 988                                          NoItinerary, DSPROpnd>;
 989
 990 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
 991                                            NoItinerary, DSPROpnd>;
 992
 993 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
 994                                         NoItinerary, GPR32Opnd>, IsCommutable;
 995
 996 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
 997                                           NoItinerary, GPR32Opnd>, IsCommutable;
 998
 999 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
1000                                         NoItinerary, GPR32Opnd>;
1001
1002 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
1003                                           NoItinerary, GPR32Opnd>;
1004
1005 // Comparison
1006 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
1007                                                  int_mips_cmpgdu_eq_qb,
1008                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
1009                           IsCommutable, Defs<[DSPCCond]>;
1010
1011 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
1012                                                  int_mips_cmpgdu_lt_qb,
1013                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
1014                           Defs<[DSPCCond]>;
1015
1016 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
1017                                                  int_mips_cmpgdu_le_qb,
1018                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
1019                           Defs<[DSPCCond]>;
1020
1021 // Absolute
1022 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
1023                                               NoItinerary, DSPROpnd>,
1024                        Defs<[DSPOutFlag20]>;
1025
1026 // Multiplication
1027 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
1028                                        DSPROpnd>, IsCommutable,
1029                     Defs<[DSPOutFlag21]>;
1030
1031 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
1032                                          NoItinerary, DSPROpnd>, IsCommutable,
1033                       Defs<[DSPOutFlag21]>;
1034
1035 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
1036                                          NoItinerary, GPR32Opnd>, IsCommutable,
1037                       Defs<[DSPOutFlag21]>;
1038
1039 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
1040                                           NoItinerary, GPR32Opnd>, IsCommutable,
1041                        Defs<[DSPOutFlag21]>;
1042
1043 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
1044                                          NoItinerary, DSPROpnd, DSPROpnd>,
1045                        IsCommutable, Defs<[DSPOutFlag21]>;
1046
1047 // Dot product with accumulate/subtract
1048 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
1049
1050 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
1051
1052 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>,
1053                           Defs<[DSPOutFlag16_19]>;
1054
1055 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
1056                                               MipsDPAQX_SA_W_PH>,
1057                            Defs<[DSPOutFlag16_19]>;
1058
1059 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
1060
1061 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
1062
1063 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>,
1064                           Defs<[DSPOutFlag16_19]>;
1065
1066 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
1067                                               MipsDPSQX_SA_W_PH>,
1068                            Defs<[DSPOutFlag16_19]>;
1069
1070 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
1071
1072 // Precision reduce/expand
1073 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
1074                                                 int_mips_precr_qb_ph,
1075                                                 NoItinerary, DSPROpnd, DSPROpnd>;
1076
1077 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1078                                                      int_mips_precr_sra_ph_w,
1079                                                      NoItinerary, DSPROpnd,
1080                                                      GPR32Opnd>;
1081
1082 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1083                                                       int_mips_precr_sra_r_ph_w,
1084                                                        NoItinerary, DSPROpnd,
1085                                                        GPR32Opnd>;
1086
1087 // Shift
1088 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
1089                                           NoItinerary, DSPROpnd, uimm3>;
1090
1091 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1092                                            NoItinerary, DSPROpnd>;
1093
1094 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1095                                             immZExt3, NoItinerary, DSPROpnd,
1096                                             uimm3>;
1097
1098 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1099                                              NoItinerary, DSPROpnd>;
1100
1101 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
1102                                           NoItinerary, DSPROpnd, uimm4>;
1103
1104 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1105                                            NoItinerary, DSPROpnd>;
1106
1107 // Misc
1108 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, uimm5, timmZExt5,
1109                                      NoItinerary>;
1110
1111 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, uimm2, timmZExt2,
1112                                      NoItinerary>;
1113
1114 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, uimm5,
1115                                       timmZExt5, NoItinerary>;
1116
1117 // Pseudos.
1118 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
1119                                                 NoItinerary>, Uses<[DSPPos]>;
1120
1121 // Instruction defs.
1122 // MIPS DSP Rev 1
1123 def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
1124 def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1125 def SUBU_QB : DspMMRel, SUBU_QB_ENC, SUBU_QB_DESC;
1126 def SUBU_S_QB : DspMMRel, SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1127 def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
1128 def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1129 def SUBQ_PH : DspMMRel, SUBQ_PH_ENC, SUBQ_PH_DESC;
1130 def SUBQ_S_PH : DspMMRel, SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1131 def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1132 def SUBQ_S_W : DspMMRel, SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1133 def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
1134 def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
1135 def MODSUB : DspMMRel, MODSUB_ENC, MODSUB_DESC;
1136 def RADDU_W_QB : DspMMRel, RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1137 def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1138 def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1139 def PRECRQ_QB_PH : DspMMRel, PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1140 def PRECRQ_PH_W : DspMMRel, PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1141 def PRECRQ_RS_PH_W : DspMMRel, PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1142 def PRECRQU_S_QB_PH : DspMMRel, PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1143 def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1144 def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1145 def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1146 def PRECEQU_PH_QBR : DspMMRel, PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1147 def PRECEQU_PH_QBLA : DspMMRel, PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1148 def PRECEQU_PH_QBRA : DspMMRel, PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1149 def PRECEU_PH_QBL : DspMMRel, PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1150 def PRECEU_PH_QBR : DspMMRel, PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1151 def PRECEU_PH_QBLA : DspMMRel, PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1152 def PRECEU_PH_QBRA : DspMMRel, PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1153 def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC;
1154 def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC;
1155 def SHRL_QB : DspMMRel, SHRL_QB_ENC, SHRL_QB_DESC;
1156 def SHRLV_QB : DspMMRel, SHRLV_QB_ENC, SHRLV_QB_DESC;
1157 def SHLL_PH : DspMMRel, SHLL_PH_ENC, SHLL_PH_DESC;
1158 def SHLLV_PH : DspMMRel, SHLLV_PH_ENC, SHLLV_PH_DESC;
1159 def SHLL_S_PH : DspMMRel, SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1160 def SHLLV_S_PH : DspMMRel, SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1161 def SHRA_PH : DspMMRel, SHRA_PH_ENC, SHRA_PH_DESC;
1162 def SHRAV_PH : DspMMRel, SHRAV_PH_ENC, SHRAV_PH_DESC;
1163 def SHRA_R_PH : DspMMRel, SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1164 def SHRAV_R_PH : DspMMRel, SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1165 def SHLL_S_W : DspMMRel, SHLL_S_W_ENC, SHLL_S_W_DESC;
1166 def SHLLV_S_W : DspMMRel, SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1167 def SHRA_R_W : DspMMRel, SHRA_R_W_ENC, SHRA_R_W_DESC;
1168 def SHRAV_R_W : DspMMRel, SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1169 def MULEU_S_PH_QBL : DspMMRel, MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1170 def MULEU_S_PH_QBR : DspMMRel, MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1171 def MULEQ_S_W_PHL : DspMMRel, MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1172 def MULEQ_S_W_PHR : DspMMRel, MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1173 def MULQ_RS_PH : DspMMRel, MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1174 def MULSAQ_S_W_PH : DspMMRel, MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1175 def MAQ_S_W_PHL : DspMMRel, MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1176 def MAQ_S_W_PHR : DspMMRel, MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1177 def MAQ_SA_W_PHL : DspMMRel, MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1178 def MAQ_SA_W_PHR : DspMMRel, MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1179 def MFHI_DSP : DspMMRel, MFHI_ENC, MFHI_DESC;
1180 def MFLO_DSP : DspMMRel, MFLO_ENC, MFLO_DESC;
1181 def MTHI_DSP : DspMMRel, MTHI_ENC, MTHI_DESC;
1182 def MTLO_DSP : DspMMRel, MTLO_ENC, MTLO_DESC;
1183 def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1184 def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1185 def DPSU_H_QBL : DspMMRel, DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1186 def DPSU_H_QBR : DspMMRel, DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1187 def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1188 def DPSQ_S_W_PH : DspMMRel, DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1189 def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1190 def DPSQ_SA_L_W : DspMMRel, DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1191 def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC;
1192 def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC;
1193 def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;
1194 def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC;
1195 def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC;
1196 def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1197 def CMPU_EQ_QB : DspMMRel, CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1198 def CMPU_LT_QB : DspMMRel, CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1199 def CMPU_LE_QB : DspMMRel, CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1200 def CMPGU_EQ_QB : DspMMRel, CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1201 def CMPGU_LT_QB : DspMMRel, CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1202 def CMPGU_LE_QB : DspMMRel, CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1203 def CMP_EQ_PH : DspMMRel, CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1204 def CMP_LT_PH : DspMMRel, CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1205 def CMP_LE_PH : DspMMRel, CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1206 def BITREV : DspMMRel, BITREV_ENC, BITREV_DESC;
1207 def PACKRL_PH : DspMMRel, PACKRL_PH_ENC, PACKRL_PH_DESC;
1208 def REPL_QB : DspMMRel, REPL_QB_ENC, REPL_QB_DESC;
1209 def REPL_PH : DspMMRel, REPL_PH_ENC, REPL_PH_DESC;
1210 def REPLV_QB : DspMMRel, REPLV_QB_ENC, REPLV_QB_DESC;
1211 def REPLV_PH : DspMMRel, REPLV_PH_ENC, REPLV_PH_DESC;
1212 def PICK_QB : DspMMRel, PICK_QB_ENC, PICK_QB_DESC;
1213 def PICK_PH : DspMMRel, PICK_PH_ENC, PICK_PH_DESC;
1214 def LWX : DspMMRel, LWX_ENC, LWX_DESC;
1215 def LHX : DspMMRel, LHX_ENC, LHX_DESC;
1216 def LBUX : DspMMRel, LBUX_ENC, LBUX_DESC;
1217 let AdditionalPredicates = [NotInMicroMips] in {
1218   def BPOSGE32 : DspMMRel, BPOSGE32_ENC, BPOSGE32_DESC;
1219 }
1220 def INSV : DspMMRel, INSV_ENC, INSV_DESC;
1221 def EXTP : DspMMRel, EXTP_ENC, EXTP_DESC;
1222 def EXTPV : DspMMRel, EXTPV_ENC, EXTPV_DESC;
1223 def EXTPDP : DspMMRel, EXTPDP_ENC, EXTPDP_DESC;
1224 def EXTPDPV : DspMMRel, EXTPDPV_ENC, EXTPDPV_DESC;
1225 def EXTR_W : DspMMRel, EXTR_W_ENC, EXTR_W_DESC;
1226 def EXTRV_W : DspMMRel, EXTRV_W_ENC, EXTRV_W_DESC;
1227 def EXTR_R_W : DspMMRel, EXTR_R_W_ENC, EXTR_R_W_DESC;
1228 def EXTRV_R_W : DspMMRel, EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1229 def EXTR_RS_W : DspMMRel, EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1230 def EXTRV_RS_W : DspMMRel, EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1231 def EXTR_S_H : DspMMRel, EXTR_S_H_ENC, EXTR_S_H_DESC;
1232 def EXTRV_S_H : DspMMRel, EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1233 def SHILO : DspMMRel, SHILO_ENC, SHILO_DESC;
1234 def SHILOV : DspMMRel, SHILOV_ENC, SHILOV_DESC;
1235 def MTHLIP : DspMMRel, MTHLIP_ENC, MTHLIP_DESC;
1236 def RDDSP : DspMMRel, RDDSP_ENC, RDDSP_DESC;
1237 let AdditionalPredicates = [NotInMicroMips] in {
1238   def WRDSP : WRDSP_ENC, WRDSP_DESC;
1239 }
1240
1241 // MIPS DSP Rev 2
1242 def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC, ISA_DSPR2;
1243 def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC, ISA_DSPR2;
1244 def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC, ISA_DSPR2;
1245 def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC, ISA_DSPR2;
1246 def CMPGDU_EQ_QB : DspMMRel, CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC, ISA_DSPR2;
1247 def CMPGDU_LT_QB : DspMMRel, CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC, ISA_DSPR2;
1248 def CMPGDU_LE_QB : DspMMRel, CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC, ISA_DSPR2;
1249 def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC, ISA_DSPR2;
1250 def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC, ISA_DSPR2;
1251 def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC, ISA_DSPR2;
1252 def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC, ISA_DSPR2;
1253 def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC, ISA_DSPR2;
1254 def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC, ISA_DSPR2;
1255 def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
1256 def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC, ISA_DSPR2;
1257 def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC, ISA_DSPR2;
1258 def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC, ISA_DSPR2;
1259 def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC, ISA_DSPR2;
1260 def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC, ISA_DSPR2;
1261 def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC, ISA_DSPR2;
1262 def MUL_PH : DspMMRel, MUL_PH_ENC, MUL_PH_DESC, ISA_DSPR2;
1263 def MUL_S_PH : DspMMRel, MUL_S_PH_ENC, MUL_S_PH_DESC, ISA_DSPR2;
1264 def MULQ_S_W : DspMMRel, MULQ_S_W_ENC, MULQ_S_W_DESC, ISA_DSPR2;
1265 def MULQ_RS_W : DspMMRel, MULQ_RS_W_ENC, MULQ_RS_W_DESC, ISA_DSPR2;
1266 def MULQ_S_PH : DspMMRel, MULQ_S_PH_ENC, MULQ_S_PH_DESC, ISA_DSPR2;
1267 def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC, ISA_DSPR2;
1268 def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC, ISA_DSPR2;
1269 def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC, ISA_DSPR2;
1270 def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC, ISA_DSPR2;
1271 def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC, ISA_DSPR2;
1272 def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC, ISA_DSPR2;
1273 def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC, ISA_DSPR2;
1274 def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC, ISA_DSPR2;
1275 def MULSA_W_PH : DspMMRel, MULSA_W_PH_ENC, MULSA_W_PH_DESC, ISA_DSPR2;
1276 def PRECR_QB_PH : DspMMRel, PRECR_QB_PH_ENC, PRECR_QB_PH_DESC, ISA_DSPR2;
1277 def PRECR_SRA_PH_W : DspMMRel, PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC, ISA_DSPR2;
1278 def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC, ISA_DSPR2;
1279 def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC, ISA_DSPR2;
1280 def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC, ISA_DSPR2;
1281 def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC, ISA_DSPR2;
1282 def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC, ISA_DSPR2;
1283 def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC, ISA_DSPR2;
1284 def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC, ISA_DSPR2;
1285 def APPEND : DspMMRel, APPEND_ENC, APPEND_DESC, ISA_DSPR2;
1286 def BALIGN : DspMMRel, BALIGN_ENC, BALIGN_DESC, ISA_DSPR2;
1287 def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC, ISA_DSPR2;
1288
1289 // Pseudos.
1290 let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
1291   // Pseudo instructions for loading and storing accumulator registers.
1292   def LOAD_ACC64DSP  : Load<"", ACC64DSPOpnd>;
1293   def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;
1294
1295   // Pseudos for loading and storing ccond field of DSP control register.
1296   def LOAD_CCOND_DSP  : Load<"load_ccond_dsp", DSPCC>;
1297   def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
1298 }
1299
1300 let DecoderNamespace = "MipsDSP", Arch = "dsp",
1301     ASEPredicate = [HasDSP] in {
1302   def LWDSP : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel, LW_FM<0x23>;
1303   def SWDSP : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel, LW_FM<0x2b>;
1304 }
1305
1306 // Pseudo CMP and PICK instructions.
1307 class PseudoCMP<Instruction RealInst> :
1308   PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
1309   PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>,
1310   NeverHasSideEffects;
1311
1312 class PseudoPICK<Instruction RealInst> :
1313   PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,
1314   PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>,
1315   NeverHasSideEffects;
1316
1317 def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;
1318 def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>;
1319 def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;
1320 def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;
1321 def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;
1322 def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;
1323
1324 def PseudoPICK_PH : PseudoPICK<PICK_PH>;
1325 def PseudoPICK_QB : PseudoPICK<PICK_QB>;
1326
1327 let AdditionalPredicates = [HasDSP] in {
1328   def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>;
1329 }
1330
1331 // Patterns.
1332 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1333   Pat<pattern, result>, Requires<[pred]>;
1334
1335 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1336                     RegisterClass SrcRC> :
1337    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1338           (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1339
1340 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1341 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1342 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1343 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1344 def : BitconvertPat<f32, v2i16, FGR32, DSPR>;
1345 def : BitconvertPat<f32, v4i8, FGR32, DSPR>;
1346 def : BitconvertPat<v2i16, f32, DSPR, FGR32>;
1347 def : BitconvertPat<v4i8, f32, DSPR, FGR32>;
1348
1349 def : DSPPat<(v2i16 (load addr:$a)),
1350              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1351 def : DSPPat<(v4i8 (load addr:$a)),
1352              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1353 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1354              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1355 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1356              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1357
1358 // Binary operations.
1359 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1360                 Predicate Pred = HasDSP> :
1361   DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
1362
1363 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1364 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1365 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1366 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1367 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1368 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1369 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1370 def : DSPBinPat<ADDU_QB, v4i8, add>;
1371 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1372 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1373 def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
1374 def : DSPBinPat<ADDSC, i32, addc>;
1375 def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
1376 def : DSPBinPat<ADDWC, i32, adde>;
1377
1378 // Shift immediate patterns.
1379 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1380                   SDPatternOperator Imm, Predicate Pred = HasDSP> :
1381   DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
1382
1383 def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
1384 def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
1385 def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
1386 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
1387 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
1388 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
1389 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
1390 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
1391 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
1392 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
1393 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
1394 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
1395
1396 // SETCC/SELECT_CC patterns.
1397 class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1398                   CondCode CC> :
1399   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1400          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1401                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1402                       (ValTy ZERO)))>;
1403
1404 class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1405                      CondCode CC> :
1406   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1407          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1408                       (ValTy ZERO),
1409                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
1410
1411 class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1412                      CondCode CC> :
1413   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1414          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>;
1415
1416 class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1417                         CondCode CC> :
1418   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1419          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>;
1420
1421 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1422 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1423 def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1424 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1425 def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1426 def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1427 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1428 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1429 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1430 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1431 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1432 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1433
1434 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1435 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1436 def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1437 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1438 def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1439 def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1440 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1441 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1442 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1443 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1444 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1445 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1446
1447 // Extr patterns.
1448 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1449   DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
1450          (Instr ACC64DSP:$ac, GPR32:$rs)>;
1451
1452 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1453   DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)),
1454          (Instr ACC64DSP:$ac, immZExt5:$shift)>;
1455
1456 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1457 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1458 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1459 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1460 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1461 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1462 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1463 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1464 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1465 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1466 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1467 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
1468
1469 // Indexed load patterns.
1470 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
1471   DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
1472          (Instr i32:$base, i32:$index)>;
1473
1474 let AddedComplexity = 20 in {
1475   def : IndexedLoadPat<zextloadi8, LBUX>;
1476   def : IndexedLoadPat<sextloadi16, LHX>;
1477   def : IndexedLoadPat<load, LWX>;
1478 }
1479
1480 // Instruction alias.
1481 let AdditionalPredicates = [NotInMicroMips] in {
1482   def : DSPInstAlias<"wrdsp $rt", (WRDSP GPR32Opnd:$rt, 0x1F), 1>;
1483 }