contrib/llvm-project/llvm/lib/Target/Mips/MipsDSPInstrInfo.td

   1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file describes Mips DSP ASE instructions.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 // ImmLeaf
  14 def immZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}]>;
  15 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
  16 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
  17 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
  18 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
  19 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
  20 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
  21 def immSExt10 : ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
  22
  23 // Mips-specific dsp nodes
  24 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
  25                                         SDTCisVT<2, untyped>]>;
  26 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
  27                                          SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
  28 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
  29                                        SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
  30 def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  31                                              SDTCisVT<2, i32>]>;
  32
  33 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
  34   SDNode<!strconcat("MipsISD::", Opc), Prof>;
  35
  36 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
  37   SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
  38
  39 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
  40 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
  41 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
  42 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
  43 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
  44 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
  45
  46 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
  47 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
  48
  49 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
  50 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
  51 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
  52 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
  53 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
  54
  55 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
  56 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
  57 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
  58 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
  59 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
  60 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
  61 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
  62 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
  63
  64 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
  65 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
  66 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
  67 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
  68 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
  69 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
  70 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
  71 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
  72 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
  73
  74 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
  75 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
  76 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
  77 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
  78 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
  79 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
  80 def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
  81 def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
  82 def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
  83 def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>;
  84 def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>;
  85
  86 // Flags.
  87 class Uses<list<Register> Regs> {
  88   list<Register> Uses = Regs;
  89 }
  90
  91 class Defs<list<Register> Regs> {
  92   list<Register> Defs = Regs;
  93 }
  94
  95 // Instruction encoding.
  96 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
  97 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
  98 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
  99 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
 100 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
 101 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
 102 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
 103 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
 104 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
 105 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
 106 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
 107 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
 108 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
 109 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
 110 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
 111 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
 112 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
 113 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
 114 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
 115 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
 116 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
 117 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
 118 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
 119 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
 120 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
 121 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
 122 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
 123 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
 124 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
 125 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
 126 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
 127 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
 128 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
 129 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
 130 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
 131 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
 132 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
 133 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
 134 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
 135 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
 136 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
 137 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
 138 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
 139 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
 140 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
 141 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
 142 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
 143 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
 144 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
 145 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
 146 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
 147 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
 148 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
 149 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
 150 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
 151 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
 152 class MFHI_ENC : MFHI_FMT<0b010000>;
 153 class MFLO_ENC : MFHI_FMT<0b010010>;
 154 class MTHI_ENC : MTHI_FMT<0b010001>;
 155 class MTLO_ENC : MTHI_FMT<0b010011>;
 156 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
 157 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
 158 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
 159 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
 160 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
 161 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
 162 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
 163 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
 164 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
 165 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
 166 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
 167 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
 168 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
 169 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
 170 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
 171 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
 172 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
 173 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
 174 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
 175 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
 176 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
 177 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
 178 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
 179 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
 180 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
 181 class REPL_QB_ENC : REPL_FMT<0b00010>;
 182 class REPL_PH_ENC : REPL_FMT<0b01010>;
 183 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
 184 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
 185 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
 186 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
 187 class LWX_ENC : LX_FMT<0b00000>;
 188 class LHX_ENC : LX_FMT<0b00100>;
 189 class LBUX_ENC : LX_FMT<0b00110>;
 190 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
 191 class INSV_ENC : INSV_FMT<0b001100>;
 192
 193 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
 194 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
 195 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
 196 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
 197 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
 198 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
 199 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
 200 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
 201 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
 202 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
 203 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
 204 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
 205 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
 206 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
 207 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
 208
 209 class RDDSP_ENC : RDDSP_FMT<0b10010>;
 210 class WRDSP_ENC : WRDSP_FMT<0b10011>;
 211 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
 212 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
 213 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
 214 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
 215 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
 216 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
 217 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
 218 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
 219 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
 220 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
 221 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
 222 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
 223 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
 224 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
 225 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
 226 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
 227 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
 228 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
 229 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
 230 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
 231 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
 232 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
 233 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
 234 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
 235 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
 236 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
 237 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
 238 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
 239 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
 240 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
 241 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
 242 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
 243 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
 244 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
 245 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
 246 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
 247 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
 248 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
 249 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
 250 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
 251 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
 252 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
 253 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
 254 class APPEND_ENC : APPEND_FMT<0b00000>;
 255 class BALIGN_ENC : APPEND_FMT<0b10000>;
 256 class PREPEND_ENC : APPEND_FMT<0b00001>;
 257
 258 // Instruction desc.
 259 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 260                         InstrItinClass itin, RegisterOperand ROD,
 261                         RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 262   dag OutOperandList = (outs ROD:$rd);
 263   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 264   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 265   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 266   InstrItinClass Itinerary = itin;
 267   string BaseOpcode = instr_asm;
 268 }
 269
 270 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 271                            InstrItinClass itin, RegisterOperand ROD,
 272                            RegisterOperand ROS = ROD> {
 273   dag OutOperandList = (outs ROD:$rd);
 274   dag InOperandList = (ins ROS:$rs);
 275   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 276   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
 277   InstrItinClass Itinerary = itin;
 278   string BaseOpcode = instr_asm;
 279 }
 280
 281 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 282                              InstrItinClass itin, RegisterOperand ROS,
 283                              RegisterOperand ROT = ROS> {
 284   dag OutOperandList = (outs);
 285   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 286   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
 287   list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
 288   InstrItinClass Itinerary = itin;
 289   string BaseOpcode = instr_asm;
 290 }
 291
 292 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 293                              InstrItinClass itin, RegisterOperand ROD,
 294                              RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 295   dag OutOperandList = (outs ROD:$rd);
 296   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 297   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 298   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 299   InstrItinClass Itinerary = itin;
 300   string BaseOpcode = instr_asm;
 301 }
 302
 303 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 304                                InstrItinClass itin, RegisterOperand ROT,
 305                                RegisterOperand ROS = ROT> {
 306   dag OutOperandList = (outs ROT:$rt);
 307   dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);
 308   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 309   list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
 310   InstrItinClass Itinerary = itin;
 311   string Constraints = "$src = $rt";
 312   string BaseOpcode = instr_asm;
 313 }
 314
 315 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 316                              InstrItinClass itin, RegisterOperand ROD,
 317                              RegisterOperand ROT = ROD> {
 318   dag OutOperandList = (outs ROD:$rd);
 319   dag InOperandList = (ins ROT:$rt);
 320   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 321   list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
 322   InstrItinClass Itinerary = itin;
 323   string BaseOpcode = instr_asm;
 324 }
 325
 326 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 327                      Operand ImmOp, ImmLeaf immPat, InstrItinClass itin,
 328                      RegisterOperand RO> {
 329   dag OutOperandList = (outs RO:$rd);
 330   dag InOperandList = (ins ImmOp:$imm);
 331   string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
 332   list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
 333   InstrItinClass Itinerary = itin;
 334   string BaseOpcode = instr_asm;
 335 }
 336
 337 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 338                            InstrItinClass itin, RegisterOperand RO> {
 339   dag OutOperandList = (outs RO:$rd);
 340   dag InOperandList =  (ins RO:$rt, GPR32Opnd:$rs_sa);
 341   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 342   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
 343   InstrItinClass Itinerary = itin;
 344   string BaseOpcode = instr_asm;
 345 }
 346
 347 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 348                            SDPatternOperator ImmPat, InstrItinClass itin,
 349                            RegisterOperand RO, Operand ImmOpnd> {
 350   dag OutOperandList = (outs RO:$rd);
 351   dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);
 352   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 353   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
 354   InstrItinClass Itinerary = itin;
 355   bit hasSideEffects = 1;
 356   string BaseOpcode = instr_asm;
 357 }
 358
 359 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 360                    InstrItinClass itin> {
 361   dag OutOperandList = (outs GPR32Opnd:$rd);
 362   dag InOperandList = (ins PtrRC:$base, PtrRC:$index);
 363   string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
 364   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))];
 365   InstrItinClass Itinerary = itin;
 366   bit mayLoad = 1;
 367   string BaseOpcode = instr_asm;
 368 }
 369
 370 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 371                          InstrItinClass itin, RegisterOperand ROD,
 372                          RegisterOperand ROS = ROD,  RegisterOperand ROT = ROD> {
 373   dag OutOperandList = (outs ROD:$rd);
 374   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 375   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 376   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 377   InstrItinClass Itinerary = itin;
 378   string BaseOpcode = instr_asm;
 379 }
 380
 381 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 382                        Operand ImmOp, SDPatternOperator Imm, InstrItinClass itin> {
 383   dag OutOperandList = (outs GPR32Opnd:$rt);
 384   dag InOperandList = (ins GPR32Opnd:$rs, ImmOp:$sa, GPR32Opnd:$src);
 385   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 386   list<dag> Pattern =  [(set GPR32Opnd:$rt,
 387                         (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, Imm:$sa))];
 388   InstrItinClass Itinerary = itin;
 389   string Constraints = "$src = $rt";
 390   string BaseOpcode = instr_asm;
 391 }
 392
 393 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 394                               InstrItinClass itin> {
 395   dag OutOperandList = (outs GPR32Opnd:$rt);
 396   dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);
 397   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 398   InstrItinClass Itinerary = itin;
 399   string BaseOpcode = instr_asm;
 400 }
 401
 402 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 403                               InstrItinClass itin> {
 404   dag OutOperandList = (outs GPR32Opnd:$rt);
 405   dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm5:$shift_rs);
 406   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 407   InstrItinClass Itinerary = itin;
 408   string BaseOpcode = instr_asm;
 409 }
 410
 411 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 412   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 413   dag InOperandList = (ins simm6:$shift, ACC64DSPOpnd:$acin);
 414   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
 415   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 416                         (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))];
 417   string Constraints = "$acin = $ac";
 418   string BaseOpcode = instr_asm;
 419 }
 420
 421 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 422   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 423   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 424   string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
 425   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 426                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 427   string Constraints = "$acin = $ac";
 428   string BaseOpcode = instr_asm;
 429 }
 430
 431 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 432   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 433   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 434   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 435   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 436                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 437   string Constraints = "$acin = $ac";
 438   string BaseOpcode = instr_asm;
 439 }
 440
 441 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 442                       InstrItinClass itin> {
 443   dag OutOperandList = (outs GPR32Opnd:$rd);
 444   dag InOperandList = (ins uimm10:$mask);
 445   string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
 446   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode immZExt10:$mask))];
 447   InstrItinClass Itinerary = itin;
 448   string BaseOpcode = instr_asm;
 449   bit isMoveReg = 1;
 450 }
 451
 452 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 453                       InstrItinClass itin> {
 454   dag OutOperandList = (outs);
 455   dag InOperandList = (ins GPR32Opnd:$rs, uimm10:$mask);
 456   string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
 457   list<dag> Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)];
 458   InstrItinClass Itinerary = itin;
 459   string BaseOpcode = instr_asm;
 460   bit isMoveReg = 1;
 461 }
 462
 463 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 464   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 465   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 466   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 467   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 468                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 469   string Constraints = "$acin = $ac";
 470   string BaseOpcode = instr_asm;
 471 }
 472
 473 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 474                      InstrItinClass itin> {
 475   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 476   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt);
 477   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 478   list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))];
 479   InstrItinClass Itinerary = itin;
 480   bit isCommutable = 1;
 481   string BaseOpcode = instr_asm;
 482 }
 483
 484 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 485                      InstrItinClass itin> {
 486   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 487   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 488   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 489   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 490                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 491   InstrItinClass Itinerary = itin;
 492   string Constraints = "$acin = $ac";
 493   string BaseOpcode = instr_asm;
 494 }
 495
 496 class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
 497                      InstrItinClass itin> {
 498   dag OutOperandList = (outs GPR32Opnd:$rd);
 499   dag InOperandList = (ins RO:$ac);
 500   string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
 501   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
 502   InstrItinClass Itinerary = itin;
 503   string BaseOpcode = instr_asm;
 504   bit isMoveReg = 1;
 505 }
 506
 507 class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> {
 508   dag OutOperandList = (outs RO:$ac);
 509   dag InOperandList = (ins GPR32Opnd:$rs);
 510   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 511   InstrItinClass Itinerary = itin;
 512   string BaseOpcode = instr_asm;
 513   bit isMoveReg = 1;
 514 }
 515
 516 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
 517   MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {
 518   bit hasNoSchedulingInfo = 1;
 519   bit usesCustomInserter = 1;
 520 }
 521
 522 class BPOSGE32_DESC_BASE<string instr_asm, DAGOperand opnd,
 523                          InstrItinClass itin> {
 524   dag OutOperandList = (outs);
 525   dag InOperandList = (ins opnd:$offset);
 526   string AsmString = !strconcat(instr_asm, "\t$offset");
 527   InstrItinClass Itinerary = itin;
 528   bit isBranch = 1;
 529   bit isTerminator = 1;
 530   bit hasDelaySlot = 1;
 531   string BaseOpcode = instr_asm;
 532 }
 533
 534 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 535                      InstrItinClass itin> {
 536   dag OutOperandList = (outs GPR32Opnd:$rt);
 537   dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs);
 538   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 539   list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];
 540   InstrItinClass Itinerary = itin;
 541   string Constraints = "$src = $rt";
 542   string BaseOpcode = instr_asm;
 543 }
 544
 545 //===----------------------------------------------------------------------===//
 546 // MIPS DSP Rev 1
 547 //===----------------------------------------------------------------------===//
 548
 549 // Addition/subtraction
 550 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
 551                                        DSPROpnd, DSPROpnd>, IsCommutable,
 552                      Defs<[DSPOutFlag20]>;
 553
 554 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
 555                                          NoItinerary, DSPROpnd, DSPROpnd>,
 556                        IsCommutable, Defs<[DSPOutFlag20]>;
 557
 558 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
 559                                        DSPROpnd, DSPROpnd>,
 560                      Defs<[DSPOutFlag20]>;
 561
 562 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
 563                                          NoItinerary, DSPROpnd, DSPROpnd>,
 564                        Defs<[DSPOutFlag20]>;
 565
 566 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
 567                                        DSPROpnd, DSPROpnd>, IsCommutable,
 568                      Defs<[DSPOutFlag20]>;
 569
 570 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
 571                                          NoItinerary, DSPROpnd, DSPROpnd>,
 572                        IsCommutable, Defs<[DSPOutFlag20]>;
 573
 574 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
 575                                        DSPROpnd, DSPROpnd>,
 576                      Defs<[DSPOutFlag20]>;
 577
 578 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
 579                                          NoItinerary, DSPROpnd, DSPROpnd>,
 580                        Defs<[DSPOutFlag20]>;
 581
 582 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
 583                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 584                       IsCommutable, Defs<[DSPOutFlag20]>;
 585
 586 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
 587                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 588                       Defs<[DSPOutFlag20]>;
 589
 590 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
 591                                      GPR32Opnd, GPR32Opnd>, IsCommutable,
 592                    Defs<[DSPCarry]>;
 593
 594 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
 595                                      GPR32Opnd, GPR32Opnd>,
 596                    IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>;
 597
 598 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
 599                                       GPR32Opnd, GPR32Opnd>;
 600
 601 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
 602                                              NoItinerary, GPR32Opnd, DSPROpnd>;
 603
 604 // Absolute value
 605 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
 606                                               NoItinerary, DSPROpnd>,
 607                        Defs<[DSPOutFlag20]>;
 608
 609 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
 610                                              NoItinerary, GPR32Opnd>,
 611                       Defs<[DSPOutFlag20]>;
 612
 613 // Precision reduce/expand
 614 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
 615                                                  int_mips_precrq_qb_ph,
 616                                                  NoItinerary, DSPROpnd, DSPROpnd>;
 617
 618 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
 619                                                 int_mips_precrq_ph_w,
 620                                                 NoItinerary, DSPROpnd, GPR32Opnd>;
 621
 622 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
 623                                                    int_mips_precrq_rs_ph_w,
 624                                                    NoItinerary, DSPROpnd,
 625                                                    GPR32Opnd>,
 626                             Defs<[DSPOutFlag22]>;
 627
 628 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
 629                                                     int_mips_precrqu_s_qb_ph,
 630                                                     NoItinerary, DSPROpnd,
 631                                                     DSPROpnd>,
 632                              Defs<[DSPOutFlag22]>;
 633
 634 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
 635                                                  int_mips_preceq_w_phl,
 636                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 637
 638 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
 639                                                  int_mips_preceq_w_phr,
 640                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 641
 642 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
 643                                                    int_mips_precequ_ph_qbl,
 644                                                    NoItinerary, DSPROpnd>;
 645
 646 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
 647                                                    int_mips_precequ_ph_qbr,
 648                                                    NoItinerary, DSPROpnd>;
 649
 650 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
 651                                                     int_mips_precequ_ph_qbla,
 652                                                     NoItinerary, DSPROpnd>;
 653
 654 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
 655                                                     int_mips_precequ_ph_qbra,
 656                                                     NoItinerary, DSPROpnd>;
 657
 658 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
 659                                                   int_mips_preceu_ph_qbl,
 660                                                   NoItinerary, DSPROpnd>;
 661
 662 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
 663                                                   int_mips_preceu_ph_qbr,
 664                                                   NoItinerary, DSPROpnd>;
 665
 666 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
 667                                                    int_mips_preceu_ph_qbla,
 668                                                    NoItinerary, DSPROpnd>;
 669
 670 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
 671                                                    int_mips_preceu_ph_qbra,
 672                                                    NoItinerary, DSPROpnd>;
 673
 674 // Shift
 675 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
 676                                           NoItinerary, DSPROpnd, uimm3>,
 677                      Defs<[DSPOutFlag22]>;
 678
 679 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
 680                                            NoItinerary, DSPROpnd>,
 681                       Defs<[DSPOutFlag22]>;
 682
 683 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
 684                                           NoItinerary, DSPROpnd, uimm3>;
 685
 686 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
 687                                            NoItinerary, DSPROpnd>;
 688
 689 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
 690                                           NoItinerary, DSPROpnd, uimm4>,
 691                      Defs<[DSPOutFlag22]>;
 692
 693 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
 694                                            NoItinerary, DSPROpnd>,
 695                       Defs<[DSPOutFlag22]>;
 696
 697 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
 698                                             immZExt4, NoItinerary, DSPROpnd,
 699                                             uimm4>,
 700                        Defs<[DSPOutFlag22]>;
 701
 702 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
 703                                              NoItinerary, DSPROpnd>,
 704                         Defs<[DSPOutFlag22]>;
 705
 706 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
 707                                           NoItinerary, DSPROpnd, uimm4>;
 708
 709 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
 710                                            NoItinerary, DSPROpnd>;
 711
 712 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
 713                                             immZExt4, NoItinerary, DSPROpnd,
 714                                             uimm4>;
 715
 716 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
 717                                              NoItinerary, DSPROpnd>;
 718
 719 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
 720                                            immZExt5, NoItinerary, GPR32Opnd,
 721                                            uimm5>,
 722                       Defs<[DSPOutFlag22]>;
 723
 724 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
 725                                             NoItinerary, GPR32Opnd>,
 726                        Defs<[DSPOutFlag22]>;
 727
 728 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
 729                                            immZExt5, NoItinerary, GPR32Opnd,
 730                                            uimm5>;
 731
 732 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
 733                                             NoItinerary, GPR32Opnd>;
 734
 735 // Multiplication
 736 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
 737                                               int_mips_muleu_s_ph_qbl,
 738                                               NoItinerary, DSPROpnd, DSPROpnd>,
 739                             Defs<[DSPOutFlag21]>;
 740
 741 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
 742                                               int_mips_muleu_s_ph_qbr,
 743                                               NoItinerary, DSPROpnd, DSPROpnd>,
 744                             Defs<[DSPOutFlag21]>;
 745
 746 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
 747                                              int_mips_muleq_s_w_phl,
 748                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 749                            IsCommutable, Defs<[DSPOutFlag21]>;
 750
 751 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
 752                                              int_mips_muleq_s_w_phr,
 753                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 754                            IsCommutable, Defs<[DSPOutFlag21]>;
 755
 756 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
 757                                           NoItinerary, DSPROpnd, DSPROpnd>,
 758                         IsCommutable, Defs<[DSPOutFlag21]>;
 759
 760 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
 761                                               MipsMULSAQ_S_W_PH>,
 762                            Defs<[DSPOutFlag16_19]>;
 763
 764 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>,
 765                          Defs<[DSPOutFlag16_19]>;
 766
 767 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>,
 768                          Defs<[DSPOutFlag16_19]>;
 769
 770 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>,
 771                           Defs<[DSPOutFlag16_19]>;
 772
 773 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>,
 774                           Defs<[DSPOutFlag16_19]>;
 775
 776 // Move from/to hi/lo.
 777 class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, NoItinerary>;
 778 class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, NoItinerary>;
 779 class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>;
 780 class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>;
 781
 782 // Dot product with accumulate/subtract
 783 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
 784
 785 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
 786
 787 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
 788
 789 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
 790
 791 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>,
 792                          Defs<[DSPOutFlag16_19]>;
 793
 794 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>,
 795                          Defs<[DSPOutFlag16_19]>;
 796
 797 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>,
 798                          Defs<[DSPOutFlag16_19]>;
 799
 800 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>,
 801                          Defs<[DSPOutFlag16_19]>;
 802
 803 class MULT_DSP_DESC  : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
 804 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
 805 class MADD_DSP_DESC  : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
 806 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
 807 class MSUB_DSP_DESC  : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
 808 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
 809
 810 // Comparison
 811 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
 812                                                int_mips_cmpu_eq_qb, NoItinerary,
 813                                                DSPROpnd>,
 814                         IsCommutable, Defs<[DSPCCond]>;
 815
 816 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
 817                                                int_mips_cmpu_lt_qb, NoItinerary,
 818                                                DSPROpnd>, Defs<[DSPCCond]>;
 819
 820 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
 821                                                int_mips_cmpu_le_qb, NoItinerary,
 822                                                DSPROpnd>, Defs<[DSPCCond]>;
 823
 824 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
 825                                                 int_mips_cmpgu_eq_qb,
 826                                                 NoItinerary, GPR32Opnd, DSPROpnd>,
 827                          IsCommutable;
 828
 829 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
 830                                                 int_mips_cmpgu_lt_qb,
 831                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 832
 833 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
 834                                                 int_mips_cmpgu_le_qb,
 835                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 836
 837 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
 838                                               NoItinerary, DSPROpnd>,
 839                        IsCommutable, Defs<[DSPCCond]>;
 840
 841 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
 842                                               NoItinerary, DSPROpnd>,
 843                        Defs<[DSPCCond]>;
 844
 845 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
 846                                               NoItinerary, DSPROpnd>,
 847                        Defs<[DSPCCond]>;
 848
 849 // Misc
 850 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 851                                            NoItinerary, GPR32Opnd>;
 852
 853 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
 854                                               NoItinerary, DSPROpnd, DSPROpnd>;
 855
 856 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, uimm8,
 857                                     immZExt8, NoItinerary, DSPROpnd>;
 858
 859 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, simm10,
 860                                     immSExt10, NoItinerary, DSPROpnd>;
 861
 862 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
 863                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 864
 865 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
 866                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 867
 868 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
 869                                             NoItinerary, DSPROpnd, DSPROpnd>,
 870                      Uses<[DSPCCond]>;
 871
 872 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
 873                                             NoItinerary, DSPROpnd, DSPROpnd>,
 874                      Uses<[DSPCCond]>;
 875
 876 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
 877
 878 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
 879
 880 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
 881
 882 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget, NoItinerary>;
 883
 884 // Extr
 885 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
 886                   Uses<[DSPPos]>, Defs<[DSPEFI]>;
 887
 888 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
 889                    Uses<[DSPPos]>, Defs<[DSPEFI]>;
 890
 891 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,
 892                     Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 893
 894 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
 895                                              NoItinerary>,
 896                      Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 897
 898 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
 899                     Defs<[DSPOutFlag23]>;
 900
 901 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
 902                                              NoItinerary>, Defs<[DSPOutFlag23]>;
 903
 904 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
 905                                               NoItinerary>,
 906                       Defs<[DSPOutFlag23]>;
 907
 908 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
 909                                                NoItinerary>,
 910                        Defs<[DSPOutFlag23]>;
 911
 912 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
 913                                                NoItinerary>,
 914                        Defs<[DSPOutFlag23]>;
 915
 916 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
 917                                                 NoItinerary>,
 918                         Defs<[DSPOutFlag23]>;
 919
 920 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
 921                                               NoItinerary>,
 922                       Defs<[DSPOutFlag23]>;
 923
 924 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
 925                                                NoItinerary>,
 926                        Defs<[DSPOutFlag23]>;
 927
 928 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
 929
 930 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
 931
 932 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>;
 933
 934 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
 935
 936 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
 937
 938 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,
 939                   Uses<[DSPPos, DSPSCount]>;
 940
 941 //===----------------------------------------------------------------------===//
 942 // MIPS DSP Rev 2
 943 // Addition/subtraction
 944 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
 945                                        DSPROpnd, DSPROpnd>, IsCommutable,
 946                      Defs<[DSPOutFlag20]>;
 947
 948 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
 949                                          NoItinerary, DSPROpnd, DSPROpnd>,
 950                        IsCommutable, Defs<[DSPOutFlag20]>;
 951
 952 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
 953                                        DSPROpnd, DSPROpnd>,
 954                      Defs<[DSPOutFlag20]>;
 955
 956 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
 957                                          NoItinerary, DSPROpnd, DSPROpnd>,
 958                        Defs<[DSPOutFlag20]>;
 959
 960 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
 961                                          NoItinerary, DSPROpnd>, IsCommutable;
 962
 963 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
 964                                            NoItinerary, DSPROpnd>, IsCommutable;
 965
 966 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
 967                                          NoItinerary, DSPROpnd>;
 968
 969 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
 970                                            NoItinerary, DSPROpnd>;
 971
 972 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
 973                                          NoItinerary, DSPROpnd>, IsCommutable;
 974
 975 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
 976                                            NoItinerary, DSPROpnd>, IsCommutable;
 977
 978 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
 979                                          NoItinerary, DSPROpnd>;
 980
 981 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
 982                                            NoItinerary, DSPROpnd>;
 983
 984 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
 985                                         NoItinerary, GPR32Opnd>, IsCommutable;
 986
 987 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
 988                                           NoItinerary, GPR32Opnd>, IsCommutable;
 989
 990 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
 991                                         NoItinerary, GPR32Opnd>;
 992
 993 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
 994                                           NoItinerary, GPR32Opnd>;
 995
 996 // Comparison
 997 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
 998                                                  int_mips_cmpgdu_eq_qb,
 999                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
1000                           IsCommutable, Defs<[DSPCCond]>;
1001
1002 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
1003                                                  int_mips_cmpgdu_lt_qb,
1004                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
1005                           Defs<[DSPCCond]>;
1006
1007 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
1008                                                  int_mips_cmpgdu_le_qb,
1009                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
1010                           Defs<[DSPCCond]>;
1011
1012 // Absolute
1013 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
1014                                               NoItinerary, DSPROpnd>,
1015                        Defs<[DSPOutFlag20]>;
1016
1017 // Multiplication
1018 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
1019                                        DSPROpnd>, IsCommutable,
1020                     Defs<[DSPOutFlag21]>;
1021
1022 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
1023                                          NoItinerary, DSPROpnd>, IsCommutable,
1024                       Defs<[DSPOutFlag21]>;
1025
1026 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
1027                                          NoItinerary, GPR32Opnd>, IsCommutable,
1028                       Defs<[DSPOutFlag21]>;
1029
1030 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
1031                                           NoItinerary, GPR32Opnd>, IsCommutable,
1032                        Defs<[DSPOutFlag21]>;
1033
1034 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
1035                                          NoItinerary, DSPROpnd, DSPROpnd>,
1036                        IsCommutable, Defs<[DSPOutFlag21]>;
1037
1038 // Dot product with accumulate/subtract
1039 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
1040
1041 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
1042
1043 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>,
1044                           Defs<[DSPOutFlag16_19]>;
1045
1046 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
1047                                               MipsDPAQX_SA_W_PH>,
1048                            Defs<[DSPOutFlag16_19]>;
1049
1050 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
1051
1052 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
1053
1054 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>,
1055                           Defs<[DSPOutFlag16_19]>;
1056
1057 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
1058                                               MipsDPSQX_SA_W_PH>,
1059                            Defs<[DSPOutFlag16_19]>;
1060
1061 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
1062
1063 // Precision reduce/expand
1064 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
1065                                                 int_mips_precr_qb_ph,
1066                                                 NoItinerary, DSPROpnd, DSPROpnd>;
1067
1068 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1069                                                      int_mips_precr_sra_ph_w,
1070                                                      NoItinerary, DSPROpnd,
1071                                                      GPR32Opnd>;
1072
1073 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1074                                                       int_mips_precr_sra_r_ph_w,
1075                                                        NoItinerary, DSPROpnd,
1076                                                        GPR32Opnd>;
1077
1078 // Shift
1079 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
1080                                           NoItinerary, DSPROpnd, uimm3>;
1081
1082 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1083                                            NoItinerary, DSPROpnd>;
1084
1085 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1086                                             immZExt3, NoItinerary, DSPROpnd,
1087                                             uimm3>;
1088
1089 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1090                                              NoItinerary, DSPROpnd>;
1091
1092 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
1093                                           NoItinerary, DSPROpnd, uimm4>;
1094
1095 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1096                                            NoItinerary, DSPROpnd>;
1097
1098 // Misc
1099 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, uimm5, immZExt5,
1100                                      NoItinerary>;
1101
1102 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, uimm2, immZExt2,
1103                                      NoItinerary>;
1104
1105 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, uimm5,
1106                                       immZExt5, NoItinerary>;
1107
1108 // Pseudos.
1109 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
1110                                                 NoItinerary>, Uses<[DSPPos]>;
1111
1112 // Instruction defs.
1113 // MIPS DSP Rev 1
1114 def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
1115 def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1116 def SUBU_QB : DspMMRel, SUBU_QB_ENC, SUBU_QB_DESC;
1117 def SUBU_S_QB : DspMMRel, SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1118 def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
1119 def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1120 def SUBQ_PH : DspMMRel, SUBQ_PH_ENC, SUBQ_PH_DESC;
1121 def SUBQ_S_PH : DspMMRel, SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1122 def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1123 def SUBQ_S_W : DspMMRel, SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1124 def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
1125 def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
1126 def MODSUB : DspMMRel, MODSUB_ENC, MODSUB_DESC;
1127 def RADDU_W_QB : DspMMRel, RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1128 def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1129 def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1130 def PRECRQ_QB_PH : DspMMRel, PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1131 def PRECRQ_PH_W : DspMMRel, PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1132 def PRECRQ_RS_PH_W : DspMMRel, PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1133 def PRECRQU_S_QB_PH : DspMMRel, PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1134 def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1135 def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1136 def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1137 def PRECEQU_PH_QBR : DspMMRel, PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1138 def PRECEQU_PH_QBLA : DspMMRel, PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1139 def PRECEQU_PH_QBRA : DspMMRel, PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1140 def PRECEU_PH_QBL : DspMMRel, PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1141 def PRECEU_PH_QBR : DspMMRel, PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1142 def PRECEU_PH_QBLA : DspMMRel, PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1143 def PRECEU_PH_QBRA : DspMMRel, PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1144 def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC;
1145 def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC;
1146 def SHRL_QB : DspMMRel, SHRL_QB_ENC, SHRL_QB_DESC;
1147 def SHRLV_QB : DspMMRel, SHRLV_QB_ENC, SHRLV_QB_DESC;
1148 def SHLL_PH : DspMMRel, SHLL_PH_ENC, SHLL_PH_DESC;
1149 def SHLLV_PH : DspMMRel, SHLLV_PH_ENC, SHLLV_PH_DESC;
1150 def SHLL_S_PH : DspMMRel, SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1151 def SHLLV_S_PH : DspMMRel, SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1152 def SHRA_PH : DspMMRel, SHRA_PH_ENC, SHRA_PH_DESC;
1153 def SHRAV_PH : DspMMRel, SHRAV_PH_ENC, SHRAV_PH_DESC;
1154 def SHRA_R_PH : DspMMRel, SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1155 def SHRAV_R_PH : DspMMRel, SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1156 def SHLL_S_W : DspMMRel, SHLL_S_W_ENC, SHLL_S_W_DESC;
1157 def SHLLV_S_W : DspMMRel, SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1158 def SHRA_R_W : DspMMRel, SHRA_R_W_ENC, SHRA_R_W_DESC;
1159 def SHRAV_R_W : DspMMRel, SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1160 def MULEU_S_PH_QBL : DspMMRel, MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1161 def MULEU_S_PH_QBR : DspMMRel, MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1162 def MULEQ_S_W_PHL : DspMMRel, MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1163 def MULEQ_S_W_PHR : DspMMRel, MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1164 def MULQ_RS_PH : DspMMRel, MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1165 def MULSAQ_S_W_PH : DspMMRel, MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1166 def MAQ_S_W_PHL : DspMMRel, MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1167 def MAQ_S_W_PHR : DspMMRel, MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1168 def MAQ_SA_W_PHL : DspMMRel, MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1169 def MAQ_SA_W_PHR : DspMMRel, MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1170 def MFHI_DSP : DspMMRel, MFHI_ENC, MFHI_DESC;
1171 def MFLO_DSP : DspMMRel, MFLO_ENC, MFLO_DESC;
1172 def MTHI_DSP : DspMMRel, MTHI_ENC, MTHI_DESC;
1173 def MTLO_DSP : DspMMRel, MTLO_ENC, MTLO_DESC;
1174 def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1175 def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1176 def DPSU_H_QBL : DspMMRel, DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1177 def DPSU_H_QBR : DspMMRel, DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1178 def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1179 def DPSQ_S_W_PH : DspMMRel, DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1180 def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1181 def DPSQ_SA_L_W : DspMMRel, DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1182 def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC;
1183 def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC;
1184 def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;
1185 def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC;
1186 def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC;
1187 def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1188 def CMPU_EQ_QB : DspMMRel, CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1189 def CMPU_LT_QB : DspMMRel, CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1190 def CMPU_LE_QB : DspMMRel, CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1191 def CMPGU_EQ_QB : DspMMRel, CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1192 def CMPGU_LT_QB : DspMMRel, CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1193 def CMPGU_LE_QB : DspMMRel, CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1194 def CMP_EQ_PH : DspMMRel, CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1195 def CMP_LT_PH : DspMMRel, CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1196 def CMP_LE_PH : DspMMRel, CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1197 def BITREV : DspMMRel, BITREV_ENC, BITREV_DESC;
1198 def PACKRL_PH : DspMMRel, PACKRL_PH_ENC, PACKRL_PH_DESC;
1199 def REPL_QB : DspMMRel, REPL_QB_ENC, REPL_QB_DESC;
1200 def REPL_PH : DspMMRel, REPL_PH_ENC, REPL_PH_DESC;
1201 def REPLV_QB : DspMMRel, REPLV_QB_ENC, REPLV_QB_DESC;
1202 def REPLV_PH : DspMMRel, REPLV_PH_ENC, REPLV_PH_DESC;
1203 def PICK_QB : DspMMRel, PICK_QB_ENC, PICK_QB_DESC;
1204 def PICK_PH : DspMMRel, PICK_PH_ENC, PICK_PH_DESC;
1205 def LWX : DspMMRel, LWX_ENC, LWX_DESC;
1206 def LHX : DspMMRel, LHX_ENC, LHX_DESC;
1207 def LBUX : DspMMRel, LBUX_ENC, LBUX_DESC;
1208 let AdditionalPredicates = [NotInMicroMips] in {
1209   def BPOSGE32 : DspMMRel, BPOSGE32_ENC, BPOSGE32_DESC;
1210 }
1211 def INSV : DspMMRel, INSV_ENC, INSV_DESC;
1212 def EXTP : DspMMRel, EXTP_ENC, EXTP_DESC;
1213 def EXTPV : DspMMRel, EXTPV_ENC, EXTPV_DESC;
1214 def EXTPDP : DspMMRel, EXTPDP_ENC, EXTPDP_DESC;
1215 def EXTPDPV : DspMMRel, EXTPDPV_ENC, EXTPDPV_DESC;
1216 def EXTR_W : DspMMRel, EXTR_W_ENC, EXTR_W_DESC;
1217 def EXTRV_W : DspMMRel, EXTRV_W_ENC, EXTRV_W_DESC;
1218 def EXTR_R_W : DspMMRel, EXTR_R_W_ENC, EXTR_R_W_DESC;
1219 def EXTRV_R_W : DspMMRel, EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1220 def EXTR_RS_W : DspMMRel, EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1221 def EXTRV_RS_W : DspMMRel, EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1222 def EXTR_S_H : DspMMRel, EXTR_S_H_ENC, EXTR_S_H_DESC;
1223 def EXTRV_S_H : DspMMRel, EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1224 def SHILO : DspMMRel, SHILO_ENC, SHILO_DESC;
1225 def SHILOV : DspMMRel, SHILOV_ENC, SHILOV_DESC;
1226 def MTHLIP : DspMMRel, MTHLIP_ENC, MTHLIP_DESC;
1227 def RDDSP : DspMMRel, RDDSP_ENC, RDDSP_DESC;
1228 let AdditionalPredicates = [NotInMicroMips] in {
1229   def WRDSP : WRDSP_ENC, WRDSP_DESC;
1230 }
1231
1232 // MIPS DSP Rev 2
1233 def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC, ISA_DSPR2;
1234 def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC, ISA_DSPR2;
1235 def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC, ISA_DSPR2;
1236 def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC, ISA_DSPR2;
1237 def CMPGDU_EQ_QB : DspMMRel, CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC, ISA_DSPR2;
1238 def CMPGDU_LT_QB : DspMMRel, CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC, ISA_DSPR2;
1239 def CMPGDU_LE_QB : DspMMRel, CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC, ISA_DSPR2;
1240 def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC, ISA_DSPR2;
1241 def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC, ISA_DSPR2;
1242 def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC, ISA_DSPR2;
1243 def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC, ISA_DSPR2;
1244 def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC, ISA_DSPR2;
1245 def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC, ISA_DSPR2;
1246 def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
1247 def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC, ISA_DSPR2;
1248 def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC, ISA_DSPR2;
1249 def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC, ISA_DSPR2;
1250 def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC, ISA_DSPR2;
1251 def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC, ISA_DSPR2;
1252 def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC, ISA_DSPR2;
1253 def MUL_PH : DspMMRel, MUL_PH_ENC, MUL_PH_DESC, ISA_DSPR2;
1254 def MUL_S_PH : DspMMRel, MUL_S_PH_ENC, MUL_S_PH_DESC, ISA_DSPR2;
1255 def MULQ_S_W : DspMMRel, MULQ_S_W_ENC, MULQ_S_W_DESC, ISA_DSPR2;
1256 def MULQ_RS_W : DspMMRel, MULQ_RS_W_ENC, MULQ_RS_W_DESC, ISA_DSPR2;
1257 def MULQ_S_PH : DspMMRel, MULQ_S_PH_ENC, MULQ_S_PH_DESC, ISA_DSPR2;
1258 def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC, ISA_DSPR2;
1259 def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC, ISA_DSPR2;
1260 def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC, ISA_DSPR2;
1261 def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC, ISA_DSPR2;
1262 def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC, ISA_DSPR2;
1263 def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC, ISA_DSPR2;
1264 def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC, ISA_DSPR2;
1265 def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC, ISA_DSPR2;
1266 def MULSA_W_PH : DspMMRel, MULSA_W_PH_ENC, MULSA_W_PH_DESC, ISA_DSPR2;
1267 def PRECR_QB_PH : DspMMRel, PRECR_QB_PH_ENC, PRECR_QB_PH_DESC, ISA_DSPR2;
1268 def PRECR_SRA_PH_W : DspMMRel, PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC, ISA_DSPR2;
1269 def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC, ISA_DSPR2;
1270 def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC, ISA_DSPR2;
1271 def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC, ISA_DSPR2;
1272 def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC, ISA_DSPR2;
1273 def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC, ISA_DSPR2;
1274 def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC, ISA_DSPR2;
1275 def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC, ISA_DSPR2;
1276 def APPEND : DspMMRel, APPEND_ENC, APPEND_DESC, ISA_DSPR2;
1277 def BALIGN : DspMMRel, BALIGN_ENC, BALIGN_DESC, ISA_DSPR2;
1278 def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC, ISA_DSPR2;
1279
1280 // Pseudos.
1281 let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
1282   // Pseudo instructions for loading and storing accumulator registers.
1283   def LOAD_ACC64DSP  : Load<"", ACC64DSPOpnd>;
1284   def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;
1285
1286   // Pseudos for loading and storing ccond field of DSP control register.
1287   def LOAD_CCOND_DSP  : Load<"load_ccond_dsp", DSPCC>;
1288   def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
1289 }
1290
1291 let DecoderNamespace = "MipsDSP", Arch = "dsp",
1292     ASEPredicate = [HasDSP] in {
1293   def LWDSP : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel, LW_FM<0x23>;
1294   def SWDSP : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel, LW_FM<0x2b>;
1295 }
1296
1297 // Pseudo CMP and PICK instructions.
1298 class PseudoCMP<Instruction RealInst> :
1299   PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
1300   PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>, NeverHasSideEffects;
1301
1302 class PseudoPICK<Instruction RealInst> :
1303   PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,
1304   PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>,
1305   NeverHasSideEffects;
1306
1307 def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;
1308 def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>;
1309 def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;
1310 def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;
1311 def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;
1312 def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;
1313
1314 def PseudoPICK_PH : PseudoPICK<PICK_PH>;
1315 def PseudoPICK_QB : PseudoPICK<PICK_QB>;
1316
1317 let AdditionalPredicates = [HasDSP] in {
1318   def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>;
1319 }
1320
1321 // Patterns.
1322 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1323   Pat<pattern, result>, Requires<[pred]>;
1324
1325 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1326                     RegisterClass SrcRC> :
1327    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1328           (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1329
1330 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1331 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1332 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1333 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1334 def : BitconvertPat<f32, v2i16, FGR32, DSPR>;
1335 def : BitconvertPat<f32, v4i8, FGR32, DSPR>;
1336 def : BitconvertPat<v2i16, f32, DSPR, FGR32>;
1337 def : BitconvertPat<v4i8, f32, DSPR, FGR32>;
1338
1339 def : DSPPat<(v2i16 (load addr:$a)),
1340              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1341 def : DSPPat<(v4i8 (load addr:$a)),
1342              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1343 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1344              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1345 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1346              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1347
1348 // Binary operations.
1349 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1350                 Predicate Pred = HasDSP> :
1351   DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
1352
1353 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1354 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1355 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1356 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1357 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1358 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1359 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1360 def : DSPBinPat<ADDU_QB, v4i8, add>;
1361 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1362 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1363 def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
1364 def : DSPBinPat<ADDSC, i32, addc>;
1365 def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
1366 def : DSPBinPat<ADDWC, i32, adde>;
1367
1368 // Shift immediate patterns.
1369 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1370                   SDPatternOperator Imm, Predicate Pred = HasDSP> :
1371   DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
1372
1373 def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
1374 def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
1375 def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
1376 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
1377 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
1378 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
1379 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
1380 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
1381 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
1382 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
1383 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
1384 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
1385
1386 // SETCC/SELECT_CC patterns.
1387 class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1388                   CondCode CC> :
1389   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1390          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1391                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1392                       (ValTy ZERO)))>;
1393
1394 class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1395                      CondCode CC> :
1396   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1397          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1398                       (ValTy ZERO),
1399                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
1400
1401 class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1402                      CondCode CC> :
1403   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1404          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>;
1405
1406 class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1407                         CondCode CC> :
1408   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1409          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>;
1410
1411 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1412 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1413 def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1414 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1415 def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1416 def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1417 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1418 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1419 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1420 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1421 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1422 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1423
1424 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1425 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1426 def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1427 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1428 def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1429 def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1430 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1431 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1432 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1433 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1434 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1435 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1436
1437 // Extr patterns.
1438 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1439   DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
1440          (Instr ACC64DSP:$ac, GPR32:$rs)>;
1441
1442 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1443   DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)),
1444          (Instr ACC64DSP:$ac, immZExt5:$shift)>;
1445
1446 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1447 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1448 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1449 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1450 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1451 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1452 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1453 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1454 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1455 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1456 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1457 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
1458
1459 // Indexed load patterns.
1460 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
1461   DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
1462          (Instr i32:$base, i32:$index)>;
1463
1464 let AddedComplexity = 20 in {
1465   def : IndexedLoadPat<zextloadi8, LBUX>;
1466   def : IndexedLoadPat<sextloadi16, LHX>;
1467   def : IndexedLoadPat<load, LWX>;
1468 }
1469
1470 // Instruction alias.
1471 let AdditionalPredicates = [NotInMicroMips] in {
1472   def : DSPInstAlias<"wrdsp $rt", (WRDSP GPR32Opnd:$rt, 0x1F), 1>;
1473 }