1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the Mips FPU instruction set.
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Floating Point Instructions
15 // ------------------------
17 // - 32 64-bit registers (default mode)
18 // - 16 even 32-bit registers (32-bit compatible mode) for
19 // single and double access.
21 // - 16 even 32-bit registers - single and double (aliased)
22 // - 32 32-bit registers (within single-only mode)
23 //===----------------------------------------------------------------------===//
25 // Floating Point Compare and Branch
26 def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>,
28 SDTCisVT<2, OtherVT>]>;
29 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
31 def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>,
33 def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
34 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
37 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
41 def SDT_MipsMTC1_D64 : SDTypeProfile<1, 1, [SDTCisVT<0, f64>,
44 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
45 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
46 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
47 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
48 [SDNPHasChain, SDNPOptInGlue]>;
49 def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>;
50 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
51 def : GINodeEquiv<G_MERGE_VALUES, MipsBuildPairF64>;
52 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
53 SDT_MipsExtractElementF64>;
55 def MipsMTC1_D64 : SDNode<"MipsISD::MTC1_D64", SDT_MipsMTC1_D64>;
57 // Operand for printing out a condition code.
58 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
59 def condcode : Operand<i32>;
61 //===----------------------------------------------------------------------===//
62 // Feature predicates.
63 //===----------------------------------------------------------------------===//
65 def IsFP64bit : Predicate<"Subtarget->isFP64bit()">,
66 AssemblerPredicate<(all_of FeatureFP64Bit)>;
67 def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">,
68 AssemblerPredicate<(all_of (not FeatureFP64Bit))>;
69 def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">,
70 AssemblerPredicate<(all_of FeatureSingleFloat)>;
71 def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">,
72 AssemblerPredicate<(all_of (not FeatureSingleFloat))>;
73 def IsNotSoftFloat : Predicate<"!Subtarget->useSoftFloat()">,
74 AssemblerPredicate<(all_of (not FeatureSoftFloat))>;
75 def HasMips3D : Predicate<"Subtarget->has3D()">,
76 AssemblerPredicate<(all_of FeatureMips3D)>;
78 //===----------------------------------------------------------------------===//
79 // Mips FGR size adjectives.
80 // They are mutually exclusive.
81 //===----------------------------------------------------------------------===//
83 class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; }
84 class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; }
85 class HARDFLOAT { list<Predicate> HardFloatPredicate = [IsNotSoftFloat]; }
87 //===----------------------------------------------------------------------===//
89 // FP immediate patterns.
90 def fpimm0 : PatLeaf<(fpimm), [{
91 return N->isExactlyValue(+0.0);
94 def fpimm0neg : PatLeaf<(fpimm), [{
95 return N->isExactlyValue(-0.0);
98 //===----------------------------------------------------------------------===//
99 // Instruction Class Templates
101 // A set of multiclasses is used to address the register usage.
103 // S32 - single precision in 16 32bit even fp registers
104 // single precision in 32 32bit fp registers in SingleOnly mode
105 // S64 - single precision in 32 64bit fp registers (In64BitMode)
106 // D32 - double precision in 16 32bit even fp registers
107 // D64 - double precision in 32 64bit fp registers (In64BitMode)
109 // Only S32 and D32 are supported right now.
110 //===----------------------------------------------------------------------===//
111 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
112 SDPatternOperator OpNode= null_frag> :
113 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
114 !strconcat(opstr, "\t$fd, $fs, $ft"),
115 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
117 let isCommutable = IsComm;
120 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
121 SDPatternOperator OpNode = null_frag> {
122 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
123 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
124 string DecoderNamespace = "MipsFP64";
128 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
129 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
130 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
131 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
135 class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
136 InstrItinClass Itin, bit IsComm,
137 SDPatternOperator OpNode = null_frag> :
138 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft),
139 !strconcat(opstr, "\t$fd, $fs, $ft"),
140 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
142 let isCommutable = IsComm;
145 multiclass ABSS_M<string opstr, InstrItinClass Itin,
146 SDPatternOperator OpNode= null_frag> {
147 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
149 def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
151 string DecoderNamespace = "MipsFP64";
155 multiclass ROUND_M<string opstr, InstrItinClass Itin> {
156 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, FGR_32;
157 def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 {
158 let DecoderNamespace = "MipsFP64";
162 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
163 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
164 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
165 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT {
169 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
170 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
171 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
172 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT {
176 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
177 InstrItinClass Itin> :
178 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt),
179 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr>, HARDFLOAT {
180 // $fs_in is part of a white lie to work around a widespread bug in the FPU
181 // implementation. See expandBuildPairF64 for details.
182 let Constraints = "$fs = $fs_in";
185 class LW_FT<string opstr, RegisterOperand RC, DAGOperand MO,
186 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
187 InstSE<(outs RC:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
188 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr>,
190 let DecoderMethod = "DecodeFMem";
194 class SW_FT<string opstr, RegisterOperand RC, DAGOperand MO,
195 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
196 InstSE<(outs), (ins RC:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
197 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr>, HARDFLOAT {
198 let DecoderMethod = "DecodeFMem";
202 class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
203 SDPatternOperator OpNode = null_frag> :
204 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
205 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
206 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin,
207 FrmFR, opstr>, HARDFLOAT;
209 class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
210 SDPatternOperator OpNode = null_frag> :
211 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
212 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
213 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
214 Itin, FrmFR, opstr>, HARDFLOAT;
216 class LWXC1_FT<string opstr, RegisterOperand DRC,
217 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
218 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
219 !strconcat(opstr, "\t$fd, ${index}(${base})"),
220 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
221 FrmFI, opstr>, HARDFLOAT {
222 let AddedComplexity = 20;
225 class SWXC1_FT<string opstr, RegisterOperand DRC,
226 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
227 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
228 !strconcat(opstr, "\t$fs, ${index}(${base})"),
229 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
230 FrmFI, opstr>, HARDFLOAT {
231 let AddedComplexity = 20;
234 class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
235 SDPatternOperator Op = null_frag> :
236 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
237 !strconcat(opstr, "\t$fcc, $offset"),
238 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
239 FrmFI, opstr>, HARDFLOAT {
241 let isTerminator = 1;
242 let hasDelaySlot = 1;
244 let hasFCCRegOperand = 1;
247 class BC1XL_FT<string opstr, DAGOperand opnd, InstrItinClass Itin> :
248 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
249 !strconcat(opstr, "\t$fcc, $offset"), [], Itin,
250 FrmFI, opstr>, HARDFLOAT {
252 let isTerminator = 1;
253 let hasDelaySlot = 1;
255 let hasFCCRegOperand = 1;
258 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
259 SDPatternOperator OpNode = null_frag> :
260 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
261 !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
262 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR,
263 !strconcat("c.$cond.", typestr)>, HARDFLOAT {
265 let isCodeGenOnly = 1;
266 let hasFCCRegOperand = 1;
270 // Note: MIPS-IV introduced $fcc1-$fcc7 and renamed FCSR31[23] $fcc0. Rather
271 // duplicating the instruction definition for MIPS1 - MIPS3, we expand
272 // c.cond.ft if necessary, and reject it after constructing the
273 // instruction if the ISA doesn't support it.
274 class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC,
275 InstrItinClass itin> :
276 InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft),
277 !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), [], itin,
280 let hasFCCRegOperand = 1;
284 multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt,
285 InstrItinClass itin> {
286 def C_F_#NAME : MMRel, C_COND_FT<"f", TypeStr, RC, itin>,
288 let BaseOpcode = "c.f."#NAME;
289 let isCommutable = 1;
291 def C_UN_#NAME : MMRel, C_COND_FT<"un", TypeStr, RC, itin>,
293 let BaseOpcode = "c.un."#NAME;
294 let isCommutable = 1;
296 def C_EQ_#NAME : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>,
298 let BaseOpcode = "c.eq."#NAME;
299 let isCommutable = 1;
301 def C_UEQ_#NAME : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>,
303 let BaseOpcode = "c.ueq."#NAME;
304 let isCommutable = 1;
306 def C_OLT_#NAME : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>,
308 let BaseOpcode = "c.olt."#NAME;
310 def C_ULT_#NAME : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>,
312 let BaseOpcode = "c.ult."#NAME;
314 def C_OLE_#NAME : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>,
316 let BaseOpcode = "c.ole."#NAME;
318 def C_ULE_#NAME : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>,
320 let BaseOpcode = "c.ule."#NAME;
322 def C_SF_#NAME : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>,
324 let BaseOpcode = "c.sf."#NAME;
325 let isCommutable = 1;
327 def C_NGLE_#NAME : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>,
329 let BaseOpcode = "c.ngle."#NAME;
331 def C_SEQ_#NAME : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>,
333 let BaseOpcode = "c.seq."#NAME;
334 let isCommutable = 1;
336 def C_NGL_#NAME : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>,
338 let BaseOpcode = "c.ngl."#NAME;
340 def C_LT_#NAME : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>,
342 let BaseOpcode = "c.lt."#NAME;
344 def C_NGE_#NAME : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>,
346 let BaseOpcode = "c.nge."#NAME;
348 def C_LE_#NAME : MMRel, C_COND_FT<"le", TypeStr, RC, itin>,
350 let BaseOpcode = "c.le."#NAME;
352 def C_NGT_#NAME : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>,
354 let BaseOpcode = "c.ngt."#NAME;
358 let AdditionalPredicates = [NotInMicroMips] in {
359 defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6;
360 defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
362 let DecoderNamespace = "MipsFP64" in
363 defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
366 //===----------------------------------------------------------------------===//
367 // Floating Point Instructions
368 //===----------------------------------------------------------------------===//
369 let AdditionalPredicates = [NotInMicroMips] in {
370 def ROUND_W_S : MMRel, StdMMR6Rel,
371 ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
372 ABSS_FM<0xc, 16>, ISA_MIPS2;
373 defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
374 def TRUNC_W_S : MMRel, StdMMR6Rel,
375 ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
376 ABSS_FM<0xd, 16>, ISA_MIPS2;
377 def CEIL_W_S : MMRel, StdMMR6Rel,
378 ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
379 ABSS_FM<0xe, 16>, ISA_MIPS2;
380 def FLOOR_W_S : MMRel, StdMMR6Rel,
381 ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
382 ABSS_FM<0xf, 16>, ISA_MIPS2;
383 def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
384 ABSS_FM<0x24, 16>, ISA_MIPS1;
386 defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
387 defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
388 defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
389 defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>, ISA_MIPS1;
392 let AdditionalPredicates = [NotInMicroMips] in {
393 def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>,
394 ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2;
395 def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>,
396 ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2, FGR_32 {
397 let BaseOpcode = "RECIP_D32";
399 let DecoderNamespace = "MipsFP64" in
400 def RECIP_D64 : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd,
401 II_RECIP_D>, ABSS_FM<0b010101, 0x11>,
402 INSN_MIPS4_32R2, FGR_64;
403 def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>,
404 ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2;
405 def RSQRT_D32 : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, II_RSQRT_D>,
406 ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2, FGR_32 {
407 let BaseOpcode = "RSQRT_D32";
409 let DecoderNamespace = "MipsFP64" in
410 def RSQRT_D64 : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd,
411 II_RSQRT_D>, ABSS_FM<0b010110, 0x11>,
412 INSN_MIPS4_32R2, FGR_64;
414 let DecoderNamespace = "MipsFP64" in {
415 let AdditionalPredicates = [NotInMicroMips] in {
416 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
417 ABSS_FM<0x8, 16>, ISA_MIPS2, FGR_64;
418 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
419 ABSS_FM<0x8, 17>, INSN_MIPS3_32, FGR_64;
420 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
421 ABSS_FM<0x9, 16>, ISA_MIPS2, FGR_64;
422 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>,
423 ABSS_FM<0x9, 17>, INSN_MIPS3_32, FGR_64;
424 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>,
425 ABSS_FM<0xa, 16>, ISA_MIPS2, FGR_64;
426 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>,
427 ABSS_FM<0xa, 17>, INSN_MIPS3_32, FGR_64;
428 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>,
429 ABSS_FM<0xb, 16>, ISA_MIPS2, FGR_64;
430 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>,
431 ABSS_FM<0xb, 17>, INSN_MIPS3_32, FGR_64;
435 let AdditionalPredicates = [NotInMicroMips] in{
436 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
437 ABSS_FM<0x20, 20>, ISA_MIPS1;
438 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
439 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;
440 def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
441 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2;
444 let AdditionalPredicates = [NotInMicroMips] in {
445 def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
446 ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_32;
447 def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
448 ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_32;
449 def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
450 ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_32;
453 let DecoderNamespace = "MipsFP64" in {
454 let AdditionalPredicates = [NotInMicroMips] in {
455 def PLL_PS64 : ADDS_FT<"pll.ps", FGR64Opnd, II_CVT, 0>,
457 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
458 def PLU_PS64 : ADDS_FT<"plu.ps", FGR64Opnd, II_CVT, 0>,
460 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
461 def PUL_PS64 : ADDS_FT<"pul.ps", FGR64Opnd, II_CVT, 0>,
463 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
464 def PUU_PS64 : ADDS_FT<"puu.ps", FGR64Opnd, II_CVT, 0>,
466 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
468 def CVT_S_PU64 : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>,
470 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
471 def CVT_S_PL64 : ABSS_FT<"cvt.s.pl", FGR32Opnd, FGR64Opnd, II_CVT>,
473 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
475 def CVT_PS_S64 : CVT_PS_S_FT<"cvt.ps.s", FGR64Opnd, FGR32Opnd, II_CVT, 0>,
477 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
481 let DecoderNamespace = "MipsFP64" in {
482 let AdditionalPredicates = [HasMips3D] in {
483 def ADDR_PS64 : ADDS_FT<"addr.ps", FGR64Opnd, II_ADDR_PS, 0>,
484 ADDS_FM<0x18, 22>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
485 def MULR_PS64 : ADDS_FT<"mulr.ps", FGR64Opnd, II_MULR_PS, 0>,
486 ADDS_FM<0x1a, 22>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
487 def CVT_PS_PW64 : ABSS_FT<"cvt.ps.pw", FGR64Opnd, FGR64Opnd, II_CVT>,
489 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
490 def CVT_PW_PS64 : ABSS_FT<"cvt.pw.ps", FGR64Opnd, FGR64Opnd, II_CVT>,
492 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
496 let DecoderNamespace = "MipsFP64" in {
497 let AdditionalPredicates = [NotInMicroMips] in {
498 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
499 ABSS_FM<0x20, 21>, INSN_MIPS3_32R2, FGR_64;
500 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
501 ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_64;
502 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
503 ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_64;
504 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
505 ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_64;
506 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
507 ABSS_FM<0x21, 21>, INSN_MIPS3_32R2, FGR_64;
511 let isPseudo = 1, isCodeGenOnly = 1 in {
512 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;
513 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;
514 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
515 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;
516 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
519 let AdditionalPredicates = [NotInMicroMips, UseAbs] in {
520 def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
521 ABSS_FM<0x5, 16>, ISA_MIPS1;
522 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>, ISA_MIPS1;
525 def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
526 ABSS_FM<0x7, 16>, ISA_MIPS1;
527 let AdditionalPredicates = [NotInMicroMips] in {
528 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>, ISA_MIPS1;
531 let AdditionalPredicates = [NotInMicroMips] in {
532 def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
533 II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2;
534 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
537 // The odd-numbered registers are only referenced when doing loads,
538 // stores, and moves between floating-point and integer registers.
539 // When defining instructions, we reference all 32-bit registers,
540 // regardless of register aliasing.
542 /// Move Control Registers From/To CPU Registers
543 let AdditionalPredicates = [NotInMicroMips] in {
544 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>,
546 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>,
549 def MFC1 : MMRel, StdMMR6Rel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
550 bitconvert>, MFC1_FM<0>, ISA_MIPS1;
551 def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>,
553 let DecoderNamespace = "MipsFP64";
555 def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
556 bitconvert>, MFC1_FM<4>, ISA_MIPS1;
557 def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>,
559 let DecoderNamespace = "MipsFP64";
562 def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
563 MFC1_FM<3>, ISA_MIPS32R2, FGR_32;
564 def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
565 MFC1_FM<3>, ISA_MIPS32R2, FGR_64 {
566 let DecoderNamespace = "MipsFP64";
569 def MTHC1_D32 : MMRel, StdMMR6Rel,
570 MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
571 MFC1_FM<7>, ISA_MIPS32R2, FGR_32;
572 def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
573 MFC1_FM<7>, ISA_MIPS32R2, FGR_64 {
574 let DecoderNamespace = "MipsFP64";
577 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
578 bitconvert>, MFC1_FM<5>, ISA_MIPS3;
579 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
580 bitconvert>, MFC1_FM<1>, ISA_MIPS3;
581 let isMoveReg = 1 in {
582 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
583 ABSS_FM<0x6, 16>, ISA_MIPS1;
584 defm FMOV : ABSS_M<"mov.d", II_MOV_D>, ABSS_FM<0x6, 17>, ISA_MIPS1;
588 /// Floating Point Memory Instructions
589 let AdditionalPredicates = [NotInMicroMips] in {
590 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>,
591 LW_FM<0x31>, ISA_MIPS1;
592 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>,
593 LW_FM<0x39>, ISA_MIPS1;
596 let DecoderNamespace = "MipsFP64", AdditionalPredicates = [NotInMicroMips] in {
597 def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, II_LDC1, load>,
598 LW_FM<0x35>, ISA_MIPS2, FGR_64 {
599 let BaseOpcode = "LDC164";
601 def SDC164 : StdMMR6Rel, SW_FT<"sdc1", FGR64Opnd, mem_simm16, II_SDC1, store>,
602 LW_FM<0x3d>, ISA_MIPS2, FGR_64;
605 let AdditionalPredicates = [NotInMicroMips] in {
606 def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, mem_simm16, II_LDC1,
607 load>, LW_FM<0x35>, ISA_MIPS2, FGR_32 {
608 let BaseOpcode = "LDC132";
610 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_simm16, II_SDC1, store>,
611 LW_FM<0x3d>, ISA_MIPS2, FGR_32;
614 // Indexed loads and stores.
615 // Base register + offset register addressing mode (indicated by "x" in the
616 // instruction mnemonic) is disallowed under NaCl.
617 let AdditionalPredicates = [IsNotNaCl] in {
618 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>,
619 INSN_MIPS4_32R2_NOT_32R6_64R6;
620 def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>,
621 INSN_MIPS4_32R2_NOT_32R6_64R6;
624 let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in {
625 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
626 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
627 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
628 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
631 let DecoderNamespace="MipsFP64" in {
632 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
633 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
634 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
635 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
638 // Load/store doubleword indexed unaligned.
639 // FIXME: This instruction should not be defined for FGR_32.
640 let AdditionalPredicates = [IsNotNaCl, NotInMicroMips] in {
641 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
642 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
643 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
644 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
647 let AdditionalPredicates = [IsNotNaCl, NotInMicroMips],
648 DecoderNamespace="MipsFP64" in {
649 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
650 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
651 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
652 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
655 /// Floating-point Arithmetic
656 let AdditionalPredicates = [NotInMicroMips] in {
657 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
658 ADDS_FM<0x00, 16>, ISA_MIPS1;
659 defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>,
661 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
662 ADDS_FM<0x03, 16>, ISA_MIPS1;
663 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>,
665 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
666 ADDS_FM<0x02, 16>, ISA_MIPS1;
667 defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>,
669 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
670 ADDS_FM<0x01, 16>, ISA_MIPS1;
671 defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>,
675 let AdditionalPredicates = [NotInMicroMips, HasMadd4] in {
676 def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
677 MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
678 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
679 MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
681 def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
682 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
683 def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
684 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
686 let DecoderNamespace = "MipsFP64" in {
687 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
688 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
689 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
690 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
694 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in {
695 def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
696 MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
697 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
698 MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
700 def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
701 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
702 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
703 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
705 let DecoderNamespace = "MipsFP64" in {
706 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
707 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
708 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
709 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
712 //===----------------------------------------------------------------------===//
713 // Floating Point Branch Codes
714 //===----------------------------------------------------------------------===//
715 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
716 // They must be kept in synch.
717 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
718 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
720 let AdditionalPredicates = [NotInMicroMips] in {
721 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
722 BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
723 def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>,
724 BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
725 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
726 BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
727 def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>,
728 BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
730 /// Floating Point Compare
731 def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>,
732 ISA_MIPS1_NOT_32R6_64R6 {
734 // FIXME: This is a required to work around the fact that these instructions
735 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
736 // fcc register set is used directly.
739 def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
740 ISA_MIPS1_NOT_32R6_64R6, FGR_32 {
741 // FIXME: This is a required to work around the fact that these instructions
742 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
743 // fcc register set is used directly.
747 let DecoderNamespace = "MipsFP64" in
748 def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
749 ISA_MIPS1_NOT_32R6_64R6, FGR_64 {
750 // FIXME: This is a required to work around the fact that thiese instructions
751 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
752 // fcc register set is used directly.
756 //===----------------------------------------------------------------------===//
757 // Floating Point Pseudo-Instructions
758 //===----------------------------------------------------------------------===//
760 // This pseudo instr gets expanded into 2 mtc1 instrs after register
762 class BuildPairF64Base<RegisterOperand RO> :
763 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi),
764 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))],
767 def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
768 def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
770 // This pseudo instr gets expanded into 2 mfc1 instrs after register
772 // if n is 0, lower part of src is extracted.
773 // if n is 1, higher part of src is extracted.
774 // This node has associated scheduling information as the pre RA scheduler
775 // asserts otherwise.
776 class ExtractElementF64Base<RegisterOperand RO> :
777 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),
778 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))],
781 def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
782 def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
784 def PseudoTRUNC_W_S : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
785 (ins FGR32Opnd:$fs, GPR32Opnd:$rs),
786 "trunc.w.s\t$fd, $fs, $rs">;
788 def PseudoTRUNC_W_D32 : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
789 (ins AFGR64Opnd:$fs, GPR32Opnd:$rs),
790 "trunc.w.d\t$fd, $fs, $rs">,
793 def PseudoTRUNC_W_D : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
794 (ins FGR64Opnd:$fs, GPR32Opnd:$rs),
795 "trunc.w.d\t$fd, $fs, $rs">,
798 def LoadImmSingleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
800 "li.s\t$rd, $fpimm">;
802 def LoadImmSingleFGR : MipsAsmPseudoInst<(outs StrictlyFGR32Opnd:$rd),
804 "li.s\t$rd, $fpimm">,
807 def LoadImmDoubleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
809 "li.d\t$rd, $fpimm">;
811 def LoadImmDoubleFGR_32 : MipsAsmPseudoInst<(outs StrictlyAFGR64Opnd:$rd),
813 "li.d\t$rd, $fpimm">,
816 def LoadImmDoubleFGR : MipsAsmPseudoInst<(outs StrictlyFGR64Opnd:$rd),
818 "li.d\t$rd, $fpimm">,
821 def SDC1_M1 : MipsAsmPseudoInst<(outs AFGR64Opnd:$fd),
822 (ins mem_simm16:$addr),
824 FGR_32, ISA_MIPS1, HARDFLOAT;
826 //===----------------------------------------------------------------------===//
828 //===----------------------------------------------------------------------===//
830 <"s.s $fd, $addr", (SWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>,
831 ISA_MIPS2, HARDFLOAT;
833 <"s.d $fd, $addr", (SDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>,
834 FGR_32, ISA_MIPS2, HARDFLOAT;
836 <"s.d $fd, $addr", (SDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>,
837 FGR_64, ISA_MIPS2, HARDFLOAT;
839 <"s.d $fd, $addr", (SDC1_M1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>,
840 FGR_32, ISA_MIPS1, HARDFLOAT;
843 <"l.s $fd, $addr", (LWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>,
844 ISA_MIPS2, HARDFLOAT;
846 <"l.d $fd, $addr", (LDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>,
847 FGR_32, ISA_MIPS2, HARDFLOAT;
849 <"l.d $fd, $addr", (LDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>,
850 FGR_64, ISA_MIPS2, HARDFLOAT;
852 multiclass C_COND_ALIASES<string TypeStr, RegisterOperand RC> {
853 def : MipsInstAlias<!strconcat("c.f.", TypeStr, " $fs, $ft"),
854 (!cast<Instruction>("C_F_"#NAME) FCC0,
856 def : MipsInstAlias<!strconcat("c.un.", TypeStr, " $fs, $ft"),
857 (!cast<Instruction>("C_UN_"#NAME) FCC0,
859 def : MipsInstAlias<!strconcat("c.eq.", TypeStr, " $fs, $ft"),
860 (!cast<Instruction>("C_EQ_"#NAME) FCC0,
862 def : MipsInstAlias<!strconcat("c.ueq.", TypeStr, " $fs, $ft"),
863 (!cast<Instruction>("C_UEQ_"#NAME) FCC0,
865 def : MipsInstAlias<!strconcat("c.olt.", TypeStr, " $fs, $ft"),
866 (!cast<Instruction>("C_OLT_"#NAME) FCC0,
868 def : MipsInstAlias<!strconcat("c.ult.", TypeStr, " $fs, $ft"),
869 (!cast<Instruction>("C_ULT_"#NAME) FCC0,
871 def : MipsInstAlias<!strconcat("c.ole.", TypeStr, " $fs, $ft"),
872 (!cast<Instruction>("C_OLE_"#NAME) FCC0,
874 def : MipsInstAlias<!strconcat("c.ule.", TypeStr, " $fs, $ft"),
875 (!cast<Instruction>("C_ULE_"#NAME) FCC0,
877 def : MipsInstAlias<!strconcat("c.sf.", TypeStr, " $fs, $ft"),
878 (!cast<Instruction>("C_SF_"#NAME) FCC0,
880 def : MipsInstAlias<!strconcat("c.ngle.", TypeStr, " $fs, $ft"),
881 (!cast<Instruction>("C_NGLE_"#NAME) FCC0,
883 def : MipsInstAlias<!strconcat("c.seq.", TypeStr, " $fs, $ft"),
884 (!cast<Instruction>("C_SEQ_"#NAME) FCC0,
886 def : MipsInstAlias<!strconcat("c.ngl.", TypeStr, " $fs, $ft"),
887 (!cast<Instruction>("C_NGL_"#NAME) FCC0,
889 def : MipsInstAlias<!strconcat("c.lt.", TypeStr, " $fs, $ft"),
890 (!cast<Instruction>("C_LT_"#NAME) FCC0,
892 def : MipsInstAlias<!strconcat("c.nge.", TypeStr, " $fs, $ft"),
893 (!cast<Instruction>("C_NGE_"#NAME) FCC0,
895 def : MipsInstAlias<!strconcat("c.le.", TypeStr, " $fs, $ft"),
896 (!cast<Instruction>("C_LE_"#NAME) FCC0,
898 def : MipsInstAlias<!strconcat("c.ngt.", TypeStr, " $fs, $ft"),
899 (!cast<Instruction>("C_NGT_"#NAME) FCC0,
903 multiclass BC1_ALIASES<Instruction BCTrue, string BCTrueString,
904 Instruction BCFalse, string BCFalseString> {
905 def : MipsInstAlias<!strconcat(BCTrueString, " $offset"),
906 (BCTrue FCC0, brtarget:$offset), 1>;
908 def : MipsInstAlias<!strconcat(BCFalseString, " $offset"),
909 (BCFalse FCC0, brtarget:$offset), 1>;
912 let AdditionalPredicates = [NotInMicroMips] in {
913 defm S : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT,
914 ISA_MIPS1_NOT_32R6_64R6;
915 defm D32 : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT,
916 ISA_MIPS1_NOT_32R6_64R6, FGR_32;
917 defm D64 : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT,
918 ISA_MIPS1_NOT_32R6_64R6, FGR_64;
920 defm : BC1_ALIASES<BC1T, "bc1t", BC1F, "bc1f">, ISA_MIPS1_NOT_32R6_64R6,
922 defm : BC1_ALIASES<BC1TL, "bc1tl", BC1FL, "bc1fl">, ISA_MIPS2_NOT_32R6_64R6,
925 //===----------------------------------------------------------------------===//
926 // Floating Point Patterns
927 //===----------------------------------------------------------------------===//
928 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>, ISA_MIPS1;
929 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>, ISA_MIPS1;
931 def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
932 (PseudoCVT_S_W GPR32Opnd:$src)>;
933 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
934 (TRUNC_W_S FGR32Opnd:$src)>, ISA_MIPS1;
936 def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src),
937 (MTC1_D64 GPR32Opnd:$src)>, ISA_MIPS1, FGR_64;
939 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
940 (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32;
941 let AdditionalPredicates = [NotInMicroMips] in {
942 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
943 (TRUNC_W_D32 AFGR64Opnd:$src)>, ISA_MIPS2, FGR_32;
944 def : MipsPat<(f32 (fpround AFGR64Opnd:$src)),
945 (CVT_S_D32 AFGR64Opnd:$src)>, ISA_MIPS1, FGR_32;
946 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)),
947 (CVT_D32_S FGR32Opnd:$src)>, ISA_MIPS1, FGR_32;
950 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, ISA_MIPS3, GPR_64, FGR_64;
951 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, ISA_MIPS3, GPR_64,
954 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
955 (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64;
956 def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)),
957 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64;
958 def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)),
959 (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64;
961 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
962 (TRUNC_W_D64 FGR64Opnd:$src)>, ISA_MIPS2, FGR_64;
963 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
964 (TRUNC_L_S FGR32Opnd:$src)>, ISA_MIPS2, FGR_64;
965 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
966 (TRUNC_L_D64 FGR64Opnd:$src)>, ISA_MIPS2, FGR_64;
968 let AdditionalPredicates = [NotInMicroMips] in {
969 def : MipsPat<(f32 (fpround FGR64Opnd:$src)),
970 (CVT_S_D64 FGR64Opnd:$src)>, ISA_MIPS1, FGR_64;
971 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)),
972 (CVT_D64_S FGR32Opnd:$src)>, ISA_MIPS1, FGR_64;
975 // To generate NMADD and NMSUB instructions when fneg node is present
976 multiclass NMADD_NMSUB<Instruction Nmadd, Instruction Nmsub, RegisterOperand RC> {
977 def : MipsPat<(fneg (fadd (fmul RC:$fs, RC:$ft), RC:$fr)),
978 (Nmadd RC:$fr, RC:$fs, RC:$ft)>;
979 def : MipsPat<(fneg (fsub (fmul RC:$fs, RC:$ft), RC:$fr)),
980 (Nmsub RC:$fr, RC:$fs, RC:$ft)>;
983 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in {
984 defm : NMADD_NMSUB<NMADD_S, NMSUB_S, FGR32Opnd>,
985 INSN_MIPS4_32R2_NOT_32R6_64R6;
986 defm : NMADD_NMSUB<NMADD_D32, NMSUB_D32, AFGR64Opnd>,
987 FGR_32, INSN_MIPS4_32R2_NOT_32R6_64R6;
988 defm : NMADD_NMSUB<NMADD_D64, NMSUB_D64, FGR64Opnd>,
989 FGR_64, INSN_MIPS4_32R2_NOT_32R6_64R6;
992 // Patterns for loads/stores with a reg+imm operand.
993 let AdditionalPredicates = [NotInMicroMips] in {
994 let AddedComplexity = 40 in {
995 def : LoadRegImmPat<LWC1, f32, load>, ISA_MIPS1;
996 def : StoreRegImmPat<SWC1, f32>, ISA_MIPS1;
998 def : LoadRegImmPat<LDC164, f64, load>, ISA_MIPS1, FGR_64;
999 def : StoreRegImmPat<SDC164, f64>, ISA_MIPS1, FGR_64;
1001 def : LoadRegImmPat<LDC1, f64, load>, ISA_MIPS1, FGR_32;
1002 def : StoreRegImmPat<SDC1, f64>, ISA_MIPS1, FGR_32;