1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
10 // Describe MIPS instructions format
12 // CPU INSTRUCTION FORMATS
14 // opcode - operation code.
16 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
17 // rd - dst reg, only used on 3 regs instr.
18 // shamt - only used on shift instructions, contains the shift amount.
19 // funct - combined with opcode field give us an operation code.
21 //===----------------------------------------------------------------------===//
23 // Format specifies the encoding used by the instruction. This is part of the
24 // ad-hoc solution used to emit machine instruction encodings by our machine
26 class Format<bits<4> val> {
30 def Pseudo : Format<0>;
34 def FrmFR : Format<4>;
35 def FrmFI : Format<5>;
36 def FrmOther : Format<6>; // Instruction w/ a custom format
40 def Std2MicroMips : InstrMapping {
41 let FilterClass = "MMRel";
42 // Instructions with the same BaseOpcode and isNVStore values form a row.
43 let RowFields = ["BaseOpcode"];
44 // Instructions with the same predicate sense form a column.
45 let ColFields = ["Arch"];
46 // The key column is the unpredicated instructions.
48 // Value columns are PredSense=true and PredSense=false
49 let ValueCols = [["se"], ["micromips"]];
54 def Std2MicroMipsR6 : InstrMapping {
55 let FilterClass = "StdMMR6Rel";
56 // Instructions with the same BaseOpcode and isNVStore values form a row.
57 let RowFields = ["BaseOpcode"];
58 // Instructions with the same predicate sense form a column.
59 let ColFields = ["Arch"];
60 // The key column is the unpredicated instructions.
62 // Value columns are PredSense=true and PredSense=false
63 let ValueCols = [["se"], ["micromipsr6"]];
70 // Generic Mips Format
71 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
72 InstrItinClass itin, Format f>: Instruction, PredicateControl
77 let Namespace = "Mips";
83 // Top 6 bits are the 'opcode' field
84 let Inst{31-26} = Opcode;
86 let OutOperandList = outs;
87 let InOperandList = ins;
89 let AsmString = asmstr;
90 let Pattern = pattern;
94 // Attributes specific to Mips instructions...
96 bits<4> FormBits = Form.Value;
97 bit isCTI = 0; // Any form of Control Transfer Instruction.
98 // Required for MIPSR6
99 bit hasForbiddenSlot = 0; // Instruction has a forbidden slot.
100 bit IsPCRelativeLoad = 0; // Load instruction with implicit source register
101 // ($pc) and with explicit offset and destination
103 bit hasFCCRegOperand = 0; // Instruction uses $fcc<X> register and is
104 // present in MIPS-I to MIPS-III.
106 // TSFlags layout should be kept in sync with MCTargetDesc/MipsBaseInfo.h.
107 let TSFlags{3-0} = FormBits;
108 let TSFlags{4} = isCTI;
109 let TSFlags{5} = hasForbiddenSlot;
110 let TSFlags{6} = IsPCRelativeLoad;
111 let TSFlags{7} = hasFCCRegOperand;
113 let DecoderNamespace = "Mips";
115 field bits<32> SoftFail = 0;
118 // Mips32/64 Instruction Format
119 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
120 InstrItinClass itin, Format f, string opstr = ""> :
121 MipsInst<outs, ins, asmstr, pattern, itin, f> {
122 let EncodingPredicates = [NotInMips16Mode];
123 string BaseOpcode = opstr;
127 // Mips Pseudo Instructions Format
128 class MipsPseudo<dag outs, dag ins, list<dag> pattern,
129 InstrItinClass itin = IIPseudo> :
130 MipsInst<outs, ins, "", pattern, itin, Pseudo> {
131 let isCodeGenOnly = 1;
135 // Mips32/64 Pseudo Instruction Format
136 class PseudoSE<dag outs, dag ins, list<dag> pattern,
137 InstrItinClass itin = IIPseudo> :
138 MipsPseudo<outs, ins, pattern, itin> {
139 let EncodingPredicates = [NotInMips16Mode];
142 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
143 // These are aliases that require C++ handling to convert to the target
144 // instruction, while InstAliases can be handled directly by tblgen.
145 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
146 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
148 let hasNoSchedulingInfo = 1;
151 //===----------------------------------------------------------------------===//
152 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
153 //===----------------------------------------------------------------------===//
155 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
156 list<dag> pattern, InstrItinClass itin>:
157 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
168 let Inst{25-21} = rs;
169 let Inst{20-16} = rt;
170 let Inst{15-11} = rd;
171 let Inst{10-6} = shamt;
172 let Inst{5-0} = funct;
175 //===----------------------------------------------------------------------===//
176 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
177 //===----------------------------------------------------------------------===//
179 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
180 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
188 let Inst{25-21} = rs;
189 let Inst{20-16} = rt;
190 let Inst{15-0} = imm16;
193 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
194 list<dag> pattern, InstrItinClass itin>:
195 InstSE<outs, ins, asmstr, pattern, itin, FrmI>
203 let Inst{25-21} = rs;
204 let Inst{20-16} = rt;
205 let Inst{15-0} = imm16;
208 //===----------------------------------------------------------------------===//
209 // Format J instruction class in Mips : <|opcode|address|>
210 //===----------------------------------------------------------------------===//
212 class FJ<bits<6> op> : StdArch
218 let Inst{31-26} = op;
219 let Inst{25-0} = target;
222 //===----------------------------------------------------------------------===//
223 // MFC instruction class in Mips : <|op|mf|rt|rd|gst|0000|sel|>
224 //===----------------------------------------------------------------------===//
225 class MFC3OP_FM<bits<6> op, bits<5> mfmt, bits<3> guest> : StdArch {
232 let Inst{31-26} = op;
233 let Inst{25-21} = mfmt;
234 let Inst{20-16} = rt;
235 let Inst{15-11} = rd;
236 let Inst{10-8} = guest;
241 class MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch {
247 let Inst{31-26} = op;
248 let Inst{25-21} = mfmt;
249 let Inst{20-16} = rt;
250 let Inst{15-0} = imm16;
253 class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
260 let Inst{31-26} = op;
261 let Inst{25-21} = rs;
262 let Inst{20-16} = rt;
263 let Inst{15-11} = rd;
265 let Inst{5-0} = funct;
268 class ADDI_FM<bits<6> op> : StdArch {
275 let Inst{31-26} = op;
276 let Inst{25-21} = rs;
277 let Inst{20-16} = rt;
278 let Inst{15-0} = imm16;
281 class SRA_FM<bits<6> funct, bit rotate> : StdArch {
290 let Inst{21} = rotate;
291 let Inst{20-16} = rt;
292 let Inst{15-11} = rd;
293 let Inst{10-6} = shamt;
294 let Inst{5-0} = funct;
297 class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
305 let Inst{25-21} = rs;
306 let Inst{20-16} = rt;
307 let Inst{15-11} = rd;
309 let Inst{6} = rotate;
310 let Inst{5-0} = funct;
313 class BEQ_FM<bits<6> op> : StdArch {
320 let Inst{31-26} = op;
321 let Inst{25-21} = rs;
322 let Inst{20-16} = rt;
323 let Inst{15-0} = offset;
326 class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
332 let Inst{31-26} = op;
333 let Inst{25-21} = rs;
334 let Inst{20-16} = funct;
335 let Inst{15-0} = offset;
338 class BBIT_FM<bits<6> op> : StdArch {
345 let Inst{31-26} = op;
346 let Inst{25-21} = rs;
348 let Inst{15-0} = offset;
351 class SLTI_FM<bits<6> op> : StdArch {
358 let Inst{31-26} = op;
359 let Inst{25-21} = rs;
360 let Inst{20-16} = rt;
361 let Inst{15-0} = imm16;
364 class MFLO_FM<bits<6> funct> : StdArch {
371 let Inst{15-11} = rd;
373 let Inst{5-0} = funct;
376 class MTLO_FM<bits<6> funct> : StdArch {
382 let Inst{25-21} = rs;
384 let Inst{5-0} = funct;
387 class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {
393 let Inst{31-26} = 0x1f;
395 let Inst{20-16} = rt;
396 let Inst{15-11} = rd;
397 let Inst{10-6} = funct;
398 let Inst{5-0} = funct2;
401 class CLO_FM<bits<6> funct> : StdArch {
408 let Inst{31-26} = 0x1c;
409 let Inst{25-21} = rs;
410 let Inst{20-16} = rt;
411 let Inst{15-11} = rd;
413 let Inst{5-0} = funct;
417 class LUI_FM : StdArch {
423 let Inst{31-26} = 0xf;
425 let Inst{20-16} = rt;
426 let Inst{15-0} = imm16;
436 let Inst{25-21} = rs;
438 let Inst{15-11} = rd;
443 class BGEZAL_FM<bits<5> funct> : StdArch {
450 let Inst{25-21} = rs;
451 let Inst{20-16} = funct;
452 let Inst{15-0} = offset;
455 class SYNC_FM : StdArch {
461 let Inst{10-6} = stype;
465 class SYNCI_FM : StdArch {
466 // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding).
468 bits<5> rs = addr{20-16};
469 bits<16> offset = addr{15-0};
473 let Inst{31-26} = 0b000001;
474 let Inst{25-21} = rs;
475 let Inst{20-16} = 0b11111;
476 let Inst{15-0} = offset;
479 class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
485 let Inst{31-26} = op;
486 let Inst{25-21} = rs;
487 let Inst{20-16} = rt;
489 let Inst{5-0} = funct;
492 class EXT_FM<bits<6> funct> : StdArch {
500 let Inst{31-26} = 0x1f;
501 let Inst{25-21} = rs;
502 let Inst{20-16} = rt;
503 let Inst{15-11} = size;
504 let Inst{10-6} = pos;
505 let Inst{5-0} = funct;
508 class RDHWR_FM : StdArch {
515 let Inst{31-26} = 0x1f;
517 let Inst{20-16} = rt;
518 let Inst{15-11} = rd;
519 let Inst{10-9} = 0b00;
521 let Inst{5-0} = 0x3b;
524 class TEQ_FM<bits<6> funct> : StdArch {
532 let Inst{25-21} = rs;
533 let Inst{20-16} = rt;
534 let Inst{15-6} = code_;
535 let Inst{5-0} = funct;
538 class TEQI_FM<bits<5> funct> : StdArch {
545 let Inst{25-21} = rs;
546 let Inst{20-16} = funct;
547 let Inst{15-0} = imm16;
550 class WAIT_FM : StdArch {
553 let Inst{31-26} = 0x10;
556 let Inst{5-0} = 0x20;
559 class EXTS_FM<bits<6> funct> : StdArch {
567 let Inst{31-26} = 0x1c;
568 let Inst{25-21} = rs;
569 let Inst{20-16} = rt;
570 let Inst{15-11} = lenm1;
571 let Inst{10-6} = pos;
572 let Inst{5-0} = funct;
575 class MTMR_FM<bits<6> funct> : StdArch {
580 let Inst{31-26} = 0x1c;
581 let Inst{25-21} = rs;
583 let Inst{5-0} = funct;
586 class POP_FM<bits<6> funct> : StdArch {
592 let Inst{31-26} = 0x1c;
593 let Inst{25-21} = rs;
595 let Inst{15-11} = rd;
597 let Inst{5-0} = funct;
600 class SEQ_FM<bits<6> funct> : StdArch {
607 let Inst{31-26} = 0x1c;
608 let Inst{25-21} = rs;
609 let Inst{20-16} = rt;
610 let Inst{15-11} = rd;
612 let Inst{5-0} = funct;
615 class SEQI_FM<bits<6> funct> : StdArch {
622 let Inst{31-26} = 0x1c;
623 let Inst{25-21} = rs;
624 let Inst{20-16} = rt;
625 let Inst{15-6} = imm10;
626 let Inst{5-0} = funct;
629 class SAA_FM<bits<6> funct> : StdArch {
635 let Inst{31-26} = 0x1c;
636 let Inst{25-21} = rs;
637 let Inst{20-16} = rt;
639 let Inst{5-0} = funct;
642 //===----------------------------------------------------------------------===//
643 // System calls format <op|code_|funct>
644 //===----------------------------------------------------------------------===//
646 class SYS_FM<bits<6> funct> : StdArch
650 let Inst{31-26} = 0x0;
651 let Inst{25-6} = code_;
652 let Inst{5-0} = funct;
655 //===----------------------------------------------------------------------===//
656 // Break instruction format <op|code_1|funct>
657 //===----------------------------------------------------------------------===//
659 class BRK_FM<bits<6> funct> : StdArch
664 let Inst{31-26} = 0x0;
665 let Inst{25-16} = code_1;
666 let Inst{15-6} = code_2;
667 let Inst{5-0} = funct;
670 //===----------------------------------------------------------------------===//
671 // Exception return format <Cop0|1|0|funct>
672 //===----------------------------------------------------------------------===//
674 class ER_FM<bits<6> funct, bit LLBit> : StdArch
677 let Inst{31-26} = 0x10;
681 let Inst{5-0} = funct;
684 //===----------------------------------------------------------------------===//
685 // Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
686 //===----------------------------------------------------------------------===//
688 class EI_FM<bits<1> sc> : StdArch
692 let Inst{31-26} = 0x10;
693 let Inst{25-21} = 0xb;
694 let Inst{20-16} = rt;
695 let Inst{15-11} = 0xc;
701 //===----------------------------------------------------------------------===//
703 // FLOATING POINT INSTRUCTION FORMATS
705 // opcode - operation code.
707 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
708 // fd - dst reg, only used on 3 regs instr.
709 // fmt - double or single precision.
710 // funct - combined with opcode field give us an operation code.
712 //===----------------------------------------------------------------------===//
714 //===----------------------------------------------------------------------===//
715 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
716 //===----------------------------------------------------------------------===//
718 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
719 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
727 let Inst{25-21} = base;
728 let Inst{20-16} = ft;
729 let Inst{15-0} = imm16;
732 class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {
739 let Inst{31-26} = 0x11;
740 let Inst{25-21} = fmt;
741 let Inst{20-16} = ft;
742 let Inst{15-11} = fs;
744 let Inst{5-0} = funct;
747 class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch {
753 let Inst{31-26} = 0x11;
754 let Inst{25-21} = fmt;
756 let Inst{15-11} = fs;
758 let Inst{5-0} = funct;
761 class MFC1_FM<bits<5> funct> : StdArch {
767 let Inst{31-26} = 0x11;
768 let Inst{25-21} = funct;
769 let Inst{20-16} = rt;
770 let Inst{15-11} = fs;
774 class LW_FM<bits<6> op> : StdArch {
780 let Inst{31-26} = op;
781 let Inst{25-21} = addr{20-16};
782 let Inst{20-16} = rt;
783 let Inst{15-0} = addr{15-0};
786 class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch {
794 let Inst{31-26} = 0x13;
795 let Inst{25-21} = fr;
796 let Inst{20-16} = ft;
797 let Inst{15-11} = fs;
799 let Inst{5-3} = funct;
803 class LWXC1_FM<bits<6> funct> : StdArch {
810 let Inst{31-26} = 0x13;
811 let Inst{25-21} = base;
812 let Inst{20-16} = index;
815 let Inst{5-0} = funct;
818 class SWXC1_FM<bits<6> funct> : StdArch {
825 let Inst{31-26} = 0x13;
826 let Inst{25-21} = base;
827 let Inst{20-16} = index;
828 let Inst{15-11} = fs;
830 let Inst{5-0} = funct;
833 class BC1F_FM<bit nd, bit tf> : StdArch {
839 let Inst{31-26} = 0x11;
840 let Inst{25-21} = 0x8;
841 let Inst{20-18} = fcc;
844 let Inst{15-0} = offset;
847 class CEQS_FM<bits<5> fmt> : StdArch {
855 let Inst{31-26} = 0x11;
856 let Inst{25-21} = fmt;
857 let Inst{20-16} = ft;
858 let Inst{15-11} = fs;
859 let Inst{10-8} = fcc;
861 let Inst{3-0} = cond;
864 class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
868 class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {
875 let Inst{31-26} = 0x11;
876 let Inst{25-21} = fmt;
877 let Inst{20-16} = rt;
878 let Inst{15-11} = fs;
880 let Inst{5-0} = funct;
883 class CMov_F_I_FM<bit tf> : StdArch {
891 let Inst{25-21} = rs;
892 let Inst{20-18} = fcc;
895 let Inst{15-11} = rd;
900 class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch {
907 let Inst{31-26} = 0x11;
908 let Inst{25-21} = fmt;
909 let Inst{20-18} = fcc;
912 let Inst{15-11} = fs;
914 let Inst{5-0} = 0x11;
917 class BARRIER_FM<bits<5> op> : StdArch {
920 let Inst{31-26} = 0; // SPECIAL
922 let Inst{20-16} = 0; // rt = 0
923 let Inst{15-11} = 0; // rd = 0
924 let Inst{10-6} = op; // Operation
925 let Inst{5-0} = 0; // SLL
928 class SDBBP_FM : StdArch {
933 let Inst{31-26} = 0b011100; // SPECIAL2
934 let Inst{25-6} = code_;
935 let Inst{5-0} = 0b111111; // SDBBP
938 class JR_HB_FM<bits<6> op> : StdArch{
943 let Inst{31-26} = 0; // SPECIAL
944 let Inst{25-21} = rs;
951 class JALR_HB_FM<bits<6> op> : StdArch {
957 let Inst{31-26} = 0; // SPECIAL
958 let Inst{25-21} = rs;
960 let Inst{15-11} = rd;
966 class COP0_TLB_FM<bits<6> op> : StdArch {
969 let Inst{31-26} = 0x10; // COP0
970 let Inst{25} = 1; // CO
972 let Inst{5-0} = op; // Operation
975 class CACHEOP_FM<bits<6> op> : StdArch {
978 bits<5> base = addr{20-16};
979 bits<16> offset = addr{15-0};
983 let Inst{31-26} = op;
984 let Inst{25-21} = base;
985 let Inst{20-16} = hint;
986 let Inst{15-0} = offset;
989 class HYPCALL_FM<bits<6> op> : StdArch {
994 let Inst{31-26} = 0b010000;
996 let Inst{20-11} = code_;