1 //===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes Mips MSA ASE instructions.
11 //===----------------------------------------------------------------------===//
13 def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
14 def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
17 SDTCisVT<3, OtherVT>]>;
18 def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
21 SDTCisVT<3, OtherVT>]>;
22 def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
23 SDTCisInt<1>, SDTCisVec<1>,
24 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
25 def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
26 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>;
27 def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
28 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
29 def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
30 SDTCisVT<2, i32>, SDTCisSameAs<0, 3>,
33 def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>;
34 def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>;
35 def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>;
36 def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>;
37 def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp,
38 [SDNPCommutative, SDNPAssociative]>;
39 def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>;
40 def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>;
41 def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
42 def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>;
43 def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>;
44 def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>;
45 def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
46 def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
47 def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>;
48 def MipsFMS : SDNode<"MipsISD::FMS", SDTFPTernaryOp>;
50 def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
51 def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
53 def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
54 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
55 def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
56 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
58 def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>;
59 def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>;
60 def immZExt3Ptr : ImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>;
61 def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>;
63 def timmZExt1Ptr : TImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>;
64 def timmZExt2Ptr : TImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>;
65 def timmZExt3Ptr : TImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>;
66 def timmZExt4Ptr : TImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>;
70 def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>;
73 def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx),
74 (MipsVExtractSExt node:$vec, node:$idx, i8)>;
75 def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
76 (MipsVExtractSExt node:$vec, node:$idx, i16)>;
77 def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
78 (MipsVExtractSExt node:$vec, node:$idx, i32)>;
79 def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx),
80 (MipsVExtractSExt node:$vec, node:$idx, i64)>;
82 def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx),
83 (MipsVExtractZExt node:$vec, node:$idx, i8)>;
84 def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
85 (MipsVExtractZExt node:$vec, node:$idx, i16)>;
86 def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
87 (MipsVExtractZExt node:$vec, node:$idx, i32)>;
88 def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx),
89 (MipsVExtractZExt node:$vec, node:$idx, i64)>;
91 def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
92 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
93 def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx),
94 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
95 def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
96 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
97 def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx),
98 (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>;
100 def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
101 (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
102 def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
103 (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
104 def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
105 (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
106 def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
107 (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
109 class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
110 PatFrag<(ops node:$lhs, node:$rhs),
111 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
113 // ISD::SETFALSE cannot occur
114 def vfseteq_v4f32 : vfsetcc_type<v4i32, v4f32, SETEQ>;
115 def vfseteq_v2f64 : vfsetcc_type<v2i64, v2f64, SETEQ>;
116 def vfsetge_v4f32 : vfsetcc_type<v4i32, v4f32, SETGE>;
117 def vfsetge_v2f64 : vfsetcc_type<v2i64, v2f64, SETGE>;
118 def vfsetgt_v4f32 : vfsetcc_type<v4i32, v4f32, SETGT>;
119 def vfsetgt_v2f64 : vfsetcc_type<v2i64, v2f64, SETGT>;
120 def vfsetle_v4f32 : vfsetcc_type<v4i32, v4f32, SETLE>;
121 def vfsetle_v2f64 : vfsetcc_type<v2i64, v2f64, SETLE>;
122 def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>;
123 def vfsetlt_v2f64 : vfsetcc_type<v2i64, v2f64, SETLT>;
124 def vfsetne_v4f32 : vfsetcc_type<v4i32, v4f32, SETNE>;
125 def vfsetne_v2f64 : vfsetcc_type<v2i64, v2f64, SETNE>;
126 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
127 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
128 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
129 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
130 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
131 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
132 def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
133 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
134 def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>;
135 def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
136 def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>;
137 def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
138 def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>;
139 def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
140 def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>;
141 def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>;
142 def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
143 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
144 def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>;
145 def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>;
146 def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>;
147 def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>;
148 def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
149 def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
150 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
151 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
152 def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
153 def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
154 // ISD::SETTRUE cannot occur
155 // ISD::SETFALSE2 cannot occur
156 // ISD::SETTRUE2 cannot occur
158 class vsetcc_type<ValueType ResTy, CondCode CC> :
159 PatFrag<(ops node:$lhs, node:$rhs),
160 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>;
162 def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>;
163 def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>;
164 def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>;
165 def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>;
166 def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>;
167 def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>;
168 def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>;
169 def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>;
170 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>;
171 def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>;
172 def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>;
173 def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>;
174 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
175 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
176 def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
177 def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
178 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
179 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
180 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
181 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
183 def vsplati8 : PatFrag<(ops node:$e0),
184 (v16i8 (build_vector node:$e0, node:$e0,
191 node:$e0, node:$e0))>;
192 def vsplati16 : PatFrag<(ops node:$e0),
193 (v8i16 (build_vector node:$e0, node:$e0,
196 node:$e0, node:$e0))>;
197 def vsplati32 : PatFrag<(ops node:$e0),
198 (v4i32 (build_vector node:$e0, node:$e0,
199 node:$e0, node:$e0))>;
201 def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{
203 SDNode *BV = N->getOperand(0).getNode();
204 EVT EltTy = N->getValueType(0).getVectorElementType();
206 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) &&
207 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
210 def vsplati64 : PatFrag<(ops node:$e0),
211 (v2i64 (build_vector node:$e0, node:$e0))>;
213 def vsplati64_splat_d : PatFrag<(ops node:$e0),
216 (v4i32 (build_vector node:$e0,
220 vsplati64_imm_eq_1))))>;
222 def vsplatf32 : PatFrag<(ops node:$e0),
223 (v4f32 (build_vector node:$e0, node:$e0,
224 node:$e0, node:$e0))>;
225 def vsplatf64 : PatFrag<(ops node:$e0),
226 (v2f64 (build_vector node:$e0, node:$e0))>;
228 def vsplati8_elt : PatFrag<(ops node:$v, node:$i),
229 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>;
230 def vsplati16_elt : PatFrag<(ops node:$v, node:$i),
231 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>;
232 def vsplati32_elt : PatFrag<(ops node:$v, node:$i),
233 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>;
234 def vsplati64_elt : PatFrag<(ops node:$v, node:$i),
235 (MipsVSHF (vsplati64_splat_d node:$i),
238 class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}],
239 SDNodeXForm xform = NOOP_SDNodeXForm>
240 : PatLeaf<frag, pred, xform> {
241 Operand OpClass = opclass;
244 class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn,
245 list<SDNode> roots = [],
246 list<SDNodeProperty> props = []> :
247 ComplexPattern<ty, numops, fn, roots, props> {
248 Operand OpClass = opclass;
251 def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,
253 [build_vector, bitconvert]>;
255 def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1,
257 [build_vector, bitconvert]>;
259 def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1,
261 [build_vector, bitconvert]>;
263 def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1,
265 [build_vector, bitconvert]>;
267 def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1,
269 [build_vector, bitconvert]>;
271 def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1,
273 [build_vector, bitconvert]>;
275 def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1,
277 [build_vector, bitconvert]>;
279 def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1,
281 [build_vector, bitconvert]>;
283 def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1,
285 [build_vector, bitconvert]>;
287 def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1,
289 [build_vector, bitconvert]>;
291 def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1,
293 [build_vector, bitconvert]>;
295 def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1,
297 [build_vector, bitconvert]>;
299 def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1,
301 [build_vector, bitconvert]>;
303 def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1,
305 [build_vector, bitconvert]>;
307 def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1,
309 [build_vector, bitconvert]>;
311 def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1,
313 [build_vector, bitconvert]>;
315 // Any build_vector that is a constant splat with a value that is an exact
317 def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",
318 [build_vector, bitconvert]>;
320 // Any build_vector that is a constant splat with a value that is the bitwise
321 // inverse of an exact power of 2
322 def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2",
323 [build_vector, bitconvert]>;
325 // Any build_vector that is a constant splat with only a consecutive sequence
326 // of left-most bits set.
327 def vsplat_maskl_bits_uimm3
328 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskL",
329 [build_vector, bitconvert]>;
330 def vsplat_maskl_bits_uimm4
331 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskL",
332 [build_vector, bitconvert]>;
333 def vsplat_maskl_bits_uimm5
334 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskL",
335 [build_vector, bitconvert]>;
336 def vsplat_maskl_bits_uimm6
337 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskL",
338 [build_vector, bitconvert]>;
340 // Any build_vector that is a constant splat with only a consecutive sequence
341 // of right-most bits set.
342 def vsplat_maskr_bits_uimm3
343 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskR",
344 [build_vector, bitconvert]>;
345 def vsplat_maskr_bits_uimm4
346 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskR",
347 [build_vector, bitconvert]>;
348 def vsplat_maskr_bits_uimm5
349 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskR",
350 [build_vector, bitconvert]>;
351 def vsplat_maskr_bits_uimm6
352 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskR",
353 [build_vector, bitconvert]>;
355 // Any build_vector that is a constant splat with a value that equals 1
356 // FIXME: These should be a ComplexPattern but we can't use them because the
357 // ISel generator requires the uses to have a name, but providing a name
358 // causes other errors ("used in pattern but not operand list")
359 def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{
361 EVT EltTy = N->getValueType(0).getVectorElementType();
363 return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&
364 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
367 def vbclr_b : PatFrag<(ops node:$ws, node:$wt),
368 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
370 def vbclr_h : PatFrag<(ops node:$ws, node:$wt),
371 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
373 def vbclr_w : PatFrag<(ops node:$ws, node:$wt),
374 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
376 def vbclr_d : PatFrag<(ops node:$ws, node:$wt),
377 (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1),
379 (bitconvert (v4i32 immAllOnesV))))>;
381 def vbneg_b : PatFrag<(ops node:$ws, node:$wt),
382 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
383 def vbneg_h : PatFrag<(ops node:$ws, node:$wt),
384 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
385 def vbneg_w : PatFrag<(ops node:$ws, node:$wt),
386 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
387 def vbneg_d : PatFrag<(ops node:$ws, node:$wt),
388 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
391 def vbset_b : PatFrag<(ops node:$ws, node:$wt),
392 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
393 def vbset_h : PatFrag<(ops node:$ws, node:$wt),
394 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
395 def vbset_w : PatFrag<(ops node:$ws, node:$wt),
396 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
397 def vbset_d : PatFrag<(ops node:$ws, node:$wt),
398 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
401 def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt),
402 (add node:$wd, (mul node:$ws, node:$wt))>;
404 def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
405 (sub node:$wd, (mul node:$ws, node:$wt))>;
407 def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
408 (fmul node:$ws, (fexp2 node:$wt))>;
410 // Instruction encoding.
411 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
412 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
413 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
414 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
416 class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
417 class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
418 class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>;
419 class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>;
421 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
422 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
423 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
424 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
426 class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
427 class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
428 class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>;
429 class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>;
431 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
432 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
433 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
434 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
436 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
437 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
438 class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
439 class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>;
441 class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>;
443 class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
445 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
446 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
447 class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
448 class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
450 class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
451 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
452 class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
453 class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>;
455 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
456 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
457 class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
458 class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
460 class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>;
461 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
462 class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
463 class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>;
465 class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>;
466 class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>;
467 class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>;
468 class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>;
470 class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>;
471 class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>;
472 class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>;
473 class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>;
475 class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>;
476 class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>;
477 class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>;
478 class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>;
480 class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>;
481 class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>;
482 class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>;
483 class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>;
485 class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>;
486 class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>;
487 class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>;
488 class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>;
490 class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>;
491 class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>;
492 class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>;
493 class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>;
495 class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>;
496 class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>;
497 class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>;
498 class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>;
500 class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>;
501 class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>;
502 class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>;
503 class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>;
505 class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>;
507 class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>;
509 class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>;
511 class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>;
513 class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>;
514 class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>;
515 class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>;
516 class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>;
518 class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>;
519 class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>;
520 class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>;
521 class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>;
523 class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>;
524 class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>;
525 class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>;
526 class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>;
528 class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>;
530 class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>;
532 class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>;
534 class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
535 class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>;
536 class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>;
537 class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>;
539 class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>;
540 class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>;
541 class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>;
542 class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>;
544 class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>;
545 class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>;
546 class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>;
547 class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>;
549 class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>;
551 class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>;
552 class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>;
553 class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>;
554 class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>;
556 class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>;
557 class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>;
558 class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>;
559 class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>;
561 class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>;
563 class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>;
564 class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>;
565 class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>;
566 class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>;
568 class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>;
569 class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>;
570 class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>;
571 class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>;
573 class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>;
574 class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>;
575 class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>;
576 class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>;
578 class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>;
579 class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>;
580 class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>;
581 class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>;
583 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
584 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
585 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
586 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
588 class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>;
589 class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>;
590 class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>;
591 class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>;
593 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
594 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
595 class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>;
596 class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>;
598 class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>;
599 class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>;
600 class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>;
601 class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>;
603 class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
604 class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
605 class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
606 class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>;
608 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
609 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
610 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
612 class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
614 class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>;
615 class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>;
616 class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>;
617 class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>;
619 class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>;
620 class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>;
621 class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>;
622 class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>;
624 class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>;
625 class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>;
626 class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>;
628 class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>;
629 class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>;
630 class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>;
632 class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>;
633 class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>;
634 class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>;
636 class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>;
637 class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>;
638 class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>;
640 class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>;
641 class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>;
642 class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>;
644 class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>;
645 class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>;
646 class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>;
648 class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>;
649 class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
651 class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>;
652 class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>;
654 class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
655 class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
657 class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>;
658 class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>;
660 class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>;
661 class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>;
663 class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
664 class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
666 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
667 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
669 class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
670 class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
672 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
673 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
675 class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
676 class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
678 class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
679 class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
681 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
682 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
684 class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
685 class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
687 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
688 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
690 class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
691 class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
693 class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;
694 class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;
696 class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>;
697 class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>;
699 class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>;
700 class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>;
702 class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>;
703 class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>;
705 class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>;
706 class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>;
708 class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>;
709 class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>;
711 class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>;
712 class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>;
714 class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>;
715 class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>;
716 class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>;
717 class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>;
719 class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>;
720 class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>;
722 class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
723 class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
725 class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>;
726 class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>;
728 class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>;
729 class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>;
731 class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>;
732 class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>;
734 class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>;
735 class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>;
737 class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;
738 class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;
740 class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
741 class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
743 class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>;
744 class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>;
746 class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>;
747 class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>;
749 class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>;
750 class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
752 class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
753 class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
755 class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
756 class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
758 class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>;
759 class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;
761 class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
762 class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
764 class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;
765 class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;
767 class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
768 class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
770 class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>;
771 class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
773 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
774 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
776 class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
777 class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
779 class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
780 class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
782 class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
783 class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
785 class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
786 class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
788 class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;
789 class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;
791 class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>;
792 class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>;
794 class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>;
795 class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>;
797 class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;
798 class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
800 class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>;
801 class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>;
803 class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>;
804 class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>;
806 class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>;
807 class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>;
808 class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>;
810 class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>;
811 class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>;
812 class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>;
814 class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>;
815 class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>;
816 class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>;
818 class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>;
819 class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>;
820 class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>;
822 class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>;
823 class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>;
824 class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>;
825 class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>;
827 class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>;
828 class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>;
829 class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>;
830 class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>;
832 class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>;
833 class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>;
834 class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>;
835 class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>;
837 class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>;
838 class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>;
839 class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>;
840 class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>;
842 class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
843 class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
844 class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
845 class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>;
847 class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;
848 class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
849 class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;
850 class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;
852 class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>;
853 class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>;
854 class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>;
855 class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>;
857 class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>;
858 class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>;
859 class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>;
860 class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>;
862 class LSA_ENC : SPECIAL_LSA_FMT<0b000101>;
863 class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>;
865 class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
866 class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
868 class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>;
869 class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>;
871 class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>;
872 class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>;
873 class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>;
874 class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>;
876 class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>;
877 class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>;
878 class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>;
879 class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>;
881 class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>;
882 class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>;
883 class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>;
884 class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>;
886 class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>;
887 class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>;
888 class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>;
889 class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>;
891 class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>;
892 class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>;
893 class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>;
894 class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>;
896 class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>;
897 class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>;
898 class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>;
899 class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>;
901 class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>;
902 class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>;
903 class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>;
904 class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>;
906 class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>;
907 class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>;
908 class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>;
909 class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>;
911 class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>;
912 class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>;
913 class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>;
914 class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>;
916 class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>;
917 class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>;
918 class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>;
919 class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>;
921 class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>;
922 class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>;
923 class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>;
924 class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>;
926 class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>;
927 class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>;
928 class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>;
929 class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>;
931 class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>;
932 class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>;
933 class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>;
934 class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>;
936 class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>;
938 class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>;
939 class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>;
941 class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;
942 class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
944 class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>;
945 class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>;
946 class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>;
947 class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>;
949 class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
950 class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
952 class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
953 class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
955 class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>;
956 class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>;
957 class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>;
958 class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>;
960 class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>;
961 class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>;
962 class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>;
963 class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>;
965 class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>;
966 class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>;
967 class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>;
968 class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>;
970 class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>;
972 class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>;
974 class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>;
976 class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>;
978 class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>;
979 class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>;
980 class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>;
981 class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>;
983 class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>;
984 class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>;
985 class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>;
986 class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>;
988 class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>;
989 class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>;
990 class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>;
991 class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>;
993 class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>;
994 class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>;
995 class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>;
996 class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>;
998 class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>;
999 class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>;
1000 class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>;
1001 class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>;
1003 class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>;
1004 class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>;
1005 class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>;
1007 class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>;
1008 class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>;
1009 class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>;
1010 class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>;
1012 class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>;
1013 class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>;
1014 class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>;
1015 class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>;
1017 class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>;
1018 class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>;
1019 class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>;
1020 class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>;
1022 class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>;
1023 class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>;
1024 class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>;
1025 class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>;
1027 class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>;
1028 class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>;
1029 class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>;
1030 class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>;
1032 class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
1033 class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
1034 class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
1035 class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
1037 class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>;
1038 class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>;
1039 class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>;
1040 class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>;
1042 class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>;
1043 class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>;
1044 class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>;
1045 class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>;
1047 class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>;
1048 class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>;
1049 class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>;
1050 class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>;
1052 class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>;
1053 class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>;
1054 class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>;
1055 class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>;
1057 class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>;
1058 class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>;
1059 class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>;
1060 class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>;
1062 class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>;
1063 class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>;
1064 class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>;
1065 class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>;
1067 class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>;
1068 class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>;
1069 class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>;
1070 class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>;
1072 class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>;
1073 class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
1074 class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
1075 class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
1077 class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>;
1078 class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>;
1079 class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>;
1080 class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>;
1082 class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>;
1083 class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>;
1084 class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>;
1085 class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>;
1087 class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>;
1088 class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>;
1089 class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>;
1090 class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>;
1092 class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>;
1093 class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>;
1094 class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>;
1095 class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>;
1097 class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>;
1098 class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>;
1099 class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>;
1100 class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>;
1102 class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>;
1103 class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>;
1104 class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>;
1105 class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>;
1107 class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>;
1108 class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>;
1109 class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>;
1110 class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>;
1112 class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>;
1113 class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>;
1114 class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>;
1115 class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>;
1117 class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>;
1119 class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
1121 // Instruction desc.
1122 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1123 ComplexPattern Imm, RegisterOperand ROWD,
1124 RegisterOperand ROWS = ROWD,
1125 InstrItinClass itin = NoItinerary> {
1126 dag OutOperandList = (outs ROWD:$wd);
1127 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m);
1128 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1129 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1130 InstrItinClass Itinerary = itin;
1133 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1134 ComplexPattern Imm, RegisterOperand ROWD,
1135 RegisterOperand ROWS = ROWD,
1136 InstrItinClass itin = NoItinerary> {
1137 dag OutOperandList = (outs ROWD:$wd);
1138 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m);
1139 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1140 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1141 InstrItinClass Itinerary = itin;
1144 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1145 ComplexPattern Imm, RegisterOperand ROWD,
1146 RegisterOperand ROWS = ROWD,
1147 InstrItinClass itin = NoItinerary> {
1148 dag OutOperandList = (outs ROWD:$wd);
1149 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m);
1150 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1151 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1152 InstrItinClass Itinerary = itin;
1155 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1156 ComplexPattern Imm, RegisterOperand ROWD,
1157 RegisterOperand ROWS = ROWD,
1158 InstrItinClass itin = NoItinerary> {
1159 dag OutOperandList = (outs ROWD:$wd);
1160 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m);
1161 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1162 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1163 InstrItinClass Itinerary = itin;
1166 class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1167 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1168 RegisterOperand ROWS = ROWD,
1169 InstrItinClass itin = NoItinerary> {
1170 dag OutOperandList = (outs ROWD:$wd);
1171 dag InOperandList = (ins ROWS:$ws, ImmOp:$m);
1172 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1173 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1174 InstrItinClass Itinerary = itin;
1177 class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty,
1178 SplatComplexPattern Mask, RegisterOperand ROWD,
1179 RegisterOperand ROWS = ROWD,
1180 InstrItinClass itin = NoItinerary> {
1181 dag OutOperandList = (outs ROWD:$wd);
1182 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, Mask.OpClass:$m);
1183 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1184 // Note that binsxi and vselect treat the condition operand the opposite
1185 // way to each other.
1186 // (vselect cond, if_set, if_clear)
1187 // (BSEL_V cond, if_clear, if_set)
1188 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws),
1190 InstrItinClass Itinerary = itin;
1191 string Constraints = "$wd = $wd_in";
1194 class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty,
1195 SplatComplexPattern ImmOp, RegisterOperand ROWD,
1196 RegisterOperand ROWS = ROWD,
1197 InstrItinClass itin = NoItinerary> :
1198 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>;
1200 class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty,
1201 SplatComplexPattern ImmOp, RegisterOperand ROWD,
1202 RegisterOperand ROWS = ROWD,
1203 InstrItinClass itin = NoItinerary> :
1204 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>;
1206 class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1207 SplatComplexPattern SplatImm,
1208 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1209 InstrItinClass itin = NoItinerary> {
1210 dag OutOperandList = (outs ROWD:$wd);
1211 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
1212 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1213 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
1214 InstrItinClass Itinerary = itin;
1217 class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1218 ValueType VecTy, Operand ImmOp, ImmLeaf Imm,
1219 RegisterOperand ROD, RegisterOperand ROWS,
1220 InstrItinClass itin = NoItinerary> {
1221 dag OutOperandList = (outs ROD:$rd);
1222 dag InOperandList = (ins ROWS:$ws, ImmOp:$n);
1223 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
1224 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), Imm:$n))];
1225 InstrItinClass Itinerary = itin;
1228 class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1229 RegisterOperand ROWD, RegisterOperand ROWS,
1230 Operand ImmOp, ImmLeaf Imm,
1231 InstrItinClass itin = NoItinerary> {
1232 dag OutOperandList = (outs ROWD:$wd);
1233 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n);
1234 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1235 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1237 string Constraints = "$wd = $wd_in";
1238 InstrItinClass Itinerary = itin;
1241 class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
1242 Operand ImmOp, ImmLeaf Imm, RegisterClass RCD,
1243 RegisterClass RCWS> :
1244 MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, ImmOp:$n),
1245 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), Imm:$n))]> {
1246 bit usesCustomInserter = 1;
1247 bit hasNoSchedulingInfo = 1;
1250 class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1251 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1252 RegisterOperand ROWS = ROWD,
1253 InstrItinClass itin = NoItinerary> {
1254 dag OutOperandList = (outs ROWD:$wd);
1255 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm);
1256 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm");
1257 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))];
1258 InstrItinClass Itinerary = itin;
1261 class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1262 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1263 RegisterOperand ROWS = ROWD,
1264 InstrItinClass itin = NoItinerary> {
1265 dag OutOperandList = (outs ROWD:$wd);
1266 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8);
1267 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1268 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))];
1269 InstrItinClass Itinerary = itin;
1272 class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1273 RegisterOperand ROWS = ROWD,
1274 InstrItinClass itin = NoItinerary> {
1275 dag OutOperandList = (outs ROWD:$wd);
1276 dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1277 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1278 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF timmZExt8:$u8, ROWS:$ws))];
1279 InstrItinClass Itinerary = itin;
1282 class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1283 InstrItinClass itin = NoItinerary> {
1284 dag OutOperandList = (outs ROWD:$wd);
1285 dag InOperandList = (ins vsplat_simm10:$s10);
1286 string AsmString = !strconcat(instr_asm, "\t$wd, $s10");
1287 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp
1288 list<dag> Pattern = [];
1289 bit hasSideEffects = 0;
1290 bit isReMaterializable = 1;
1291 InstrItinClass Itinerary = itin;
1294 class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1295 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1296 InstrItinClass itin = NoItinerary> {
1297 dag OutOperandList = (outs ROWD:$wd);
1298 dag InOperandList = (ins ROWS:$ws);
1299 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1300 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1301 InstrItinClass Itinerary = itin;
1304 class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
1305 SDPatternOperator OpNode, RegisterOperand ROWD,
1306 RegisterOperand ROS = ROWD,
1307 InstrItinClass itin = NoItinerary> {
1308 dag OutOperandList = (outs ROWD:$wd);
1309 dag InOperandList = (ins ROS:$rs);
1310 string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
1311 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
1312 InstrItinClass Itinerary = itin;
1315 class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode,
1316 RegisterClass RCWD, RegisterClass RCWS = RCWD> :
1317 MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs),
1318 [(set RCWD:$wd, (OpNode RCWS:$fs))]> {
1319 let usesCustomInserter = 1;
1322 class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1323 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1324 InstrItinClass itin = NoItinerary> {
1325 dag OutOperandList = (outs ROWD:$wd);
1326 dag InOperandList = (ins ROWS:$ws);
1327 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1328 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1329 InstrItinClass Itinerary = itin;
1332 class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1333 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1334 RegisterOperand ROWT = ROWD,
1335 InstrItinClass itin = NoItinerary> {
1336 dag OutOperandList = (outs ROWD:$wd);
1337 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1338 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1339 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1340 InstrItinClass Itinerary = itin;
1343 class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1344 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1345 RegisterOperand ROWT = ROWD,
1346 InstrItinClass itin = NoItinerary> {
1347 dag OutOperandList = (outs ROWD:$wd);
1348 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1349 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1350 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1352 string Constraints = "$wd = $wd_in";
1353 InstrItinClass Itinerary = itin;
1356 class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1357 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1358 InstrItinClass itin = NoItinerary> {
1359 dag OutOperandList = (outs ROWD:$wd);
1360 dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt);
1361 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1362 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))];
1363 InstrItinClass Itinerary = itin;
1366 class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1367 RegisterOperand ROWS = ROWD,
1368 RegisterOperand ROWT = ROWD,
1369 InstrItinClass itin = NoItinerary> {
1370 dag OutOperandList = (outs ROWD:$wd);
1371 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1372 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1373 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws,
1375 string Constraints = "$wd = $wd_in";
1376 InstrItinClass Itinerary = itin;
1379 class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1380 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1381 InstrItinClass itin = NoItinerary> {
1382 dag OutOperandList = (outs ROWD:$wd);
1383 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt);
1384 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1385 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1387 InstrItinClass Itinerary = itin;
1388 string Constraints = "$wd = $wd_in";
1391 class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1392 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1393 RegisterOperand ROWT = ROWD,
1394 InstrItinClass itin = NoItinerary> {
1395 dag OutOperandList = (outs ROWD:$wd);
1396 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1397 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1398 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1400 InstrItinClass Itinerary = itin;
1401 string Constraints = "$wd = $wd_in";
1404 class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1405 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1406 RegisterOperand ROWT = ROWD,
1407 InstrItinClass itin = NoItinerary> :
1408 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1410 class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1411 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1412 RegisterOperand ROWT = ROWD,
1413 InstrItinClass itin = NoItinerary> :
1414 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1416 class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
1417 dag OutOperandList = (outs);
1418 dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
1419 string AsmString = !strconcat(instr_asm, "\t$wt, $offset");
1420 list<dag> Pattern = [];
1421 InstrItinClass Itinerary = NoItinerary;
1423 bit isTerminator = 1;
1424 bit hasDelaySlot = 1;
1425 list<Register> Defs = [AT];
1428 class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1429 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1430 RegisterOperand ROS,
1431 InstrItinClass itin = NoItinerary> {
1432 dag OutOperandList = (outs ROWD:$wd);
1433 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, ImmOp:$n);
1434 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
1435 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROS:$rs, Imm:$n))];
1436 InstrItinClass Itinerary = itin;
1437 string Constraints = "$wd = $wd_in";
1440 class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1441 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1442 RegisterOperand ROFS> :
1443 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ImmOp:$n, ROFS:$fs),
1444 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, Imm:$n))]> {
1445 bit usesCustomInserter = 1;
1446 string Constraints = "$wd = $wd_in";
1449 class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1450 RegisterOperand ROWD, RegisterOperand ROFS,
1451 RegisterOperand ROIdx> :
1452 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs),
1453 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
1455 bit usesCustomInserter = 1;
1456 bit hasNoSchedulingInfo = 1;
1457 string Constraints = "$wd = $wd_in";
1460 class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1461 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1462 RegisterOperand ROWS = ROWD,
1463 InstrItinClass itin = NoItinerary> {
1464 dag OutOperandList = (outs ROWD:$wd);
1465 dag InOperandList = (ins ROWD:$wd_in, ImmOp:$n, ROWS:$ws, uimmz:$n2);
1466 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]");
1467 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1471 InstrItinClass Itinerary = itin;
1472 string Constraints = "$wd = $wd_in";
1475 class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1476 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1477 RegisterOperand ROWT = ROWD,
1478 InstrItinClass itin = NoItinerary> {
1479 dag OutOperandList = (outs ROWD:$wd);
1480 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1481 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1482 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1483 InstrItinClass Itinerary = itin;
1486 class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm,
1487 RegisterOperand ROWD,
1488 RegisterOperand ROWS = ROWD,
1489 InstrItinClass itin = NoItinerary> {
1490 dag OutOperandList = (outs ROWD:$wd);
1491 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n);
1492 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1493 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws,
1495 InstrItinClass Itinerary = itin;
1498 class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD,
1499 RegisterOperand ROWS = ROWD,
1500 RegisterOperand ROWT = ROWD> :
1501 MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt),
1502 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
1504 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1506 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1508 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1510 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
1513 class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b,
1514 MSA128BOpnd>, IsCommutable;
1515 class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h,
1516 MSA128HOpnd>, IsCommutable;
1517 class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w,
1518 MSA128WOpnd>, IsCommutable;
1519 class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d,
1520 MSA128DOpnd>, IsCommutable;
1522 class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b,
1523 MSA128BOpnd>, IsCommutable;
1524 class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h,
1525 MSA128HOpnd>, IsCommutable;
1526 class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w,
1527 MSA128WOpnd>, IsCommutable;
1528 class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d,
1529 MSA128DOpnd>, IsCommutable;
1531 class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b,
1532 MSA128BOpnd>, IsCommutable;
1533 class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h,
1534 MSA128HOpnd>, IsCommutable;
1535 class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w,
1536 MSA128WOpnd>, IsCommutable;
1537 class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d,
1538 MSA128DOpnd>, IsCommutable;
1540 class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable;
1541 class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable;
1542 class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable;
1543 class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable;
1545 class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5,
1547 class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5,
1549 class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5,
1551 class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5,
1554 class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>;
1555 class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>;
1556 class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>;
1557 class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>;
1559 class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8,
1562 class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b,
1564 class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h,
1566 class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w,
1568 class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d,
1571 class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b,
1573 class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h,
1575 class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w,
1577 class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d,
1580 class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>,
1582 class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>,
1584 class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>,
1586 class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>,
1589 class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>,
1591 class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>,
1593 class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>,
1595 class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>,
1598 class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b,
1599 MSA128BOpnd>, IsCommutable;
1600 class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h,
1601 MSA128HOpnd>, IsCommutable;
1602 class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w,
1603 MSA128WOpnd>, IsCommutable;
1604 class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d,
1605 MSA128DOpnd>, IsCommutable;
1607 class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b,
1608 MSA128BOpnd>, IsCommutable;
1609 class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h,
1610 MSA128HOpnd>, IsCommutable;
1611 class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w,
1612 MSA128WOpnd>, IsCommutable;
1613 class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d,
1614 MSA128DOpnd>, IsCommutable;
1616 class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>;
1617 class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>;
1618 class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>;
1619 class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>;
1621 class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2,
1623 class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2,
1625 class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2,
1627 class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2,
1630 class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b,
1632 class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h,
1634 class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w,
1636 class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d,
1639 class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, vsplat_maskl_bits_uimm3, MSA128BOpnd>;
1640 class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, vsplat_maskl_bits_uimm4, MSA128HOpnd>;
1641 class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, vsplat_maskl_bits_uimm5, MSA128WOpnd>;
1642 class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, vsplat_maskl_bits_uimm6, MSA128DOpnd>;
1644 class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b,
1646 class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h,
1648 class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w,
1650 class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d,
1654 : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, vsplat_maskr_bits_uimm3,
1657 : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, vsplat_maskr_bits_uimm4,
1660 : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, vsplat_maskr_bits_uimm5,
1663 : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, vsplat_maskr_bits_uimm6,
1667 dag OutOperandList = (outs MSA128BOpnd:$wd);
1668 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1670 string AsmString = "bmnz.v\t$wd, $ws, $wt";
1671 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1673 MSA128BOpnd:$wd_in))];
1674 InstrItinClass Itinerary = NoItinerary;
1675 string Constraints = "$wd = $wd_in";
1678 class BMNZI_B_DESC {
1679 dag OutOperandList = (outs MSA128BOpnd:$wd);
1680 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1682 string AsmString = "bmnzi.b\t$wd, $ws, $u8";
1683 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1685 MSA128BOpnd:$wd_in))];
1686 InstrItinClass Itinerary = NoItinerary;
1687 string Constraints = "$wd = $wd_in";
1691 dag OutOperandList = (outs MSA128BOpnd:$wd);
1692 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1694 string AsmString = "bmz.v\t$wd, $ws, $wt";
1695 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1698 InstrItinClass Itinerary = NoItinerary;
1699 string Constraints = "$wd = $wd_in";
1703 dag OutOperandList = (outs MSA128BOpnd:$wd);
1704 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1706 string AsmString = "bmzi.b\t$wd, $ws, $u8";
1707 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1710 InstrItinClass Itinerary = NoItinerary;
1711 string Constraints = "$wd = $wd_in";
1714 class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>;
1715 class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>;
1716 class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>;
1717 class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>;
1719 class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2,
1721 class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2,
1723 class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2,
1725 class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2,
1728 class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>;
1729 class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>;
1730 class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>;
1731 class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>;
1733 class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>;
1736 dag OutOperandList = (outs MSA128BOpnd:$wd);
1737 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1739 string AsmString = "bsel.v\t$wd, $ws, $wt";
1740 // Note that vselect and BSEL_V treat the condition operand the opposite way
1742 // (vselect cond, if_set, if_clear)
1743 // (BSEL_V cond, if_clear, if_set)
1744 list<dag> Pattern = [(set MSA128BOpnd:$wd,
1745 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt,
1747 InstrItinClass Itinerary = NoItinerary;
1748 string Constraints = "$wd = $wd_in";
1751 class BSELI_B_DESC {
1752 dag OutOperandList = (outs MSA128BOpnd:$wd);
1753 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1755 string AsmString = "bseli.b\t$wd, $ws, $u8";
1756 // Note that vselect and BSEL_V treat the condition operand the opposite way
1758 // (vselect cond, if_set, if_clear)
1759 // (BSEL_V cond, if_clear, if_set)
1760 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in,
1763 InstrItinClass Itinerary = NoItinerary;
1764 string Constraints = "$wd = $wd_in";
1767 class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>;
1768 class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>;
1769 class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>;
1770 class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>;
1772 class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2,
1774 class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2,
1776 class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2,
1778 class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2,
1781 class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>;
1782 class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>;
1783 class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>;
1784 class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>;
1786 class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>;
1788 class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>,
1790 class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>,
1792 class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>,
1794 class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>,
1797 class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5,
1799 class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5,
1801 class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5,
1803 class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5,
1807 dag OutOperandList = (outs GPR32Opnd:$rd);
1808 dag InOperandList = (ins MSA128CROpnd:$cs);
1809 string AsmString = "cfcmsa\t$rd, $cs";
1810 InstrItinClass Itinerary = NoItinerary;
1811 bit hasSideEffects = 1;
1815 class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>;
1816 class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>;
1817 class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>;
1818 class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>;
1820 class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>;
1821 class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>;
1822 class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>;
1823 class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>;
1825 class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8,
1826 vsplati8_simm5, MSA128BOpnd>;
1827 class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16,
1828 vsplati16_simm5, MSA128HOpnd>;
1829 class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32,
1830 vsplati32_simm5, MSA128WOpnd>;
1831 class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64,
1832 vsplati64_simm5, MSA128DOpnd>;
1834 class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8,
1835 vsplati8_uimm5, MSA128BOpnd>;
1836 class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16,
1837 vsplati16_uimm5, MSA128HOpnd>;
1838 class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32,
1839 vsplati32_uimm5, MSA128WOpnd>;
1840 class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64,
1841 vsplati64_uimm5, MSA128DOpnd>;
1843 class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>;
1844 class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>;
1845 class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>;
1846 class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>;
1848 class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>;
1849 class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>;
1850 class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>;
1851 class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>;
1853 class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8,
1854 vsplati8_simm5, MSA128BOpnd>;
1855 class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16,
1856 vsplati16_simm5, MSA128HOpnd>;
1857 class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32,
1858 vsplati32_simm5, MSA128WOpnd>;
1859 class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64,
1860 vsplati64_simm5, MSA128DOpnd>;
1862 class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8,
1863 vsplati8_uimm5, MSA128BOpnd>;
1864 class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16,
1865 vsplati16_uimm5, MSA128HOpnd>;
1866 class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32,
1867 vsplati32_uimm5, MSA128WOpnd>;
1868 class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64,
1869 vsplati64_uimm5, MSA128DOpnd>;
1871 class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8,
1872 uimm4_ptr, immZExt4Ptr, GPR32Opnd,
1874 class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
1875 uimm3_ptr, immZExt3Ptr, GPR32Opnd,
1877 class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
1878 uimm2_ptr, immZExt2Ptr, GPR32Opnd,
1880 class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64,
1881 uimm1_ptr, immZExt1Ptr, GPR64Opnd,
1884 class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8,
1885 uimm4_ptr, immZExt4Ptr, GPR32Opnd,
1887 class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
1888 uimm3_ptr, immZExt3Ptr, GPR32Opnd,
1890 class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
1891 uimm2_ptr, immZExt2Ptr, GPR32Opnd,
1894 class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32,
1895 uimm2_ptr, immZExt2Ptr, FGR32,
1897 class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64,
1898 uimm1_ptr, immZExt1Ptr, FGR64,
1902 dag OutOperandList = (outs);
1903 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
1904 string AsmString = "ctcmsa\t$cd, $rs";
1905 InstrItinClass Itinerary = NoItinerary;
1906 bit hasSideEffects = 1;
1910 class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>;
1911 class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>;
1912 class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>;
1913 class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>;
1915 class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>;
1916 class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>;
1917 class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>;
1918 class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>;
1920 class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h,
1921 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1923 class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w,
1924 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1926 class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d,
1927 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1930 class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h,
1931 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1933 class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w,
1934 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1936 class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d,
1937 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1940 class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h,
1941 MSA128HOpnd, MSA128BOpnd,
1942 MSA128BOpnd>, IsCommutable;
1943 class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w,
1944 MSA128WOpnd, MSA128HOpnd,
1945 MSA128HOpnd>, IsCommutable;
1946 class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d,
1947 MSA128DOpnd, MSA128WOpnd,
1948 MSA128WOpnd>, IsCommutable;
1950 class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h,
1951 MSA128HOpnd, MSA128BOpnd,
1952 MSA128BOpnd>, IsCommutable;
1953 class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w,
1954 MSA128WOpnd, MSA128HOpnd,
1955 MSA128HOpnd>, IsCommutable;
1956 class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d,
1957 MSA128DOpnd, MSA128WOpnd,
1958 MSA128WOpnd>, IsCommutable;
1960 class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h,
1961 MSA128HOpnd, MSA128BOpnd,
1963 class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w,
1964 MSA128WOpnd, MSA128HOpnd,
1966 class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d,
1967 MSA128DOpnd, MSA128WOpnd,
1970 class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h,
1971 MSA128HOpnd, MSA128BOpnd,
1973 class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w,
1974 MSA128WOpnd, MSA128HOpnd,
1976 class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d,
1977 MSA128DOpnd, MSA128WOpnd,
1980 class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>,
1982 class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>,
1985 class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>,
1987 class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>,
1990 class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>,
1992 class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>,
1995 class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w,
1997 class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d,
2000 class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>;
2001 class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>;
2003 class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>;
2004 class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>;
2006 class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>,
2008 class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>,
2011 class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>,
2013 class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>,
2016 class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>,
2018 class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>,
2021 class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>,
2023 class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>,
2026 class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>,
2028 class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>,
2031 class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>,
2033 class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>,
2036 class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>,
2038 class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>,
2041 class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>;
2042 class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>;
2044 class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h,
2045 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2046 class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w,
2047 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2049 // The fexp2.df instruction multiplies the first operand by 2 to the power of
2050 // the second operand. We therefore need a pseudo-insn in order to invent the
2051 // 1.0 when we only need to match ISD::FEXP2.
2052 class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>;
2053 class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>;
2054 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
2055 class FEXP2_W_1_PSEUDO_DESC :
2056 MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws),
2057 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>;
2058 class FEXP2_D_1_PSEUDO_DESC :
2059 MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws),
2060 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>;
2063 class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w,
2064 MSA128WOpnd, MSA128HOpnd>;
2065 class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d,
2066 MSA128DOpnd, MSA128WOpnd>;
2068 class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w,
2069 MSA128WOpnd, MSA128HOpnd>;
2070 class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d,
2071 MSA128DOpnd, MSA128WOpnd>;
2073 class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>;
2074 class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>;
2076 class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>;
2077 class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>;
2079 class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w,
2080 MSA128WOpnd, MSA128HOpnd>;
2081 class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d,
2082 MSA128DOpnd, MSA128WOpnd>;
2084 class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w,
2085 MSA128WOpnd, MSA128HOpnd>;
2086 class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
2087 MSA128DOpnd, MSA128WOpnd>;
2089 class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,
2090 MSA128BOpnd, GPR32Opnd>;
2091 class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16,
2092 MSA128HOpnd, GPR32Opnd>;
2093 class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
2094 MSA128WOpnd, GPR32Opnd>;
2095 class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64,
2096 MSA128DOpnd, GPR64Opnd>;
2098 class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W,
2100 class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D,
2103 class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
2104 class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;
2106 class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>;
2107 class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>;
2109 class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>;
2110 class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>;
2112 class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w,
2114 class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d,
2117 class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>;
2118 class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>;
2120 class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w,
2122 class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d,
2125 class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", MipsFMS, MSA128WOpnd>;
2126 class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", MipsFMS, MSA128DOpnd>;
2128 class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>;
2129 class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>;
2131 class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>;
2132 class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>;
2134 class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
2135 class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
2137 class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w,
2139 class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d,
2142 class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>;
2143 class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>;
2145 class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>;
2146 class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>;
2148 class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>;
2149 class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>;
2151 class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>;
2152 class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>;
2154 class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>;
2155 class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>;
2157 class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>;
2158 class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>;
2160 class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>;
2161 class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>;
2163 class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>;
2164 class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>;
2166 class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w,
2168 class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d,
2171 class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w,
2173 class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d,
2176 class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w,
2178 class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d,
2181 class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
2183 class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
2186 class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w,
2188 class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d,
2191 class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w,
2193 class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d,
2196 class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w,
2198 class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d,
2201 class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h,
2202 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2203 class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w,
2204 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2206 class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint,
2208 class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint,
2211 class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint,
2213 class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint,
2216 class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h,
2217 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2218 class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w,
2219 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2220 class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d,
2221 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2223 class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h,
2224 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2225 class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w,
2226 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2227 class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d,
2228 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2230 class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h,
2231 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2232 class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w,
2233 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2234 class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d,
2235 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2237 class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h,
2238 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2239 class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w,
2240 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2241 class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d,
2242 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2244 class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>;
2245 class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>;
2246 class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>;
2247 class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>;
2249 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
2250 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
2251 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
2252 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
2254 class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>;
2255 class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>;
2256 class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>;
2257 class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>;
2259 class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>;
2260 class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>;
2261 class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>;
2262 class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>;
2264 class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, uimm4,
2265 immZExt4Ptr, MSA128BOpnd, GPR32Opnd>;
2266 class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, uimm3,
2267 immZExt3Ptr, MSA128HOpnd, GPR32Opnd>;
2268 class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, uimm2,
2269 immZExt2Ptr, MSA128WOpnd, GPR32Opnd>;
2270 class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, uimm1,
2271 immZExt1Ptr, MSA128DOpnd, GPR64Opnd>;
2273 class INSERT_B_VIDX_PSEUDO_DESC :
2274 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>;
2275 class INSERT_H_VIDX_PSEUDO_DESC :
2276 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>;
2277 class INSERT_W_VIDX_PSEUDO_DESC :
2278 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>;
2279 class INSERT_D_VIDX_PSEUDO_DESC :
2280 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>;
2282 class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
2284 MSA128WOpnd, FGR32Opnd>;
2285 class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
2287 MSA128DOpnd, FGR64Opnd>;
2289 class INSERT_FW_VIDX_PSEUDO_DESC :
2290 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>;
2291 class INSERT_FD_VIDX_PSEUDO_DESC :
2292 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>;
2294 class INSERT_B_VIDX64_PSEUDO_DESC :
2295 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>;
2296 class INSERT_H_VIDX64_PSEUDO_DESC :
2297 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>;
2298 class INSERT_W_VIDX64_PSEUDO_DESC :
2299 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>;
2300 class INSERT_D_VIDX64_PSEUDO_DESC :
2301 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>;
2303 class INSERT_FW_VIDX64_PSEUDO_DESC :
2304 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>;
2305 class INSERT_FD_VIDX64_PSEUDO_DESC :
2306 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>;
2308 class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, uimm4, timmZExt4,
2310 class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, uimm3, timmZExt3,
2312 class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, uimm2, timmZExt2,
2314 class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, timmZExt1,
2317 class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2318 ValueType TyNode, RegisterOperand ROWD,
2319 Operand MemOpnd, ComplexPattern Addr = addrimm10,
2320 InstrItinClass itin = NoItinerary> {
2321 dag OutOperandList = (outs ROWD:$wd);
2322 dag InOperandList = (ins MemOpnd:$addr);
2323 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2324 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))];
2325 InstrItinClass Itinerary = itin;
2326 string DecoderMethod = "DecodeMSA128Mem";
2329 class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>;
2330 class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd,
2331 mem_simm10_lsl1, addrimm10lsl1>;
2332 class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd,
2333 mem_simm10_lsl2, addrimm10lsl2>;
2334 class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd,
2335 mem_simm10_lsl3, addrimm10lsl3>;
2337 class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
2338 class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
2339 class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>;
2340 class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>;
2342 class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD,
2343 InstrItinClass itin = NoItinerary> {
2344 dag OutOperandList = (outs RORD:$rd);
2345 dag InOperandList = (ins RORD:$rs, RORD:$rt, uimm2_plus1:$sa);
2346 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa");
2347 list<dag> Pattern = [(set RORD:$rd, (add RORD:$rt,
2349 immZExt2Lsa:$sa)))];
2350 InstrItinClass Itinerary = itin;
2353 class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd, II_LSA>;
2354 class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd, II_DLSA>;
2356 class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
2358 class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w,
2361 class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h,
2363 class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w,
2366 class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>;
2367 class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>;
2368 class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>;
2369 class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>;
2371 class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>;
2372 class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>;
2373 class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>;
2374 class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>;
2376 class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", smax, MSA128BOpnd>;
2377 class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", smax, MSA128HOpnd>;
2378 class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", smax, MSA128WOpnd>;
2379 class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", smax, MSA128DOpnd>;
2381 class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", umax, MSA128BOpnd>;
2382 class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", umax, MSA128HOpnd>;
2383 class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", umax, MSA128WOpnd>;
2384 class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", umax, MSA128DOpnd>;
2386 class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", smax, vsplati8_simm5,
2388 class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", smax, vsplati16_simm5,
2390 class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", smax, vsplati32_simm5,
2392 class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", smax, vsplati64_simm5,
2395 class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", umax, vsplati8_uimm5,
2397 class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", umax, vsplati16_uimm5,
2399 class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", umax, vsplati32_uimm5,
2401 class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", umax, vsplati64_uimm5,
2404 class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>;
2405 class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>;
2406 class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>;
2407 class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>;
2409 class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", smin, MSA128BOpnd>;
2410 class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", smin, MSA128HOpnd>;
2411 class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", smin, MSA128WOpnd>;
2412 class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", smin, MSA128DOpnd>;
2414 class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", umin, MSA128BOpnd>;
2415 class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", umin, MSA128HOpnd>;
2416 class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", umin, MSA128WOpnd>;
2417 class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", umin, MSA128DOpnd>;
2419 class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", smin, vsplati8_simm5,
2421 class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", smin, vsplati16_simm5,
2423 class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", smin, vsplati32_simm5,
2425 class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", smin, vsplati64_simm5,
2428 class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", umin, vsplati8_uimm5,
2430 class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", umin, vsplati16_uimm5,
2432 class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", umin, vsplati32_uimm5,
2434 class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", umin, vsplati64_uimm5,
2437 class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>;
2438 class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>;
2439 class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>;
2440 class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>;
2442 class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>;
2443 class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>;
2444 class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>;
2445 class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>;
2448 dag OutOperandList = (outs MSA128BOpnd:$wd);
2449 dag InOperandList = (ins MSA128BOpnd:$ws);
2450 string AsmString = "move.v\t$wd, $ws";
2451 list<dag> Pattern = [];
2452 InstrItinClass Itinerary = NoItinerary;
2456 class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h,
2458 class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w,
2461 class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h,
2463 class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w,
2466 class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>;
2467 class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>;
2468 class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>;
2469 class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>;
2471 class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h,
2473 class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w,
2476 class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h,
2478 class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w,
2481 class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>;
2482 class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>;
2483 class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>;
2484 class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>;
2486 class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
2487 class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
2488 class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
2489 class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
2491 class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>;
2492 class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>;
2493 class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>;
2494 class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>;
2496 class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>;
2497 class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>;
2498 class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>;
2499 class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>;
2501 class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8,
2504 class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>;
2505 class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>;
2506 class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>;
2507 class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>;
2509 class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>;
2511 class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>;
2512 class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>;
2513 class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>;
2514 class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>;
2516 class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>;
2517 class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>;
2518 class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>;
2519 class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>;
2521 class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>;
2522 class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>;
2523 class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
2524 class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
2526 class SAT_S_B_DESC : MSA_BIT_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, uimm3,
2527 timmZExt3, MSA128BOpnd>;
2528 class SAT_S_H_DESC : MSA_BIT_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, uimm4,
2529 timmZExt4, MSA128HOpnd>;
2530 class SAT_S_W_DESC : MSA_BIT_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, uimm5,
2531 timmZExt5, MSA128WOpnd>;
2532 class SAT_S_D_DESC : MSA_BIT_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, uimm6,
2533 timmZExt6, MSA128DOpnd>;
2535 class SAT_U_B_DESC : MSA_BIT_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, uimm3,
2536 timmZExt3, MSA128BOpnd>;
2537 class SAT_U_H_DESC : MSA_BIT_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, uimm4,
2538 timmZExt4, MSA128HOpnd>;
2539 class SAT_U_W_DESC : MSA_BIT_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, uimm5,
2540 timmZExt5, MSA128WOpnd>;
2541 class SAT_U_D_DESC : MSA_BIT_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, uimm6,
2542 timmZExt6, MSA128DOpnd>;
2544 class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
2545 class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
2546 class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
2548 class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
2549 class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
2550 class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>;
2551 class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>;
2553 class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b,
2554 MSA128BOpnd, MSA128BOpnd, uimm4,
2556 class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h,
2557 MSA128HOpnd, MSA128HOpnd, uimm3,
2559 class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w,
2560 MSA128WOpnd, MSA128WOpnd, uimm2,
2562 class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d,
2563 MSA128DOpnd, MSA128DOpnd, uimm1,
2566 class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>;
2567 class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>;
2568 class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>;
2569 class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>;
2571 class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3,
2573 class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4,
2575 class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5,
2577 class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6,
2580 class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt,
2582 class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt,
2584 class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt,
2586 class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt,
2589 class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4,
2591 class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3,
2593 class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2,
2595 class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1,
2598 class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>;
2599 class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>;
2600 class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>;
2601 class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
2603 class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
2605 class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
2607 class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
2609 class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
2612 class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
2613 class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
2614 class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
2615 class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
2617 class SRARI_B_DESC : MSA_BIT_X_DESC_BASE<"srari.b", int_mips_srari_b, uimm3,
2618 timmZExt3, MSA128BOpnd>;
2619 class SRARI_H_DESC : MSA_BIT_X_DESC_BASE<"srari.h", int_mips_srari_h, uimm4,
2620 timmZExt4, MSA128HOpnd>;
2621 class SRARI_W_DESC : MSA_BIT_X_DESC_BASE<"srari.w", int_mips_srari_w, uimm5,
2622 timmZExt5, MSA128WOpnd>;
2623 class SRARI_D_DESC : MSA_BIT_X_DESC_BASE<"srari.d", int_mips_srari_d, uimm6,
2624 timmZExt6, MSA128DOpnd>;
2626 class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
2627 class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
2628 class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>;
2629 class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
2631 class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
2633 class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
2635 class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
2637 class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
2640 class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
2641 class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
2642 class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
2643 class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
2645 class SRLRI_B_DESC : MSA_BIT_X_DESC_BASE<"srlri.b", int_mips_srlri_b, uimm3,
2646 timmZExt3, MSA128BOpnd>;
2647 class SRLRI_H_DESC : MSA_BIT_X_DESC_BASE<"srlri.h", int_mips_srlri_h, uimm4,
2648 timmZExt4, MSA128HOpnd>;
2649 class SRLRI_W_DESC : MSA_BIT_X_DESC_BASE<"srlri.w", int_mips_srlri_w, uimm5,
2650 timmZExt5, MSA128WOpnd>;
2651 class SRLRI_D_DESC : MSA_BIT_X_DESC_BASE<"srlri.d", int_mips_srlri_d, uimm6,
2652 timmZExt6, MSA128DOpnd>;
2654 class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2655 ValueType TyNode, RegisterOperand ROWD,
2656 Operand MemOpnd, ComplexPattern Addr = addrimm10,
2657 InstrItinClass itin = NoItinerary> {
2658 dag OutOperandList = (outs);
2659 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
2660 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2661 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
2662 InstrItinClass Itinerary = itin;
2663 string DecoderMethod = "DecodeMSA128Mem";
2666 class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd, mem_simm10>;
2667 class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd,
2668 mem_simm10_lsl1, addrimm10lsl1>;
2669 class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd,
2670 mem_simm10_lsl2, addrimm10lsl2>;
2671 class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd,
2672 mem_simm10_lsl3, addrimm10lsl3>;
2674 class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
2676 class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h,
2678 class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w,
2680 class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d,
2683 class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b,
2685 class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h,
2687 class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w,
2689 class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d,
2692 class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b,
2694 class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h,
2696 class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w,
2698 class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d,
2701 class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b,
2703 class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h,
2705 class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w,
2707 class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d,
2710 class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>;
2711 class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>;
2712 class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>;
2713 class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>;
2715 class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5,
2717 class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5,
2719 class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5,
2721 class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5,
2724 class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>;
2725 class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>;
2726 class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>;
2727 class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>;
2729 class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>;
2730 class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>;
2731 class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>;
2732 class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>;
2734 class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8,
2737 // Instruction defs.
2738 def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC;
2739 def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC;
2740 def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC;
2741 def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC;
2743 def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC;
2744 def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC;
2745 def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC;
2746 def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC;
2748 def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC;
2749 def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC;
2750 def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC;
2751 def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC;
2753 def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC;
2754 def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC;
2755 def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC;
2756 def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC;
2758 def ADDV_B : ADDV_B_ENC, ADDV_B_DESC;
2759 def ADDV_H : ADDV_H_ENC, ADDV_H_DESC;
2760 def ADDV_W : ADDV_W_ENC, ADDV_W_DESC;
2761 def ADDV_D : ADDV_D_ENC, ADDV_D_DESC;
2763 def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC;
2764 def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;
2765 def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
2766 def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC;
2768 def AND_V : AND_V_ENC, AND_V_DESC;
2769 def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC,
2770 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2773 def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC,
2774 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2777 def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC,
2778 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2782 def ANDI_B : ANDI_B_ENC, ANDI_B_DESC;
2784 def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC;
2785 def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC;
2786 def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC;
2787 def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC;
2789 def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC;
2790 def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC;
2791 def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC;
2792 def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC;
2794 def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC;
2795 def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC;
2796 def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC;
2797 def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC;
2799 def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC;
2800 def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC;
2801 def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC;
2802 def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC;
2804 def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC;
2805 def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC;
2806 def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC;
2807 def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC;
2809 def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC;
2810 def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC;
2811 def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC;
2812 def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC;
2814 def BCLR_B : BCLR_B_ENC, BCLR_B_DESC;
2815 def BCLR_H : BCLR_H_ENC, BCLR_H_DESC;
2816 def BCLR_W : BCLR_W_ENC, BCLR_W_DESC;
2817 def BCLR_D : BCLR_D_ENC, BCLR_D_DESC;
2819 def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC;
2820 def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC;
2821 def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC;
2822 def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC;
2824 def BINSL_B : BINSL_B_ENC, BINSL_B_DESC;
2825 def BINSL_H : BINSL_H_ENC, BINSL_H_DESC;
2826 def BINSL_W : BINSL_W_ENC, BINSL_W_DESC;
2827 def BINSL_D : BINSL_D_ENC, BINSL_D_DESC;
2829 def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC;
2830 def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC;
2831 def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC;
2832 def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC;
2834 def BINSR_B : BINSR_B_ENC, BINSR_B_DESC;
2835 def BINSR_H : BINSR_H_ENC, BINSR_H_DESC;
2836 def BINSR_W : BINSR_W_ENC, BINSR_W_DESC;
2837 def BINSR_D : BINSR_D_ENC, BINSR_D_DESC;
2839 def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC;
2840 def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC;
2841 def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC;
2842 def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC;
2844 def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC;
2846 def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC;
2848 def BMZ_V : BMZ_V_ENC, BMZ_V_DESC;
2850 def BMZI_B : BMZI_B_ENC, BMZI_B_DESC;
2852 def BNEG_B : BNEG_B_ENC, BNEG_B_DESC;
2853 def BNEG_H : BNEG_H_ENC, BNEG_H_DESC;
2854 def BNEG_W : BNEG_W_ENC, BNEG_W_DESC;
2855 def BNEG_D : BNEG_D_ENC, BNEG_D_DESC;
2857 def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC;
2858 def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC;
2859 def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC;
2860 def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC;
2862 def BNZ_B : BNZ_B_ENC, BNZ_B_DESC;
2863 def BNZ_H : BNZ_H_ENC, BNZ_H_DESC;
2864 def BNZ_W : BNZ_W_ENC, BNZ_W_DESC;
2865 def BNZ_D : BNZ_D_ENC, BNZ_D_DESC;
2867 def BNZ_V : BNZ_V_ENC, BNZ_V_DESC;
2869 def BSEL_V : BSEL_V_ENC, BSEL_V_DESC;
2871 class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> :
2872 MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt),
2873 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>,
2874 // Note that vselect and BSEL_V treat the condition operand the opposite way
2876 // (vselect cond, if_set, if_clear)
2877 // (BSEL_V cond, if_clear, if_set)
2878 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in,
2879 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> {
2880 let Constraints = "$wd_in = $wd";
2883 def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>;
2884 def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>;
2885 def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>;
2886 def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>;
2887 def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>;
2889 def BSELI_B : BSELI_B_ENC, BSELI_B_DESC;
2891 def BSET_B : BSET_B_ENC, BSET_B_DESC;
2892 def BSET_H : BSET_H_ENC, BSET_H_DESC;
2893 def BSET_W : BSET_W_ENC, BSET_W_DESC;
2894 def BSET_D : BSET_D_ENC, BSET_D_DESC;
2896 def BSETI_B : BSETI_B_ENC, BSETI_B_DESC;
2897 def BSETI_H : BSETI_H_ENC, BSETI_H_DESC;
2898 def BSETI_W : BSETI_W_ENC, BSETI_W_DESC;
2899 def BSETI_D : BSETI_D_ENC, BSETI_D_DESC;
2901 def BZ_B : BZ_B_ENC, BZ_B_DESC;
2902 def BZ_H : BZ_H_ENC, BZ_H_DESC;
2903 def BZ_W : BZ_W_ENC, BZ_W_DESC;
2904 def BZ_D : BZ_D_ENC, BZ_D_DESC;
2906 def BZ_V : BZ_V_ENC, BZ_V_DESC;
2908 def CEQ_B : CEQ_B_ENC, CEQ_B_DESC;
2909 def CEQ_H : CEQ_H_ENC, CEQ_H_DESC;
2910 def CEQ_W : CEQ_W_ENC, CEQ_W_DESC;
2911 def CEQ_D : CEQ_D_ENC, CEQ_D_DESC;
2913 def CEQI_B : CEQI_B_ENC, CEQI_B_DESC;
2914 def CEQI_H : CEQI_H_ENC, CEQI_H_DESC;
2915 def CEQI_W : CEQI_W_ENC, CEQI_W_DESC;
2916 def CEQI_D : CEQI_D_ENC, CEQI_D_DESC;
2918 def CFCMSA : CFCMSA_ENC, CFCMSA_DESC;
2920 def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC;
2921 def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC;
2922 def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC;
2923 def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC;
2925 def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC;
2926 def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC;
2927 def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC;
2928 def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC;
2930 def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC;
2931 def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC;
2932 def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC;
2933 def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC;
2935 def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC;
2936 def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC;
2937 def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC;
2938 def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC;
2940 def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC;
2941 def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC;
2942 def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC;
2943 def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC;
2945 def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC;
2946 def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC;
2947 def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC;
2948 def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC;
2950 def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC;
2951 def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC;
2952 def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC;
2953 def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC;
2955 def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC;
2956 def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC;
2957 def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC;
2958 def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
2960 def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
2961 def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
2962 def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
2963 def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64;
2965 def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
2966 def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
2967 def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC, ASE_MSA64;
2969 def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
2970 def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
2972 def CTCMSA : CTCMSA_ENC, CTCMSA_DESC;
2974 def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC;
2975 def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC;
2976 def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC;
2977 def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC;
2979 def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC;
2980 def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC;
2981 def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC;
2982 def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC;
2984 def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC;
2985 def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC;
2986 def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC;
2988 def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC;
2989 def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC;
2990 def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC;
2992 def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC;
2993 def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC;
2994 def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC;
2996 def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC;
2997 def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC;
2998 def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC;
3000 def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC;
3001 def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC;
3002 def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC;
3004 def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC;
3005 def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC;
3006 def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC;
3008 def FADD_W : FADD_W_ENC, FADD_W_DESC;
3009 def FADD_D : FADD_D_ENC, FADD_D_DESC;
3011 def FCAF_W : FCAF_W_ENC, FCAF_W_DESC;
3012 def FCAF_D : FCAF_D_ENC, FCAF_D_DESC;
3014 def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC;
3015 def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC;
3017 def FCLE_W : FCLE_W_ENC, FCLE_W_DESC;
3018 def FCLE_D : FCLE_D_ENC, FCLE_D_DESC;
3020 def FCLT_W : FCLT_W_ENC, FCLT_W_DESC;
3021 def FCLT_D : FCLT_D_ENC, FCLT_D_DESC;
3023 def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC;
3024 def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC;
3026 def FCNE_W : FCNE_W_ENC, FCNE_W_DESC;
3027 def FCNE_D : FCNE_D_ENC, FCNE_D_DESC;
3029 def FCOR_W : FCOR_W_ENC, FCOR_W_DESC;
3030 def FCOR_D : FCOR_D_ENC, FCOR_D_DESC;
3032 def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC;
3033 def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC;
3035 def FCULE_W : FCULE_W_ENC, FCULE_W_DESC;
3036 def FCULE_D : FCULE_D_ENC, FCULE_D_DESC;
3038 def FCULT_W : FCULT_W_ENC, FCULT_W_DESC;
3039 def FCULT_D : FCULT_D_ENC, FCULT_D_DESC;
3041 def FCUN_W : FCUN_W_ENC, FCUN_W_DESC;
3042 def FCUN_D : FCUN_D_ENC, FCUN_D_DESC;
3044 def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC;
3045 def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC;
3047 def FDIV_W : FDIV_W_ENC, FDIV_W_DESC;
3048 def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;
3050 def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC;
3051 def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC;
3053 def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC;
3054 def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC;
3055 def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC;
3056 def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC;
3058 def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC;
3059 def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC;
3061 def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC;
3062 def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC;
3064 def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC;
3065 def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC;
3067 def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC;
3068 def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC;
3070 def FFQL_W : FFQL_W_ENC, FFQL_W_DESC;
3071 def FFQL_D : FFQL_D_ENC, FFQL_D_DESC;
3073 def FFQR_W : FFQR_W_ENC, FFQR_W_DESC;
3074 def FFQR_D : FFQR_D_ENC, FFQR_D_DESC;
3076 def FILL_B : FILL_B_ENC, FILL_B_DESC;
3077 def FILL_H : FILL_H_ENC, FILL_H_DESC;
3078 def FILL_W : FILL_W_ENC, FILL_W_DESC;
3079 def FILL_D : FILL_D_ENC, FILL_D_DESC, ASE_MSA64;
3080 def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC;
3081 def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC;
3083 def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC;
3084 def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC;
3086 def FMADD_W : FMADD_W_ENC, FMADD_W_DESC;
3087 def FMADD_D : FMADD_D_ENC, FMADD_D_DESC;
3089 def FMAX_W : FMAX_W_ENC, FMAX_W_DESC;
3090 def FMAX_D : FMAX_D_ENC, FMAX_D_DESC;
3092 def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC;
3093 def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC;
3095 def FMIN_W : FMIN_W_ENC, FMIN_W_DESC;
3096 def FMIN_D : FMIN_D_ENC, FMIN_D_DESC;
3098 def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC;
3099 def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC;
3101 def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC;
3102 def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC;
3104 def FMUL_W : FMUL_W_ENC, FMUL_W_DESC;
3105 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
3107 def FRINT_W : FRINT_W_ENC, FRINT_W_DESC;
3108 def FRINT_D : FRINT_D_ENC, FRINT_D_DESC;
3110 def FRCP_W : FRCP_W_ENC, FRCP_W_DESC;
3111 def FRCP_D : FRCP_D_ENC, FRCP_D_DESC;
3113 def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC;
3114 def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC;
3116 def FSAF_W : FSAF_W_ENC, FSAF_W_DESC;
3117 def FSAF_D : FSAF_D_ENC, FSAF_D_DESC;
3119 def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC;
3120 def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC;
3122 def FSLE_W : FSLE_W_ENC, FSLE_W_DESC;
3123 def FSLE_D : FSLE_D_ENC, FSLE_D_DESC;
3125 def FSLT_W : FSLT_W_ENC, FSLT_W_DESC;
3126 def FSLT_D : FSLT_D_ENC, FSLT_D_DESC;
3128 def FSNE_W : FSNE_W_ENC, FSNE_W_DESC;
3129 def FSNE_D : FSNE_D_ENC, FSNE_D_DESC;
3131 def FSOR_W : FSOR_W_ENC, FSOR_W_DESC;
3132 def FSOR_D : FSOR_D_ENC, FSOR_D_DESC;
3134 def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC;
3135 def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC;
3137 def FSUB_W : FSUB_W_ENC, FSUB_W_DESC;
3138 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
3140 def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC;
3141 def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC;
3143 def FSULE_W : FSULE_W_ENC, FSULE_W_DESC;
3144 def FSULE_D : FSULE_D_ENC, FSULE_D_DESC;
3146 def FSULT_W : FSULT_W_ENC, FSULT_W_DESC;
3147 def FSULT_D : FSULT_D_ENC, FSULT_D_DESC;
3149 def FSUN_W : FSUN_W_ENC, FSUN_W_DESC;
3150 def FSUN_D : FSUN_D_ENC, FSUN_D_DESC;
3152 def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC;
3153 def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC;
3155 def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC;
3156 def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC;
3158 def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC;
3159 def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC;
3161 def FTQ_H : FTQ_H_ENC, FTQ_H_DESC;
3162 def FTQ_W : FTQ_W_ENC, FTQ_W_DESC;
3164 def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC;
3165 def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC;
3167 def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC;
3168 def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC;
3170 def : MipsPat<(fsub MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)),
3171 (FMSUB_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>,
3172 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST;
3173 def : MipsPat<(fsub MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)),
3174 (FMSUB_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>,
3175 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST;
3177 def : MipsPat<(fadd MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)),
3178 (FMADD_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>,
3179 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST;
3180 def : MipsPat<(fadd MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)),
3181 (FMADD_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>,
3182 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST;
3184 def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC;
3185 def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC;
3186 def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC;
3188 def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC;
3189 def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC;
3190 def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC;
3192 def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC;
3193 def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC;
3194 def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC;
3196 def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC;
3197 def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC;
3198 def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC;
3200 def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC;
3201 def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC;
3202 def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC;
3203 def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC;
3205 def ILVL_B : ILVL_B_ENC, ILVL_B_DESC;
3206 def ILVL_H : ILVL_H_ENC, ILVL_H_DESC;
3207 def ILVL_W : ILVL_W_ENC, ILVL_W_DESC;
3208 def ILVL_D : ILVL_D_ENC, ILVL_D_DESC;
3210 def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC;
3211 def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC;
3212 def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC;
3213 def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC;
3215 def ILVR_B : ILVR_B_ENC, ILVR_B_DESC;
3216 def ILVR_H : ILVR_H_ENC, ILVR_H_DESC;
3217 def ILVR_W : ILVR_W_ENC, ILVR_W_DESC;
3218 def ILVR_D : ILVR_D_ENC, ILVR_D_DESC;
3220 def INSERT_B : INSERT_B_ENC, INSERT_B_DESC;
3221 def INSERT_H : INSERT_H_ENC, INSERT_H_DESC;
3222 def INSERT_W : INSERT_W_ENC, INSERT_W_DESC;
3223 def INSERT_D : INSERT_D_ENC, INSERT_D_DESC, ASE_MSA64;
3225 // INSERT_FW_PSEUDO defined after INSVE_W
3226 // INSERT_FD_PSEUDO defined after INSVE_D
3228 // There is a fourth operand that is not present in the encoding. Use a
3229 // custom decoder to get a chance to add it.
3230 let DecoderMethod = "DecodeINSVE_DF" in {
3231 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;
3232 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC;
3233 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC;
3234 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC;
3237 def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
3238 def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;
3240 def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC;
3241 def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC;
3242 def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC;
3243 def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC;
3244 def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC;
3245 def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC;
3247 def INSERT_B_VIDX64_PSEUDO : INSERT_B_VIDX64_PSEUDO_DESC;
3248 def INSERT_H_VIDX64_PSEUDO : INSERT_H_VIDX64_PSEUDO_DESC;
3249 def INSERT_W_VIDX64_PSEUDO : INSERT_W_VIDX64_PSEUDO_DESC;
3250 def INSERT_D_VIDX64_PSEUDO : INSERT_D_VIDX64_PSEUDO_DESC;
3251 def INSERT_FW_VIDX64_PSEUDO : INSERT_FW_VIDX64_PSEUDO_DESC;
3252 def INSERT_FD_VIDX64_PSEUDO : INSERT_FD_VIDX64_PSEUDO_DESC;
3254 def LD_B: LD_B_ENC, LD_B_DESC;
3255 def LD_H: LD_H_ENC, LD_H_DESC;
3256 def LD_W: LD_W_ENC, LD_W_DESC;
3257 def LD_D: LD_D_ENC, LD_D_DESC;
3259 def LDI_B : LDI_B_ENC, LDI_B_DESC;
3260 def LDI_H : LDI_H_ENC, LDI_H_DESC;
3261 def LDI_W : LDI_W_ENC, LDI_W_DESC;
3262 def LDI_D : LDI_D_ENC, LDI_D_DESC;
3264 def LSA : LSA_ENC, LSA_DESC;
3265 def DLSA : DLSA_ENC, DLSA_DESC, ASE_MSA64;
3267 def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
3268 def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;
3270 def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC;
3271 def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC;
3273 def MADDV_B : MADDV_B_ENC, MADDV_B_DESC;
3274 def MADDV_H : MADDV_H_ENC, MADDV_H_DESC;
3275 def MADDV_W : MADDV_W_ENC, MADDV_W_DESC;
3276 def MADDV_D : MADDV_D_ENC, MADDV_D_DESC;
3278 def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC;
3279 def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC;
3280 def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC;
3281 def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC;
3283 def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC;
3284 def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC;
3285 def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC;
3286 def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC;
3288 def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC;
3289 def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC;
3290 def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC;
3291 def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC;
3293 def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC;
3294 def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC;
3295 def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC;
3296 def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC;
3298 def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC;
3299 def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC;
3300 def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC;
3301 def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC;
3303 def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC;
3304 def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC;
3305 def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC;
3306 def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC;
3308 def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC;
3309 def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC;
3310 def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC;
3311 def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC;
3313 def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC;
3314 def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC;
3315 def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC;
3316 def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC;
3318 def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC;
3319 def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC;
3320 def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC;
3321 def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC;
3323 def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC;
3324 def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC;
3325 def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC;
3326 def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC;
3328 def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC;
3329 def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC;
3330 def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC;
3331 def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC;
3333 def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC;
3334 def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC;
3335 def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC;
3336 def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC;
3338 def MOVE_V : MOVE_V_ENC, MOVE_V_DESC;
3340 def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC;
3341 def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC;
3343 def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC;
3344 def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC;
3346 def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC;
3347 def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC;
3348 def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC;
3349 def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC;
3351 def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC;
3352 def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC;
3354 def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC;
3355 def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC;
3357 def MULV_B : MULV_B_ENC, MULV_B_DESC;
3358 def MULV_H : MULV_H_ENC, MULV_H_DESC;
3359 def MULV_W : MULV_W_ENC, MULV_W_DESC;
3360 def MULV_D : MULV_D_ENC, MULV_D_DESC;
3362 def NLOC_B : NLOC_B_ENC, NLOC_B_DESC;
3363 def NLOC_H : NLOC_H_ENC, NLOC_H_DESC;
3364 def NLOC_W : NLOC_W_ENC, NLOC_W_DESC;
3365 def NLOC_D : NLOC_D_ENC, NLOC_D_DESC;
3367 def NLZC_B : NLZC_B_ENC, NLZC_B_DESC;
3368 def NLZC_H : NLZC_H_ENC, NLZC_H_DESC;
3369 def NLZC_W : NLZC_W_ENC, NLZC_W_DESC;
3370 def NLZC_D : NLZC_D_ENC, NLZC_D_DESC;
3372 def NOR_V : NOR_V_ENC, NOR_V_DESC;
3373 def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC,
3374 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3377 def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC,
3378 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3381 def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC,
3382 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3386 def NORI_B : NORI_B_ENC, NORI_B_DESC;
3388 def OR_V : OR_V_ENC, OR_V_DESC;
3389 def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC,
3390 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3393 def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC,
3394 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3397 def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC,
3398 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3402 def ORI_B : ORI_B_ENC, ORI_B_DESC;
3404 def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC;
3405 def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC;
3406 def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC;
3407 def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC;
3409 def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC;
3410 def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC;
3411 def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC;
3412 def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC;
3414 def PCNT_B : PCNT_B_ENC, PCNT_B_DESC;
3415 def PCNT_H : PCNT_H_ENC, PCNT_H_DESC;
3416 def PCNT_W : PCNT_W_ENC, PCNT_W_DESC;
3417 def PCNT_D : PCNT_D_ENC, PCNT_D_DESC;
3419 def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC;
3420 def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC;
3421 def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC;
3422 def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC;
3424 def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC;
3425 def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC;
3426 def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC;
3427 def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC;
3429 def SHF_B : SHF_B_ENC, SHF_B_DESC;
3430 def SHF_H : SHF_H_ENC, SHF_H_DESC;
3431 def SHF_W : SHF_W_ENC, SHF_W_DESC;
3433 def SLD_B : SLD_B_ENC, SLD_B_DESC;
3434 def SLD_H : SLD_H_ENC, SLD_H_DESC;
3435 def SLD_W : SLD_W_ENC, SLD_W_DESC;
3436 def SLD_D : SLD_D_ENC, SLD_D_DESC;
3438 def SLDI_B : SLDI_B_ENC, SLDI_B_DESC;
3439 def SLDI_H : SLDI_H_ENC, SLDI_H_DESC;
3440 def SLDI_W : SLDI_W_ENC, SLDI_W_DESC;
3441 def SLDI_D : SLDI_D_ENC, SLDI_D_DESC;
3443 def SLL_B : SLL_B_ENC, SLL_B_DESC;
3444 def SLL_H : SLL_H_ENC, SLL_H_DESC;
3445 def SLL_W : SLL_W_ENC, SLL_W_DESC;
3446 def SLL_D : SLL_D_ENC, SLL_D_DESC;
3448 def SLLI_B : SLLI_B_ENC, SLLI_B_DESC;
3449 def SLLI_H : SLLI_H_ENC, SLLI_H_DESC;
3450 def SLLI_W : SLLI_W_ENC, SLLI_W_DESC;
3451 def SLLI_D : SLLI_D_ENC, SLLI_D_DESC;
3453 def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC;
3454 def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC;
3455 def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC;
3456 def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC;
3458 def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC;
3459 def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC;
3460 def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC;
3461 def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC;
3463 def SRA_B : SRA_B_ENC, SRA_B_DESC;
3464 def SRA_H : SRA_H_ENC, SRA_H_DESC;
3465 def SRA_W : SRA_W_ENC, SRA_W_DESC;
3466 def SRA_D : SRA_D_ENC, SRA_D_DESC;
3468 def SRAI_B : SRAI_B_ENC, SRAI_B_DESC;
3469 def SRAI_H : SRAI_H_ENC, SRAI_H_DESC;
3470 def SRAI_W : SRAI_W_ENC, SRAI_W_DESC;
3471 def SRAI_D : SRAI_D_ENC, SRAI_D_DESC;
3473 def SRAR_B : SRAR_B_ENC, SRAR_B_DESC;
3474 def SRAR_H : SRAR_H_ENC, SRAR_H_DESC;
3475 def SRAR_W : SRAR_W_ENC, SRAR_W_DESC;
3476 def SRAR_D : SRAR_D_ENC, SRAR_D_DESC;
3478 def SRARI_B : SRARI_B_ENC, SRARI_B_DESC;
3479 def SRARI_H : SRARI_H_ENC, SRARI_H_DESC;
3480 def SRARI_W : SRARI_W_ENC, SRARI_W_DESC;
3481 def SRARI_D : SRARI_D_ENC, SRARI_D_DESC;
3483 def SRL_B : SRL_B_ENC, SRL_B_DESC;
3484 def SRL_H : SRL_H_ENC, SRL_H_DESC;
3485 def SRL_W : SRL_W_ENC, SRL_W_DESC;
3486 def SRL_D : SRL_D_ENC, SRL_D_DESC;
3488 def SRLI_B : SRLI_B_ENC, SRLI_B_DESC;
3489 def SRLI_H : SRLI_H_ENC, SRLI_H_DESC;
3490 def SRLI_W : SRLI_W_ENC, SRLI_W_DESC;
3491 def SRLI_D : SRLI_D_ENC, SRLI_D_DESC;
3493 def SRLR_B : SRLR_B_ENC, SRLR_B_DESC;
3494 def SRLR_H : SRLR_H_ENC, SRLR_H_DESC;
3495 def SRLR_W : SRLR_W_ENC, SRLR_W_DESC;
3496 def SRLR_D : SRLR_D_ENC, SRLR_D_DESC;
3498 def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC;
3499 def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC;
3500 def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC;
3501 def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC;
3503 def ST_B: ST_B_ENC, ST_B_DESC;
3504 def ST_H: ST_H_ENC, ST_H_DESC;
3505 def ST_W: ST_W_ENC, ST_W_DESC;
3506 def ST_D: ST_D_ENC, ST_D_DESC;
3508 def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC;
3509 def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC;
3510 def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC;
3511 def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC;
3513 def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC;
3514 def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC;
3515 def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC;
3516 def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC;
3518 def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC;
3519 def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC;
3520 def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC;
3521 def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC;
3523 def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC;
3524 def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC;
3525 def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC;
3526 def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC;
3528 def SUBV_B : SUBV_B_ENC, SUBV_B_DESC;
3529 def SUBV_H : SUBV_H_ENC, SUBV_H_DESC;
3530 def SUBV_W : SUBV_W_ENC, SUBV_W_DESC;
3531 def SUBV_D : SUBV_D_ENC, SUBV_D_DESC;
3533 def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC;
3534 def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC;
3535 def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC;
3536 def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC;
3538 def VSHF_B : VSHF_B_ENC, VSHF_B_DESC;
3539 def VSHF_H : VSHF_H_ENC, VSHF_H_DESC;
3540 def VSHF_W : VSHF_W_ENC, VSHF_W_DESC;
3541 def VSHF_D : VSHF_D_ENC, VSHF_D_DESC;
3543 def XOR_V : XOR_V_ENC, XOR_V_DESC;
3544 def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC,
3545 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3548 def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC,
3549 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3552 def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC,
3553 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3557 def XORI_B : XORI_B_ENC, XORI_B_DESC;
3560 class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
3561 Pat<pattern, result>, Requires<pred>;
3563 def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
3564 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
3566 def : MSAPat<(v8f16 (load addrimm10lsl1:$addr)), (LD_H addrimm10lsl1:$addr)>;
3567 def : MSAPat<(v4f32 (load addrimm10lsl2:$addr)), (LD_W addrimm10lsl2:$addr)>;
3568 def : MSAPat<(v2f64 (load addrimm10lsl3:$addr)), (LD_D addrimm10lsl3:$addr)>;
3570 def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10lsl1:$addr),
3571 (ST_H MSA128H:$ws, addrimm10lsl1:$addr)>;
3572 def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10lsl2:$addr),
3573 (ST_W MSA128W:$ws, addrimm10lsl2:$addr)>;
3574 def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10lsl3:$addr),
3575 (ST_D MSA128D:$ws, addrimm10lsl3:$addr)>;
3577 class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
3578 RegisterOperand ROWS = ROWD,
3579 InstrItinClass itin = NoItinerary> :
3580 MSAPseudo<(outs ROWD:$wd),
3582 [(set ROWD:$wd, (fabs ROWS:$ws))]> {
3583 InstrItinClass Itinerary = itin;
3585 def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>,
3586 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws,
3588 def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>,
3589 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws,
3592 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3593 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
3594 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3595 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3597 // These are endian-independent because the element size doesnt change
3598 def : MSABitconvertPat<v8i16, v8f16, MSA128H>;
3599 def : MSABitconvertPat<v4i32, v4f32, MSA128W>;
3600 def : MSABitconvertPat<v2i64, v2f64, MSA128D>;
3601 def : MSABitconvertPat<v8f16, v8i16, MSA128H>;
3602 def : MSABitconvertPat<v4f32, v4i32, MSA128W>;
3603 def : MSABitconvertPat<v2f64, v2i64, MSA128D>;
3605 // Little endian bitcasts are always no-ops
3606 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3607 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3608 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3609 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3610 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3611 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3613 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3614 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3615 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3616 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
3617 def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>;
3619 def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>;
3620 def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>;
3621 def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>;
3622 def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>;
3623 def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>;
3625 def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>;
3626 def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>;
3627 def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>;
3628 def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>;
3629 def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>;
3631 def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>;
3632 def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>;
3633 def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>;
3634 def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>;
3635 def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>;
3637 def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>;
3638 def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>;
3639 def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>;
3640 def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>;
3641 def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>;
3643 // Big endian bitcasts expand to shuffle instructions.
3644 // This is because bitcast is defined to be a store/load sequence and the
3645 // vector store/load instructions are mixed-endian with respect to the vector
3646 // as a whole (little endian with respect to element order, but big endian
3649 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3650 RegisterClass DstRC, MSAInst Insn,
3651 RegisterClass ViaRC> :
3652 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3653 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3657 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3658 RegisterClass DstRC, MSAInst Insn,
3659 RegisterClass ViaRC> :
3660 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3661 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3665 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3666 RegisterClass DstRC> :
3667 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3669 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3670 RegisterClass DstRC> :
3671 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3673 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3674 RegisterClass DstRC> :
3675 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3679 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3684 class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
3685 RegisterClass DstRC> :
3686 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3688 class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
3689 RegisterClass DstRC> :
3690 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3692 class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT,
3693 RegisterClass DstRC> :
3694 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>;
3696 def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>;
3697 def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>;
3698 def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>;
3699 def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>;
3700 def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>;
3701 def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>;
3703 def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>;
3704 def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>;
3705 def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>;
3706 def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>;
3707 def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>;
3709 def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>;
3710 def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>;
3711 def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>;
3712 def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>;
3713 def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>;
3715 def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>;
3716 def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>;
3717 def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>;
3718 def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>;
3719 def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>;
3721 def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>;
3722 def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>;
3723 def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>;
3724 def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>;
3725 def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>;
3727 def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>;
3728 def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>;
3729 def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>;
3730 def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>;
3731 def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>;
3733 def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>;
3734 def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>;
3735 def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>;
3736 def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>;
3737 def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>;
3739 // Pseudos used to implement BNZ.df, and BZ.df
3741 class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode,
3743 InstrItinClass itin = NoItinerary> :
3744 MipsPseudo<(outs GPR32:$dst),
3746 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
3747 bit usesCustomInserter = 1;
3748 bit hasNoSchedulingInfo = 1;
3751 def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8,
3752 MSA128B, NoItinerary>;
3753 def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16,
3754 MSA128H, NoItinerary>;
3755 def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32,
3756 MSA128W, NoItinerary>;
3757 def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64,
3758 MSA128D, NoItinerary>;
3759 def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8,
3760 MSA128B, NoItinerary>;
3762 def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8,
3763 MSA128B, NoItinerary>;
3764 def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16,
3765 MSA128H, NoItinerary>;
3766 def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32,
3767 MSA128W, NoItinerary>;
3768 def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
3769 MSA128D, NoItinerary>;
3770 def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
3771 MSA128B, NoItinerary>;
3773 // Pseudoes used to implement transparent fp16 support.
3775 let ASEPredicate = [HasMSA] in {
3776 let usesCustomInserter = 1 in {
3778 MipsPseudo<(outs), (ins MSA128F16:$ws, mem_simm10:$addr),
3779 [(store (f16 MSA128F16:$ws), (addrimm10:$addr))]>;
3781 MipsPseudo<(outs MSA128F16:$ws), (ins mem_simm10:$addr),
3782 [(set MSA128F16:$ws, (f16 (load addrimm10:$addr)))]>;
3785 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
3786 def MSA_FP_EXTEND_W_PSEUDO :
3787 MipsPseudo<(outs FGR32Opnd:$fd), (ins MSA128F16:$ws),
3788 [(set FGR32Opnd:$fd, (f32 (fpextend MSA128F16:$ws)))]>;
3789 def MSA_FP_ROUND_W_PSEUDO :
3790 MipsPseudo<(outs MSA128F16:$wd), (ins FGR32Opnd:$fs),
3791 [(set MSA128F16:$wd, (f16 (fpround FGR32Opnd:$fs)))]>;
3792 def MSA_FP_EXTEND_D_PSEUDO :
3793 MipsPseudo<(outs FGR64Opnd:$fd), (ins MSA128F16:$ws),
3794 [(set FGR64Opnd:$fd, (f64 (fpextend MSA128F16:$ws)))]>;
3795 def MSA_FP_ROUND_D_PSEUDO :
3796 MipsPseudo<(outs MSA128F16:$wd), (ins FGR64Opnd:$fs),
3797 [(set MSA128F16:$wd, (f16 (fpround FGR64Opnd:$fs)))]>;
3800 def : MipsPat<(MipsTruncIntFP MSA128F16:$ws),
3801 (TRUNC_W_D64 (MSA_FP_EXTEND_D_PSEUDO MSA128F16:$ws))>,
3804 def : MipsPat<(MipsFPCmp MSA128F16:$ws, MSA128F16:$wt, imm:$cond),
3805 (FCMP_S32 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$ws),
3806 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$wt), imm:$cond)>,
3807 ISA_MIPS1_NOT_32R6_64R6, ASE_MSA;
3810 def vsplati64_imm_eq_63 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{
3812 SDNode *BV = N->getOperand(0).getNode();
3813 EVT EltTy = N->getValueType(0).getVectorElementType();
3815 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) &&
3816 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63;
3819 def immi32Cst7 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 7;}]>;
3820 def immi32Cst15 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 15;}]>;
3821 def immi32Cst31 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 31;}]>;
3823 def vsplati8imm7 : PatFrag<(ops node:$wt),
3824 (and node:$wt, (vsplati8 immi32Cst7))>;
3825 def vsplati16imm15 : PatFrag<(ops node:$wt),
3826 (and node:$wt, (vsplati16 immi32Cst15))>;
3827 def vsplati32imm31 : PatFrag<(ops node:$wt),
3828 (and node:$wt, (vsplati32 immi32Cst31))>;
3829 def vsplati64imm63 : PatFrag<(ops node:$wt),
3830 (and node:$wt, vsplati64_imm_eq_63)>;
3832 class MSAShiftPat<SDNode Node, ValueType VT, MSAInst Insn, dag Vec> :
3833 MSAPat<(VT (Node VT:$ws, (VT (and VT:$wt, Vec)))),
3834 (VT (Insn VT:$ws, VT:$wt))>;
3836 class MSABitPat<SDNode Node, ValueType VT, MSAInst Insn, PatFrag Frag> :
3837 MSAPat<(VT (Node VT:$ws, (shl vsplat_imm_eq_1, (Frag VT:$wt)))),
3838 (VT (Insn VT:$ws, VT:$wt))>;
3840 multiclass MSAShiftPats<SDNode Node, string Insn> {
3841 def : MSAShiftPat<Node, v16i8, !cast<MSAInst>(Insn#_B),
3842 (vsplati8 immi32Cst7)>;
3843 def : MSAShiftPat<Node, v8i16, !cast<MSAInst>(Insn#_H),
3844 (vsplati16 immi32Cst15)>;
3845 def : MSAShiftPat<Node, v4i32, !cast<MSAInst>(Insn#_W),
3846 (vsplati32 immi32Cst31)>;
3847 def : MSAPat<(v2i64 (Node v2i64:$ws, (v2i64 (and v2i64:$wt,
3848 vsplati64_imm_eq_63)))),
3849 (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>;
3852 multiclass MSABitPats<SDNode Node, string Insn> {
3853 def : MSABitPat<Node, v16i8, !cast<MSAInst>(Insn#_B), vsplati8imm7>;
3854 def : MSABitPat<Node, v8i16, !cast<MSAInst>(Insn#_H), vsplati16imm15>;
3855 def : MSABitPat<Node, v4i32, !cast<MSAInst>(Insn#_W), vsplati32imm31>;
3856 def : MSAPat<(Node v2i64:$ws, (shl (v2i64 vsplati64_imm_eq_1),
3857 (vsplati64imm63 v2i64:$wt))),
3858 (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>;
3861 defm : MSAShiftPats<shl, "SLL">;
3862 defm : MSAShiftPats<srl, "SRL">;
3863 defm : MSAShiftPats<sra, "SRA">;
3864 defm : MSABitPats<xor, "BNEG">;
3865 defm : MSABitPats<or, "BSET">;
3867 def : MSAPat<(and v16i8:$ws, (xor (shl vsplat_imm_eq_1,
3868 (vsplati8imm7 v16i8:$wt)),
3870 (v16i8 (BCLR_B v16i8:$ws, v16i8:$wt))>;
3871 def : MSAPat<(and v8i16:$ws, (xor (shl vsplat_imm_eq_1,
3872 (vsplati16imm15 v8i16:$wt)),
3874 (v8i16 (BCLR_H v8i16:$ws, v8i16:$wt))>;
3875 def : MSAPat<(and v4i32:$ws, (xor (shl vsplat_imm_eq_1,
3876 (vsplati32imm31 v4i32:$wt)),
3878 (v4i32 (BCLR_W v4i32:$ws, v4i32:$wt))>;
3879 def : MSAPat<(and v2i64:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1),
3880 (vsplati64imm63 v2i64:$wt)),
3881 (bitconvert (v4i32 immAllOnesV)))),
3882 (v2i64 (BCLR_D v2i64:$ws, v2i64:$wt))>;
3884 // Vector extraction with fixed index.
3886 // Extracting 32-bit values on MSA32 should always use COPY_S_W rather than
3887 // COPY_U_W, even for the zero-extended case. This is because our forward
3888 // compatibility strategy is to consider registers to be infinitely
3889 // sign-extended so that a MIPS64 can execute MIPS32 code without getting
3890 // different register values.
3891 def : MSAPat<(vextract_zext_i32 (v4i32 MSA128W:$ws), immZExt2Ptr:$idx),
3892 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64;
3893 def : MSAPat<(vextract_zext_i32 (v4f32 MSA128W:$ws), immZExt2Ptr:$idx),
3894 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64;
3896 // Extracting 64-bit values on MSA64 should always use COPY_S_D rather than
3897 // COPY_U_D, even for the zero-extended case. This is because our forward
3898 // compatibility strategy is to consider registers to be infinitely
3899 // sign-extended so that a hypothetical MIPS128 would be able to execute MIPS64
3900 // code without getting different register values.
3901 def : MSAPat<(vextract_zext_i64 (v2i64 MSA128D:$ws), immZExt1Ptr:$idx),
3902 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64;
3903 def : MSAPat<(vextract_zext_i64 (v2f64 MSA128D:$ws), immZExt1Ptr:$idx),
3904 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64;
3906 // Vector extraction with variable index
3907 def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)),
3908 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3912 def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)),
3913 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3917 def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)),
3918 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3922 def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)),
3923 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3926 GPR64), [HasMSA, IsGP64bit]>;
3928 def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)),
3929 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3933 def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)),
3934 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3938 def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)),
3939 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3943 def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)),
3944 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3947 GPR64), [HasMSA, IsGP64bit]>;
3949 def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)),
3950 (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws,
3953 def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)),
3954 (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws,
3958 // Vector extraction with variable index (N64 ABI)
3960 (i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)),
3961 (SRA (COPY_TO_REGCLASS
3962 (i32 (EXTRACT_SUBREG
3965 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3970 (i32 (vextract_sext_i16 v8i16:$ws, i64:$idx)),
3971 (SRA (COPY_TO_REGCLASS
3972 (i32 (EXTRACT_SUBREG
3975 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3980 (i32 (vextract_sext_i32 v4i32:$ws, i64:$idx)),
3982 (i32 (EXTRACT_SUBREG
3985 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3989 (i64 (vextract_sext_i64 v2i64:$ws, i64:$idx)),
3991 (i64 (EXTRACT_SUBREG
3993 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3995 GPR64), [HasMSA, IsGP64bit]>;
3998 (i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)),
3999 (SRL (COPY_TO_REGCLASS
4000 (i32 (EXTRACT_SUBREG
4003 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4008 (i32 (vextract_zext_i16 v8i16:$ws, i64:$idx)),
4009 (SRL (COPY_TO_REGCLASS
4010 (i32 (EXTRACT_SUBREG
4013 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4018 (i32 (vextract_zext_i32 v4i32:$ws, i64:$idx)),
4020 (i32 (EXTRACT_SUBREG
4022 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4026 (i64 (vextract_zext_i64 v2i64:$ws, i64:$idx)),
4028 (i64 (EXTRACT_SUBREG
4030 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4033 [HasMSA, IsGP64bit]>;
4036 (f32 (vector_extract v4f32:$ws, i64:$idx)),
4037 (f32 (EXTRACT_SUBREG
4039 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4042 (f64 (vector_extract v2f64:$ws, i64:$idx)),
4043 (f64 (EXTRACT_SUBREG
4045 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4048 def : MSAPat<(vfseteq_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
4049 (FCEQ_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
4050 def : MSAPat<(vfseteq_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
4051 (FCEQ_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
4052 def : MSAPat<(vfsetle_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
4053 (FCLE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
4054 def : MSAPat<(vfsetle_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
4055 (FCLE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
4056 def : MSAPat<(vfsetlt_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
4057 (FCLT_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
4058 def : MSAPat<(vfsetlt_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
4059 (FCLT_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
4060 def : MSAPat<(vfsetne_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
4061 (FCNE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
4062 def : MSAPat<(vfsetne_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
4063 (FCNE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;