1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
11 //===----------------------------------------------------------------------===//
13 #include "MipsSEInstrInfo.h"
14 #include "MCTargetDesc/MipsInstPrinter.h"
15 #include "MipsAnalyzeImmediate.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/TargetRegistry.h"
27 static unsigned getUnconditionalBranch(const MipsSubtarget &STI) {
28 if (STI.inMicroMipsMode())
29 return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM;
30 return STI.isPositionIndependent() ? Mips::B : Mips::J;
33 MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI)
34 : MipsInstrInfo(STI, getUnconditionalBranch(STI)), RI() {}
36 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
40 /// isLoadFromStackSlot - If the specified machine instruction is a direct
41 /// load from a stack slot, return the virtual or physical register number of
42 /// the destination along with the FrameIndex of the loaded stack slot. If
43 /// not, return 0. This predicate must return 0 if the instruction has
44 /// any side effects other than loading from the stack slot.
45 unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
46 int &FrameIndex) const {
47 unsigned Opc = MI.getOpcode();
49 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
51 if ((MI.getOperand(1).isFI()) && // is a stack slot
52 (MI.getOperand(2).isImm()) && // the imm is zero
53 (isZeroImm(MI.getOperand(2)))) {
54 FrameIndex = MI.getOperand(1).getIndex();
55 return MI.getOperand(0).getReg();
62 /// isStoreToStackSlot - If the specified machine instruction is a direct
63 /// store to a stack slot, return the virtual or physical register number of
64 /// the source reg along with the FrameIndex of the loaded stack slot. If
65 /// not, return 0. This predicate must return 0 if the instruction has
66 /// any side effects other than storing to the stack slot.
67 unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
68 int &FrameIndex) const {
69 unsigned Opc = MI.getOpcode();
71 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
73 if ((MI.getOperand(1).isFI()) && // is a stack slot
74 (MI.getOperand(2).isImm()) && // the imm is zero
75 (isZeroImm(MI.getOperand(2)))) {
76 FrameIndex = MI.getOperand(1).getIndex();
77 return MI.getOperand(0).getReg();
83 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator I,
85 const DebugLoc &DL, MCRegister DestReg,
86 MCRegister SrcReg, bool KillSrc) const {
87 unsigned Opc = 0, ZeroReg = 0;
88 bool isMicroMips = Subtarget.inMicroMipsMode();
90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
91 if (Mips::GPR32RegClass.contains(SrcReg)) {
93 Opc = Mips::MOVE16_MM;
95 Opc = Mips::OR, ZeroReg = Mips::ZERO;
96 } else if (Mips::CCRRegClass.contains(SrcReg))
98 else if (Mips::FGR32RegClass.contains(SrcReg))
100 else if (Mips::HI32RegClass.contains(SrcReg)) {
101 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
103 } else if (Mips::LO32RegClass.contains(SrcReg)) {
104 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
106 } else if (Mips::HI32DSPRegClass.contains(SrcReg))
107 Opc = Mips::MFHI_DSP;
108 else if (Mips::LO32DSPRegClass.contains(SrcReg))
109 Opc = Mips::MFLO_DSP;
110 else if (Mips::DSPCCRegClass.contains(SrcReg)) {
111 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
112 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
115 else if (Mips::MSACtrlRegClass.contains(SrcReg))
118 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
119 if (Mips::CCRRegClass.contains(DestReg))
121 else if (Mips::FGR32RegClass.contains(DestReg))
123 else if (Mips::HI32RegClass.contains(DestReg))
124 Opc = Mips::MTHI, DestReg = 0;
125 else if (Mips::LO32RegClass.contains(DestReg))
126 Opc = Mips::MTLO, DestReg = 0;
127 else if (Mips::HI32DSPRegClass.contains(DestReg))
128 Opc = Mips::MTHI_DSP;
129 else if (Mips::LO32DSPRegClass.contains(DestReg))
130 Opc = Mips::MTLO_DSP;
131 else if (Mips::DSPCCRegClass.contains(DestReg)) {
132 BuildMI(MBB, I, DL, get(Mips::WRDSP))
133 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
134 .addReg(DestReg, RegState::ImplicitDefine);
136 } else if (Mips::MSACtrlRegClass.contains(DestReg)) {
137 BuildMI(MBB, I, DL, get(Mips::CTCMSA))
139 .addReg(SrcReg, getKillRegState(KillSrc));
143 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
145 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
146 Opc = Mips::FMOV_D32;
147 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
148 Opc = Mips::FMOV_D64;
149 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
150 if (Mips::GPR64RegClass.contains(SrcReg))
151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
152 else if (Mips::HI64RegClass.contains(SrcReg))
153 Opc = Mips::MFHI64, SrcReg = 0;
154 else if (Mips::LO64RegClass.contains(SrcReg))
155 Opc = Mips::MFLO64, SrcReg = 0;
156 else if (Mips::FGR64RegClass.contains(SrcReg))
159 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
160 if (Mips::HI64RegClass.contains(DestReg))
161 Opc = Mips::MTHI64, DestReg = 0;
162 else if (Mips::LO64RegClass.contains(DestReg))
163 Opc = Mips::MTLO64, DestReg = 0;
164 else if (Mips::FGR64RegClass.contains(DestReg))
167 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
168 if (Mips::MSA128BRegClass.contains(SrcReg))
172 assert(Opc && "Cannot copy registers");
174 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
177 MIB.addReg(DestReg, RegState::Define);
180 MIB.addReg(SrcReg, getKillRegState(KillSrc));
186 static bool isORCopyInst(const MachineInstr &MI) {
187 switch (MI.getOpcode()) {
192 if (MI.getOperand(2).getReg() == Mips::ZERO)
196 if (MI.getOperand(2).getReg() == Mips::ZERO_64)
203 /// If @MI is WRDSP/RRDSP instruction return true with @isWrite set to true
204 /// if it is WRDSP instruction.
205 static bool isReadOrWriteToDSPReg(const MachineInstr &MI, bool &isWrite) {
206 switch (MI.getOpcode()) {
221 /// We check for the common case of 'or', as it's MIPS' preferred instruction
222 /// for GPRs but we have to check the operands to ensure that is the case.
223 /// Other move instructions for MIPS are directly identifiable.
224 Optional<DestSourcePair>
225 MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
226 bool isDSPControlWrite = false;
227 // Condition is made to match the creation of WRDSP/RDDSP copy instruction
228 // from copyPhysReg function.
229 if (isReadOrWriteToDSPReg(MI, isDSPControlWrite)) {
230 if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1 << 4))
232 else if (isDSPControlWrite) {
233 return DestSourcePair{MI.getOperand(2), MI.getOperand(0)};
236 return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
238 } else if (MI.isMoveReg() || isORCopyInst(MI)) {
239 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
244 void MipsSEInstrInfo::
245 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
246 unsigned SrcReg, bool isKill, int FI,
247 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
248 int64_t Offset) const {
250 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
254 if (Mips::GPR32RegClass.hasSubClassEq(RC))
256 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
258 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
259 Opc = Mips::STORE_ACC64;
260 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
261 Opc = Mips::STORE_ACC64DSP;
262 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
263 Opc = Mips::STORE_ACC128;
264 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
265 Opc = Mips::STORE_CCOND_DSP;
266 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
268 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
270 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
272 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
274 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
275 TRI->isTypeLegalForClass(*RC, MVT::v8f16))
277 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
278 TRI->isTypeLegalForClass(*RC, MVT::v4f32))
280 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
281 TRI->isTypeLegalForClass(*RC, MVT::v2f64))
283 else if (Mips::LO32RegClass.hasSubClassEq(RC))
285 else if (Mips::LO64RegClass.hasSubClassEq(RC))
287 else if (Mips::HI32RegClass.hasSubClassEq(RC))
289 else if (Mips::HI64RegClass.hasSubClassEq(RC))
291 else if (Mips::DSPRRegClass.hasSubClassEq(RC))
294 // Hi, Lo are normally caller save but they are callee save
295 // for interrupt handling.
296 const Function &Func = MBB.getParent()->getFunction();
297 if (Func.hasFnAttribute("interrupt")) {
298 if (Mips::HI32RegClass.hasSubClassEq(RC)) {
299 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
301 } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
302 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
303 SrcReg = Mips::K0_64;
304 } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
305 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
307 } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
308 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
309 SrcReg = Mips::K0_64;
313 assert(Opc && "Register class not handled!");
314 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
315 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
318 void MipsSEInstrInfo::
319 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
320 unsigned DestReg, int FI, const TargetRegisterClass *RC,
321 const TargetRegisterInfo *TRI, int64_t Offset) const {
323 if (I != MBB.end()) DL = I->getDebugLoc();
324 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
327 const Function &Func = MBB.getParent()->getFunction();
328 bool ReqIndirectLoad = Func.hasFnAttribute("interrupt") &&
329 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
330 DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
332 if (Mips::GPR32RegClass.hasSubClassEq(RC))
334 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
336 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
337 Opc = Mips::LOAD_ACC64;
338 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
339 Opc = Mips::LOAD_ACC64DSP;
340 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
341 Opc = Mips::LOAD_ACC128;
342 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
343 Opc = Mips::LOAD_CCOND_DSP;
344 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
346 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
348 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
350 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
352 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
353 TRI->isTypeLegalForClass(*RC, MVT::v8f16))
355 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
356 TRI->isTypeLegalForClass(*RC, MVT::v4f32))
358 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
359 TRI->isTypeLegalForClass(*RC, MVT::v2f64))
361 else if (Mips::HI32RegClass.hasSubClassEq(RC))
363 else if (Mips::HI64RegClass.hasSubClassEq(RC))
365 else if (Mips::LO32RegClass.hasSubClassEq(RC))
367 else if (Mips::LO64RegClass.hasSubClassEq(RC))
369 else if (Mips::DSPRRegClass.hasSubClassEq(RC))
372 assert(Opc && "Register class not handled!");
374 if (!ReqIndirectLoad)
375 BuildMI(MBB, I, DL, get(Opc), DestReg)
380 // Load HI/LO through K0. Notably the DestReg is encoded into the
381 // instruction itself.
382 unsigned Reg = Mips::K0;
383 unsigned LdOp = Mips::MTLO;
384 if (DestReg == Mips::HI0)
387 if (Subtarget.getABI().ArePtrs64bit()) {
389 if (DestReg == Mips::HI0_64)
395 BuildMI(MBB, I, DL, get(Opc), Reg)
399 BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
403 bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
404 MachineBasicBlock &MBB = *MI.getParent();
405 bool isMicroMips = Subtarget.inMicroMipsMode();
408 switch (MI.getDesc().getOpcode()) {
412 expandRetRA(MBB, MI);
417 case Mips::PseudoMFHI:
418 expandPseudoMFHiLo(MBB, MI, Mips::MFHI);
420 case Mips::PseudoMFHI_MM:
421 expandPseudoMFHiLo(MBB, MI, Mips::MFHI16_MM);
423 case Mips::PseudoMFLO:
424 expandPseudoMFHiLo(MBB, MI, Mips::MFLO);
426 case Mips::PseudoMFLO_MM:
427 expandPseudoMFHiLo(MBB, MI, Mips::MFLO16_MM);
429 case Mips::PseudoMFHI64:
430 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
432 case Mips::PseudoMFLO64:
433 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
435 case Mips::PseudoMTLOHI:
436 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
438 case Mips::PseudoMTLOHI64:
439 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
441 case Mips::PseudoMTLOHI_DSP:
442 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
444 case Mips::PseudoMTLOHI_MM:
445 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_MM, Mips::MTHI_MM, false);
447 case Mips::PseudoCVT_S_W:
448 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
450 case Mips::PseudoCVT_D32_W:
451 Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W;
452 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false);
454 case Mips::PseudoCVT_S_L:
455 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
457 case Mips::PseudoCVT_D64_W:
458 Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W;
459 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true);
461 case Mips::PseudoCVT_D64_L:
462 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
464 case Mips::BuildPairF64:
465 expandBuildPairF64(MBB, MI, isMicroMips, false);
467 case Mips::BuildPairF64_64:
468 expandBuildPairF64(MBB, MI, isMicroMips, true);
470 case Mips::ExtractElementF64:
471 expandExtractElementF64(MBB, MI, isMicroMips, false);
473 case Mips::ExtractElementF64_64:
474 expandExtractElementF64(MBB, MI, isMicroMips, true);
476 case Mips::MIPSeh_return32:
477 case Mips::MIPSeh_return64:
478 expandEhReturn(MBB, MI);
486 /// getOppositeBranchOpc - Return the inverse of the specified
487 /// opcode, e.g. turning BEQ to BNE.
488 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
490 default: llvm_unreachable("Illegal opcode!");
491 case Mips::BEQ: return Mips::BNE;
492 case Mips::BEQ_MM: return Mips::BNE_MM;
493 case Mips::BNE: return Mips::BEQ;
494 case Mips::BNE_MM: return Mips::BEQ_MM;
495 case Mips::BGTZ: return Mips::BLEZ;
496 case Mips::BGEZ: return Mips::BLTZ;
497 case Mips::BLTZ: return Mips::BGEZ;
498 case Mips::BLEZ: return Mips::BGTZ;
499 case Mips::BGTZ_MM: return Mips::BLEZ_MM;
500 case Mips::BGEZ_MM: return Mips::BLTZ_MM;
501 case Mips::BLTZ_MM: return Mips::BGEZ_MM;
502 case Mips::BLEZ_MM: return Mips::BGTZ_MM;
503 case Mips::BEQ64: return Mips::BNE64;
504 case Mips::BNE64: return Mips::BEQ64;
505 case Mips::BGTZ64: return Mips::BLEZ64;
506 case Mips::BGEZ64: return Mips::BLTZ64;
507 case Mips::BLTZ64: return Mips::BGEZ64;
508 case Mips::BLEZ64: return Mips::BGTZ64;
509 case Mips::BC1T: return Mips::BC1F;
510 case Mips::BC1F: return Mips::BC1T;
511 case Mips::BC1T_MM: return Mips::BC1F_MM;
512 case Mips::BC1F_MM: return Mips::BC1T_MM;
513 case Mips::BEQZ16_MM: return Mips::BNEZ16_MM;
514 case Mips::BNEZ16_MM: return Mips::BEQZ16_MM;
515 case Mips::BEQZC_MM: return Mips::BNEZC_MM;
516 case Mips::BNEZC_MM: return Mips::BEQZC_MM;
517 case Mips::BEQZC: return Mips::BNEZC;
518 case Mips::BNEZC: return Mips::BEQZC;
519 case Mips::BLEZC: return Mips::BGTZC;
520 case Mips::BGEZC: return Mips::BLTZC;
521 case Mips::BGEC: return Mips::BLTC;
522 case Mips::BGTZC: return Mips::BLEZC;
523 case Mips::BLTZC: return Mips::BGEZC;
524 case Mips::BLTC: return Mips::BGEC;
525 case Mips::BGEUC: return Mips::BLTUC;
526 case Mips::BLTUC: return Mips::BGEUC;
527 case Mips::BEQC: return Mips::BNEC;
528 case Mips::BNEC: return Mips::BEQC;
529 case Mips::BC1EQZ: return Mips::BC1NEZ;
530 case Mips::BC1NEZ: return Mips::BC1EQZ;
531 case Mips::BEQZC_MMR6: return Mips::BNEZC_MMR6;
532 case Mips::BNEZC_MMR6: return Mips::BEQZC_MMR6;
533 case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6;
534 case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR6;
535 case Mips::BGEC_MMR6: return Mips::BLTC_MMR6;
536 case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6;
537 case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR6;
538 case Mips::BLTC_MMR6: return Mips::BGEC_MMR6;
539 case Mips::BGEUC_MMR6: return Mips::BLTUC_MMR6;
540 case Mips::BLTUC_MMR6: return Mips::BGEUC_MMR6;
541 case Mips::BEQC_MMR6: return Mips::BNEC_MMR6;
542 case Mips::BNEC_MMR6: return Mips::BEQC_MMR6;
543 case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR6;
544 case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR6;
545 case Mips::BEQZC64: return Mips::BNEZC64;
546 case Mips::BNEZC64: return Mips::BEQZC64;
547 case Mips::BEQC64: return Mips::BNEC64;
548 case Mips::BNEC64: return Mips::BEQC64;
549 case Mips::BGEC64: return Mips::BLTC64;
550 case Mips::BGEUC64: return Mips::BLTUC64;
551 case Mips::BLTC64: return Mips::BGEC64;
552 case Mips::BLTUC64: return Mips::BGEUC64;
553 case Mips::BGTZC64: return Mips::BLEZC64;
554 case Mips::BGEZC64: return Mips::BLTZC64;
555 case Mips::BLTZC64: return Mips::BGEZC64;
556 case Mips::BLEZC64: return Mips::BGTZC64;
557 case Mips::BBIT0: return Mips::BBIT1;
558 case Mips::BBIT1: return Mips::BBIT0;
559 case Mips::BBIT032: return Mips::BBIT132;
560 case Mips::BBIT132: return Mips::BBIT032;
561 case Mips::BZ_B: return Mips::BNZ_B;
562 case Mips::BZ_H: return Mips::BNZ_H;
563 case Mips::BZ_W: return Mips::BNZ_W;
564 case Mips::BZ_D: return Mips::BNZ_D;
565 case Mips::BZ_V: return Mips::BNZ_V;
566 case Mips::BNZ_B: return Mips::BZ_B;
567 case Mips::BNZ_H: return Mips::BZ_H;
568 case Mips::BNZ_W: return Mips::BZ_W;
569 case Mips::BNZ_D: return Mips::BZ_D;
570 case Mips::BNZ_V: return Mips::BZ_V;
574 /// Adjust SP by Amount bytes.
575 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
576 MachineBasicBlock &MBB,
577 MachineBasicBlock::iterator I) const {
578 MipsABIInfo ABI = Subtarget.getABI();
580 unsigned ADDiu = ABI.GetPtrAddiuOp();
585 if (isInt<16>(Amount)) {
586 // addi sp, sp, amount
587 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
589 // For numbers which are not 16bit integers we synthesize Amount inline
590 // then add or subtract it from sp.
591 unsigned Opc = ABI.GetPtrAdduOp();
593 Opc = ABI.GetPtrSubuOp();
596 unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
597 BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
601 /// This function generates the sequence of instructions needed to get the
602 /// result of adding register REG and immediate IMM.
603 unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
604 MachineBasicBlock::iterator II,
606 unsigned *NewImm) const {
607 MipsAnalyzeImmediate AnalyzeImm;
608 const MipsSubtarget &STI = Subtarget;
609 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
610 unsigned Size = STI.isABI_N64() ? 64 : 32;
611 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
612 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
613 const TargetRegisterClass *RC = STI.isABI_N64() ?
614 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
615 bool LastInstrIsADDiu = NewImm;
617 const MipsAnalyzeImmediate::InstSeq &Seq =
618 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
619 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
621 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
623 // The first instruction can be a LUi, which is different from other
624 // instructions (ADDiu, ORI and SLL) in that it does not have a register
626 Register Reg = RegInfo.createVirtualRegister(RC);
628 if (Inst->Opc == LUi)
629 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
631 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
632 .addImm(SignExtend64<16>(Inst->ImmOpnd));
634 // Build the remaining instructions in Seq.
635 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
636 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
637 .addImm(SignExtend64<16>(Inst->ImmOpnd));
639 if (LastInstrIsADDiu)
640 *NewImm = Inst->ImmOpnd;
645 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
646 return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE ||
647 Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ ||
648 Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 ||
649 Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
650 Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T ||
651 Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J ||
652 Opc == Mips::J_MM || Opc == Mips::B_MM || Opc == Mips::BEQZC_MM ||
653 Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC ||
654 Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC ||
655 Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC ||
656 Opc == Mips::BGEZC || Opc == Mips::BLTZC || Opc == Mips::BEQZC ||
657 Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 ||
658 Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 ||
659 Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 ||
660 Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 ||
661 Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC ||
662 Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||
663 Opc == Mips::BBIT132 || Opc == Mips::BC_MMR6 ||
664 Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 ||
665 Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 ||
666 Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 ||
667 Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 ||
668 Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 ||
669 Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0;
672 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
673 MachineBasicBlock::iterator I) const {
675 MachineInstrBuilder MIB;
676 if (Subtarget.isGP64bit())
677 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
678 .addReg(Mips::RA_64, RegState::Undef);
680 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
681 .addReg(Mips::RA, RegState::Undef);
683 // Retain any imp-use flags.
684 for (auto & MO : I->operands()) {
690 void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB,
691 MachineBasicBlock::iterator I) const {
692 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
695 std::pair<bool, bool>
696 MipsSEInstrInfo::compareOpndSize(unsigned Opc,
697 const MachineFunction &MF) const {
698 const MCInstrDesc &Desc = get(Opc);
699 assert(Desc.NumOperands == 2 && "Unary instruction expected.");
700 const MipsRegisterInfo *RI = &getRegisterInfo();
701 unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF));
702 unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF));
704 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
707 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
708 MachineBasicBlock::iterator I,
709 unsigned NewOpc) const {
710 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
713 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
714 MachineBasicBlock::iterator I,
717 bool HasExplicitDef) const {
719 // lo_hi pseudomtlohi $gpr0, $gpr1
720 // to these two instructions:
724 DebugLoc DL = I->getDebugLoc();
725 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
726 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
727 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
729 // Add lo/hi registers if the mtlo/hi instructions created have explicit
731 if (HasExplicitDef) {
732 Register DstReg = I->getOperand(0).getReg();
733 Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
734 Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
735 LoInst.addReg(DstLo, RegState::Define);
736 HiInst.addReg(DstHi, RegState::Define);
739 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
740 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
743 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
744 MachineBasicBlock::iterator I,
745 unsigned CvtOpc, unsigned MovOpc,
747 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
748 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
749 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
750 unsigned KillSrc = getKillRegState(Src.isKill());
751 DebugLoc DL = I->getDebugLoc();
752 bool DstIsLarger, SrcIsLarger;
754 std::tie(DstIsLarger, SrcIsLarger) =
755 compareOpndSize(CvtOpc, *MBB.getParent());
758 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
761 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
763 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
764 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
767 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
768 MachineBasicBlock::iterator I,
771 Register DstReg = I->getOperand(0).getReg();
772 Register SrcReg = I->getOperand(1).getReg();
773 unsigned N = I->getOperand(2).getImm();
774 DebugLoc dl = I->getDebugLoc();
776 assert(N < 2 && "Invalid immediate");
777 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
778 Register SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
780 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
781 // in MipsSEFrameLowering.cpp.
782 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
784 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
785 // in MipsSEFrameLowering.cpp.
786 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
788 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
789 // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
790 // claim to read the whole 64-bits as part of a white lie used to
791 // temporarily work around a widespread bug in the -mfp64 support.
792 // The problem is that none of the 32-bit fpu ops mention the fact
793 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
794 // requires a major overhaul of the FPU implementation which can't
795 // be done right now due to time constraints.
796 // MFHC1 is one of two instructions that are affected since they are
797 // the only instructions that don't read the lower 32-bits.
798 // We therefore pretend that it reads the bottom 32-bits to
799 // artificially create a dependency and prevent the scheduler
800 // changing the behaviour of the code.
802 get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM)
803 : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)),
807 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
810 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
811 MachineBasicBlock::iterator I,
812 bool isMicroMips, bool FP64) const {
813 Register DstReg = I->getOperand(0).getReg();
814 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
815 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
816 DebugLoc dl = I->getDebugLoc();
817 const TargetRegisterInfo &TRI = getRegisterInfo();
819 // When mthc1 is available, use:
823 // Otherwise, for O32 FPXX ABI:
824 // spill + reload via ldc1
825 // This case is handled by the frame lowering code.
827 // Otherwise, for FP32:
831 // The case where dmtc1 is available doesn't need to be handled here
832 // because it never creates a BuildPairF64 node.
834 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
835 // in MipsSEFrameLowering.cpp.
836 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
838 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
839 // in MipsSEFrameLowering.cpp.
840 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
842 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
845 if (Subtarget.hasMTHC1()) {
846 // FIXME: The .addReg(DstReg) is a white lie used to temporarily work
847 // around a widespread bug in the -mfp64 support.
848 // The problem is that none of the 32-bit fpu ops mention the fact
849 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
850 // requires a major overhaul of the FPU implementation which can't
851 // be done right now due to time constraints.
852 // MTHC1 is one of two instructions that are affected since they are
853 // the only instructions that don't read the lower 32-bits.
854 // We therefore pretend that it reads the bottom 32-bits to
855 // artificially create a dependency and prevent the scheduler
856 // changing the behaviour of the code.
858 get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM)
859 : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)),
863 } else if (Subtarget.isABI_FPXX())
864 llvm_unreachable("BuildPairF64 not expanded in frame lowering code!");
866 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
870 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
871 MachineBasicBlock::iterator I) const {
872 // This pseudo instruction is generated as part of the lowering of
873 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
874 // indirect jump to TargetReg
875 MipsABIInfo ABI = Subtarget.getABI();
876 unsigned ADDU = ABI.GetPtrAdduOp();
877 unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
878 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
879 unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;
880 unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
881 Register OffsetReg = I->getOperand(0).getReg();
882 Register TargetReg = I->getOperand(1).getReg();
884 // addu $ra, $v0, $zero
885 // addu $sp, $sp, $v1
886 // jr $ra (via RetRA)
887 const TargetMachine &TM = MBB.getParent()->getTarget();
888 if (TM.isPositionIndependent())
889 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
892 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
895 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
899 const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) {
900 return new MipsSEInstrInfo(STI);