1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This class prints an PPC MCInst to a .s file.
11 //===----------------------------------------------------------------------===//
13 #include "MCTargetDesc/PPCInstPrinter.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCInstrInfo.h"
17 #include "llvm/CodeGen/TargetOpcodes.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "asm-printer"
30 // FIXME: Once the integrated assembler supports full register names, tie this
31 // to the verbose-asm setting.
33 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
34 cl::desc("Use full register names when printing assembly"));
36 // Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
38 ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
39 cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
41 // Prints full register names with percent symbol.
43 FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,
45 cl::desc("Prints full register names with percent"));
47 #define PRINT_ALIAS_INSTR
48 #include "PPCGenAsmWriter.inc"
50 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
51 const char *RegName = getRegisterName(RegNo);
52 if (RegName[0] == 'q' /* QPX */) {
53 // The system toolchain on the BG/Q does not understand QPX register names
54 // in .cfi_* directives, so print the name of the floating-point
55 // subregister instead.
56 std::string RN(RegName);
67 void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
68 StringRef Annot, const MCSubtargetInfo &STI,
70 // Customize printing of the addis instruction on AIX. When an operand is a
71 // symbol reference, the instruction syntax is changed to look like a load
73 // Transform: addis $rD, $rA, $src --> addis $rD, $src($rA).
75 (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&
76 MI->getOperand(2).isExpr()) {
77 assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) &&
78 "The first and the second operand of an addis instruction"
79 " should be registers.");
81 assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) &&
82 "The third operand of an addis instruction should be a symbol "
83 "reference expression if it is an expression at all.");
86 printOperand(MI, 0, O);
88 printOperand(MI, 2, O);
90 printOperand(MI, 1, O);
95 // Check for slwi/srwi mnemonics.
96 if (MI->getOpcode() == PPC::RLWINM) {
97 unsigned char SH = MI->getOperand(2).getImm();
98 unsigned char MB = MI->getOperand(3).getImm();
99 unsigned char ME = MI->getOperand(4).getImm();
100 bool useSubstituteMnemonic = false;
101 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
102 O << "\tslwi "; useSubstituteMnemonic = true;
104 if (SH <= 31 && MB == (32-SH) && ME == 31) {
105 O << "\tsrwi "; useSubstituteMnemonic = true;
108 if (useSubstituteMnemonic) {
109 printOperand(MI, 0, O);
111 printOperand(MI, 1, O);
112 O << ", " << (unsigned int)SH;
114 printAnnotation(O, Annot);
119 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
120 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
122 printOperand(MI, 0, O);
124 printOperand(MI, 1, O);
125 printAnnotation(O, Annot);
129 if (MI->getOpcode() == PPC::RLDICR ||
130 MI->getOpcode() == PPC::RLDICR_32) {
131 unsigned char SH = MI->getOperand(2).getImm();
132 unsigned char ME = MI->getOperand(3).getImm();
133 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
136 printOperand(MI, 0, O);
138 printOperand(MI, 1, O);
139 O << ", " << (unsigned int)SH;
140 printAnnotation(O, Annot);
145 // dcbt[st] is printed manually here because:
146 // 1. The assembly syntax is different between embedded and server targets
147 // 2. We must print the short mnemonics for TH == 0 because the
148 // embedded/server syntax default will not be stable across assemblers
149 // The syntax for dcbt is:
150 // dcbt ra, rb, th [server]
151 // dcbt th, ra, rb [embedded]
152 // where th can be omitted when it is 0. dcbtst is the same.
153 if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
154 unsigned char TH = MI->getOperand(0).getImm();
156 if (MI->getOpcode() == PPC::DCBTST)
162 bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
163 if (IsBookE && TH != 0 && TH != 16)
164 O << (unsigned int) TH << ", ";
166 printOperand(MI, 1, O);
168 printOperand(MI, 2, O);
170 if (!IsBookE && TH != 0 && TH != 16)
171 O << ", " << (unsigned int) TH;
173 printAnnotation(O, Annot);
177 if (MI->getOpcode() == PPC::DCBF) {
178 unsigned char L = MI->getOperand(0).getImm();
179 if (!L || L == 1 || L == 3) {
181 if (L == 1 || L == 3)
187 printOperand(MI, 1, O);
189 printOperand(MI, 2, O);
191 printAnnotation(O, Annot);
196 if (!printAliasInstr(MI, O))
197 printInstruction(MI, Address, O);
198 printAnnotation(O, Annot);
201 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
203 const char *Modifier) {
204 unsigned Code = MI->getOperand(OpNo).getImm();
206 if (StringRef(Modifier) == "cc") {
207 switch ((PPC::Predicate)Code) {
208 case PPC::PRED_LT_MINUS:
209 case PPC::PRED_LT_PLUS:
213 case PPC::PRED_LE_MINUS:
214 case PPC::PRED_LE_PLUS:
218 case PPC::PRED_EQ_MINUS:
219 case PPC::PRED_EQ_PLUS:
223 case PPC::PRED_GE_MINUS:
224 case PPC::PRED_GE_PLUS:
228 case PPC::PRED_GT_MINUS:
229 case PPC::PRED_GT_PLUS:
233 case PPC::PRED_NE_MINUS:
234 case PPC::PRED_NE_PLUS:
238 case PPC::PRED_UN_MINUS:
239 case PPC::PRED_UN_PLUS:
243 case PPC::PRED_NU_MINUS:
244 case PPC::PRED_NU_PLUS:
248 case PPC::PRED_BIT_SET:
249 case PPC::PRED_BIT_UNSET:
250 llvm_unreachable("Invalid use of bit predicate code");
252 llvm_unreachable("Invalid predicate code");
255 if (StringRef(Modifier) == "pm") {
256 switch ((PPC::Predicate)Code) {
266 case PPC::PRED_LT_MINUS:
267 case PPC::PRED_LE_MINUS:
268 case PPC::PRED_EQ_MINUS:
269 case PPC::PRED_GE_MINUS:
270 case PPC::PRED_GT_MINUS:
271 case PPC::PRED_NE_MINUS:
272 case PPC::PRED_UN_MINUS:
273 case PPC::PRED_NU_MINUS:
276 case PPC::PRED_LT_PLUS:
277 case PPC::PRED_LE_PLUS:
278 case PPC::PRED_EQ_PLUS:
279 case PPC::PRED_GE_PLUS:
280 case PPC::PRED_GT_PLUS:
281 case PPC::PRED_NE_PLUS:
282 case PPC::PRED_UN_PLUS:
283 case PPC::PRED_NU_PLUS:
286 case PPC::PRED_BIT_SET:
287 case PPC::PRED_BIT_UNSET:
288 llvm_unreachable("Invalid use of bit predicate code");
290 llvm_unreachable("Invalid predicate code");
293 assert(StringRef(Modifier) == "reg" &&
294 "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
295 printOperand(MI, OpNo+1, O);
298 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
300 unsigned Code = MI->getOperand(OpNo).getImm();
307 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
309 unsigned int Value = MI->getOperand(OpNo).getImm();
310 assert(Value <= 1 && "Invalid u1imm argument!");
311 O << (unsigned int)Value;
314 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
316 unsigned int Value = MI->getOperand(OpNo).getImm();
317 assert(Value <= 3 && "Invalid u2imm argument!");
318 O << (unsigned int)Value;
321 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
323 unsigned int Value = MI->getOperand(OpNo).getImm();
324 assert(Value <= 8 && "Invalid u3imm argument!");
325 O << (unsigned int)Value;
328 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
330 unsigned int Value = MI->getOperand(OpNo).getImm();
331 assert(Value <= 15 && "Invalid u4imm argument!");
332 O << (unsigned int)Value;
335 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
337 int Value = MI->getOperand(OpNo).getImm();
338 Value = SignExtend32<5>(Value);
342 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
344 unsigned int Value = MI->getOperand(OpNo).getImm();
345 assert(Value <= 31 && "Invalid u5imm argument!");
346 O << (unsigned int)Value;
349 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
351 unsigned int Value = MI->getOperand(OpNo).getImm();
352 assert(Value <= 63 && "Invalid u6imm argument!");
353 O << (unsigned int)Value;
356 void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
358 unsigned int Value = MI->getOperand(OpNo).getImm();
359 assert(Value <= 127 && "Invalid u7imm argument!");
360 O << (unsigned int)Value;
363 // Operands of BUILD_VECTOR are signed and we use this to print operands
364 // of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
365 // print as unsigned.
366 void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
368 unsigned char Value = MI->getOperand(OpNo).getImm();
369 O << (unsigned int)Value;
372 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
374 unsigned short Value = MI->getOperand(OpNo).getImm();
375 assert(Value <= 1023 && "Invalid u10imm argument!");
376 O << (unsigned short)Value;
379 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
381 unsigned short Value = MI->getOperand(OpNo).getImm();
382 assert(Value <= 4095 && "Invalid u12imm argument!");
383 O << (unsigned short)Value;
386 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
388 if (MI->getOperand(OpNo).isImm())
389 O << (short)MI->getOperand(OpNo).getImm();
391 printOperand(MI, OpNo, O);
394 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
396 if (MI->getOperand(OpNo).isImm())
397 O << (unsigned short)MI->getOperand(OpNo).getImm();
399 printOperand(MI, OpNo, O);
402 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
404 if (!MI->getOperand(OpNo).isImm())
405 return printOperand(MI, OpNo, O);
407 // Branches can take an immediate operand. This is used by the branch
408 // selection pass to print .+8, an eight byte displacement from the PC.
410 int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
416 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
418 if (!MI->getOperand(OpNo).isImm())
419 return printOperand(MI, OpNo, O);
421 O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
425 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
427 unsigned CCReg = MI->getOperand(OpNo).getReg();
430 default: llvm_unreachable("Unknown CR register");
431 case PPC::CR0: RegNo = 0; break;
432 case PPC::CR1: RegNo = 1; break;
433 case PPC::CR2: RegNo = 2; break;
434 case PPC::CR3: RegNo = 3; break;
435 case PPC::CR4: RegNo = 4; break;
436 case PPC::CR5: RegNo = 5; break;
437 case PPC::CR6: RegNo = 6; break;
438 case PPC::CR7: RegNo = 7; break;
440 O << (0x80 >> RegNo);
443 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
445 printS16ImmOperand(MI, OpNo, O);
447 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
450 printOperand(MI, OpNo+1, O);
454 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
456 // When used as the base register, r0 reads constant zero rather than
457 // the value contained in the register. For this reason, the darwin
458 // assembler requires that we print r0 as 0 (no r) when used as the base.
459 if (MI->getOperand(OpNo).getReg() == PPC::R0)
462 printOperand(MI, OpNo, O);
464 printOperand(MI, OpNo+1, O);
467 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
469 // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
470 // come at the _end_ of the expression.
471 const MCOperand &Op = MI->getOperand(OpNo);
472 const MCSymbolRefExpr *RefExp = nullptr;
473 const MCConstantExpr *ConstExp = nullptr;
474 if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) {
475 RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
476 ConstExp = cast<MCConstantExpr>(BinExpr->getRHS());
478 RefExp = cast<MCSymbolRefExpr>(Op.getExpr());
480 O << RefExp->getSymbol().getName();
482 printOperand(MI, OpNo+1, O);
484 if (RefExp->getKind() != MCSymbolRefExpr::VK_None)
485 O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
486 if (ConstExp != nullptr)
487 O << '+' << ConstExp->getValue();
490 /// showRegistersWithPercentPrefix - Check if this register name should be
491 /// printed with a percentage symbol as prefix.
492 bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
493 if (!FullRegNamesWithPercent || TT.isOSDarwin() || TT.getOS() == Triple::AIX)
496 switch (RegName[0]) {
508 /// getVerboseConditionalRegName - This method expands the condition register
509 /// when requested explicitly or targetting Darwin.
510 const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
511 unsigned RegEncoding)
513 if (!TT.isOSDarwin() && !FullRegNames)
515 if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
517 const char *CRBits[] = {
518 "lt", "gt", "eq", "un",
519 "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
520 "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
521 "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
522 "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
523 "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
524 "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
525 "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
527 return CRBits[RegEncoding];
530 // showRegistersWithPrefix - This method determines whether registers
531 // should be number-only or include the prefix.
532 bool PPCInstPrinter::showRegistersWithPrefix() const {
533 if (TT.getOS() == Triple::AIX)
535 return TT.isOSDarwin() || FullRegNamesWithPercent || FullRegNames;
538 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
540 const MCOperand &Op = MI->getOperand(OpNo);
542 unsigned Reg = Op.getReg();
543 if (!ShowVSRNumsAsVR)
544 Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()),
548 RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
549 if (RegName == nullptr)
550 RegName = getRegisterName(Reg);
551 if (showRegistersWithPercentPrefix(RegName))
553 if (!showRegistersWithPrefix())
554 RegName = PPCRegisterInfo::stripRegisterPrefix(RegName);
565 assert(Op.isExpr() && "unknown operand kind in printOperand");
566 Op.getExpr()->print(O, &MAI);