contrib/llvm-project/llvm/lib/Target/PowerPC/PPC.td

   1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This is the top level entry point for the PowerPC target.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 // Get the target-independent interfaces which we are implementing.
  14 //
  15 include "llvm/Target/Target.td"
  16
  17 //===----------------------------------------------------------------------===//
  18 // PowerPC Subtarget features.
  19 //
  20
  21 //===----------------------------------------------------------------------===//
  22 // CPU Directives                                                             //
  23 //===----------------------------------------------------------------------===//
  24
  25 def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">;
  26 def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">;
  27 def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">;
  28 def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
  29 def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
  30 def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
  31 def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">;
  32 def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">;
  33 def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">;
  34 def Directive32  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">;
  35 def Directive64  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">;
  36 def DirectiveA2  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">;
  37 def DirectiveE500   : SubtargetFeature<"", "CPUDirective",
  38                                        "PPC::DIR_E500", "">;
  39 def DirectiveE500mc : SubtargetFeature<"", "CPUDirective",
  40                                        "PPC::DIR_E500mc", "">;
  41 def DirectiveE5500  : SubtargetFeature<"", "CPUDirective",
  42                                        "PPC::DIR_E5500", "">;
  43 def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">;
  44 def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">;
  45 def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">;
  46 def DirectivePwr5x
  47     : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">;
  48 def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">;
  49 def DirectivePwr6x
  50     : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">;
  51 def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">;
  52 def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">;
  53 def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">;
  54 def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">;
  55 def DirectivePwrFuture
  56     : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;
  57
  58 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  59                                         "Enable 64-bit instructions">;
  60 def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
  61                               "Enable floating-point instructions">;
  62 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  63                               "Enable 64-bit registers usage for ppc32 [beta]">;
  64 def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
  65                               "Use condition-register bits individually">;
  66 def FeatureFPU       : SubtargetFeature<"fpu","HasFPU","true",
  67                                         "Enable classic FPU instructions",
  68                                         [FeatureHardFloat]>;
  69 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  70                                         "Enable Altivec instructions",
  71                                         [FeatureFPU]>;
  72 def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
  73                                         "Enable SPE instructions",
  74                                         [FeatureHardFloat]>;
  75 def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
  76                                         "Enable the MFOCRF instruction">;
  77 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  78                                         "Enable the fsqrt instruction",
  79                                         [FeatureFPU]>;
  80 def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
  81                                         "Enable the fcpsgn instruction",
  82                                         [FeatureFPU]>;
  83 def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
  84                                         "Enable the fre instruction",
  85                                         [FeatureFPU]>;
  86 def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
  87                                         "Enable the fres instruction",
  88                                         [FeatureFPU]>;
  89 def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
  90                                         "Enable the frsqrte instruction",
  91                                         [FeatureFPU]>;
  92 def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
  93                                         "Enable the frsqrtes instruction",
  94                                         [FeatureFPU]>;
  95 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
  96                               "Assume higher precision reciprocal estimates">;
  97 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  98                                         "Enable the stfiwx instruction",
  99                                         [FeatureFPU]>;
 100 def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
 101                                         "Enable the lfiwax instruction",
 102                                         [FeatureFPU]>;
 103 def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
 104                                         "Enable the fri[mnpz] instructions",
 105                                         [FeatureFPU]>;
 106 def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
 107   "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
 108                                         [FeatureFPU]>;
 109 def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
 110                                         "Enable the isel instruction">;
 111 def FeatureBPERMD    : SubtargetFeature<"bpermd", "HasBPERMD", "true",
 112                                         "Enable the bpermd instruction">;
 113 def FeatureExtDiv    : SubtargetFeature<"extdiv", "HasExtDiv", "true",
 114                                         "Enable extended divide instructions">;
 115 def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
 116                                         "Enable the ldbrx instruction">;
 117 def FeatureCMPB      : SubtargetFeature<"cmpb", "HasCMPB", "true",
 118                                         "Enable the cmpb instruction">;
 119 def FeatureICBT      : SubtargetFeature<"icbt","HasICBT", "true",
 120                                         "Enable icbt instruction">;
 121 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
 122                                         "Enable Book E instructions",
 123                                         [FeatureICBT]>;
 124 def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
 125                               "Has only the msync instruction instead of sync",
 126                               [FeatureBookE]>;
 127 def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
 128                                         "Enable E500/E500mc instructions">;
 129 def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true",
 130                                         "Enable secure plt mode">;
 131 def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
 132                                         "Enable PPC 4xx instructions">;
 133 def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
 134                                         "Enable PPC 6xx instructions">;
 135 def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
 136                                         "Enable QPX instructions",
 137                                         [FeatureFPU]>;
 138 def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
 139                                         "Enable VSX instructions",
 140                                         [FeatureAltivec]>;
 141 def FeatureTwoConstNR :
 142   SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true",
 143                    "Requires two constant Newton-Raphson computation">;
 144 def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
 145                                         "Enable POWER8 Altivec instructions",
 146                                         [FeatureAltivec]>;
 147 def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
 148                                        "Enable POWER8 Crypto instructions",
 149                                        [FeatureP8Altivec]>;
 150 def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
 151                                         "Enable POWER8 vector instructions",
 152                                         [FeatureVSX, FeatureP8Altivec]>;
 153 def FeatureDirectMove :
 154   SubtargetFeature<"direct-move", "HasDirectMove", "true",
 155                    "Enable Power8 direct move instructions",
 156                    [FeatureVSX]>;
 157 def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
 158                                              "HasPartwordAtomics", "true",
 159                                              "Enable l[bh]arx and st[bh]cx.">;
 160 def FeatureInvariantFunctionDescriptors :
 161   SubtargetFeature<"invariant-function-descriptors",
 162                    "HasInvariantFunctionDescriptors", "true",
 163                    "Assume function descriptors are invariant">;
 164 def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
 165                                        "Always use indirect calls">;
 166 def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
 167                                   "Enable Hardware Transactional Memory instructions">;
 168 def FeatureMFTB   : SubtargetFeature<"", "FeatureMFTB", "true",
 169                                         "Implement mftb using the mfspr instruction">;
 170 def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
 171                                      "Target supports instruction fusion">;
 172 def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load",
 173                                              "HasAddiLoadFusion", "true",
 174                                              "Power8 Addi-Load fusion",
 175                                              [FeatureFusion]>;
 176 def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load",
 177                                               "HasAddisLoadFusion", "true",
 178                                               "Power8 Addis-Load fusion",
 179                                               [FeatureFusion]>;
 180 def FeatureUnalignedFloats :
 181   SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess",
 182                    "true", "CPU does not trap on unaligned FP access">;
 183 def FeaturePPCPreRASched:
 184   SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true",
 185                    "Use PowerPC pre-RA scheduling strategy">;
 186 def FeaturePPCPostRASched:
 187   SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true",
 188                    "Use PowerPC post-RA scheduling strategy">;
 189 def FeatureFloat128 :
 190   SubtargetFeature<"float128", "HasFloat128", "true",
 191                    "Enable the __float128 data type for IEEE-754R Binary128.",
 192                    [FeatureVSX]>;
 193 def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD",
 194                                         "POPCNTD_Fast",
 195                                         "Enable the popcnt[dw] instructions">;
 196 // Note that for the a2/a2q processor models we should not use popcnt[dw] by
 197 // default. These processors do support the instructions, but they're
 198 // microcoded, and the software emulation is about twice as fast.
 199 def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
 200                                           "POPCNTD_Slow",
 201                                           "Has slow popcnt[dw] instructions">;
 202
 203 def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
 204   "Treat vector data stream cache control instructions as deprecated">;
 205
 206 def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
 207                                      "true",
 208                                      "Enable instructions in ISA 3.0.">;
 209 def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1",
 210                                      "true",
 211                                      "Enable instructions in ISA 3.1.",
 212                                      [FeatureISA3_0]>;
 213 def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
 214                                         "Enable POWER9 Altivec instructions",
 215                                         [FeatureISA3_0, FeatureP8Altivec]>;
 216 def FeatureP9Vector  : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
 217                                         "Enable POWER9 vector instructions",
 218                                         [FeatureISA3_0, FeatureP8Vector,
 219                                          FeatureP9Altivec]>;
 220 def FeatureP10Vector  : SubtargetFeature<"power10-vector", "HasP10Vector",
 221                                          "true",
 222                                          "Enable POWER10 vector instructions",
 223                                          [FeatureISA3_1, FeatureP9Vector]>;
 224 // A separate feature for this even though it is equivalent to P9Vector
 225 // because this is a feature of the implementation rather than the architecture
 226 // and may go away with future CPU's.
 227 def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
 228                                                  "VectorsUseTwoUnits",
 229                                                  "true",
 230                                                  "Vectors use two units">;
 231 def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs",
 232                                            "true",
 233                                            "Enable prefixed instructions",
 234                                            [FeatureISA3_0, FeatureP8Vector,
 235                                             FeatureP9Altivec]>;
 236 def FeaturePCRelativeMemops :
 237   SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
 238                    "Enable PC relative Memory Ops",
 239                    [FeatureISA3_0]>;
 240
 241 def FeaturePredictableSelectIsExpensive :
 242   SubtargetFeature<"predictable-select-expensive",
 243                    "PredictableSelectIsExpensive",
 244                    "true",
 245                    "Prefer likely predicted branches over selects">;
 246
 247 // Since new processors generally contain a superset of features of those that
 248 // came before them, the idea is to make implementations of new processors
 249 // less error prone and easier to read.
 250 // Namely:
 251 //     list<SubtargetFeature> P8InheritableFeatures = ...
 252 //     list<SubtargetFeature> FutureProcessorAddtionalFeatures =
 253 //         [ features that Power8 does not support but inheritable ]
 254 //     list<SubtargetFeature> FutureProcessorSpecificFeatures =
 255 //         [ features that Power8 does not support and not inheritable ]
 256 //     list<SubtargetFeature> FutureProcessorInheritableFeatures =
 257 //         !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures)
 258 //     list<SubtargetFeature> FutureProcessorFeatures =
 259 //         !listconcat(FutureProcessorInheritableFeatures,
 260 //                     FutureProcessorSpecificFeatures)
 261
 262 // Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as
 263 // well as providing a single point of definition if the feature set will be
 264 // used elsewhere.
 265 def ProcessorFeatures {
 266   // Power7
 267   list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7,
 268                                                   FeatureAltivec,
 269                                                   FeatureVSX,
 270                                                   FeatureMFOCRF,
 271                                                   FeatureFCPSGN,
 272                                                   FeatureFSqrt,
 273                                                   FeatureFRE,
 274                                                   FeatureFRES,
 275                                                   FeatureFRSQRTE,
 276                                                   FeatureFRSQRTES,
 277                                                   FeatureRecipPrec,
 278                                                   FeatureSTFIWX,
 279                                                   FeatureLFIWAX,
 280                                                   FeatureFPRND,
 281                                                   FeatureFPCVT,
 282                                                   FeatureISEL,
 283                                                   FeaturePOPCNTD,
 284                                                   FeatureCMPB,
 285                                                   FeatureLDBRX,
 286                                                   Feature64Bit,
 287                                                   /* Feature64BitRegs, */
 288                                                   FeatureBPERMD,
 289                                                   FeatureExtDiv,
 290                                                   FeatureMFTB,
 291                                                   DeprecatedDST,
 292                                                   FeatureTwoConstNR,
 293                                                   FeatureUnalignedFloats];
 294   list<SubtargetFeature> P7SpecificFeatures = [];
 295   list<SubtargetFeature> P7Features =
 296     !listconcat(P7InheritableFeatures, P7SpecificFeatures);
 297
 298   // Power8
 299   list<SubtargetFeature> P8AdditionalFeatures =
 300     [DirectivePwr8,
 301      FeatureP8Altivec,
 302      FeatureP8Vector,
 303      FeatureP8Crypto,
 304      FeatureHTM,
 305      FeatureDirectMove,
 306      FeatureICBT,
 307      FeaturePartwordAtomic,
 308      FeaturePredictableSelectIsExpensive
 309     ];
 310
 311   list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion,
 312                                                FeatureAddisLoadFusion];
 313   list<SubtargetFeature> P8InheritableFeatures =
 314     !listconcat(P7InheritableFeatures, P8AdditionalFeatures);
 315   list<SubtargetFeature> P8Features =
 316     !listconcat(P8InheritableFeatures, P8SpecificFeatures);
 317
 318   // Power9
 319   list<SubtargetFeature> P9AdditionalFeatures =
 320     [DirectivePwr9,
 321      FeatureP9Altivec,
 322      FeatureP9Vector,
 323      FeatureISA3_0,
 324      FeaturePredictableSelectIsExpensive
 325     ];
 326
 327   // Some features are unique to Power9 and there is no reason to assume
 328   // they will be part of any future CPUs. One example is the narrower
 329   // dispatch for vector operations than scalar ones. For the time being,
 330   // this list also includes scheduling-related features since we do not have
 331   // enough info to create custom scheduling strategies for future CPUs.
 332   list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits,
 333                                                FeaturePPCPreRASched,
 334                                                FeaturePPCPostRASched];
 335   list<SubtargetFeature> P9InheritableFeatures =
 336     !listconcat(P8InheritableFeatures, P9AdditionalFeatures);
 337   list<SubtargetFeature> P9Features =
 338     !listconcat(P9InheritableFeatures, P9SpecificFeatures);
 339
 340   // Power10
 341   // For P10 CPU we assume that all of the existing features from Power9
 342   // still exist with the exception of those we know are Power9 specific.
 343   list<SubtargetFeature> P10AdditionalFeatures =
 344     [DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
 345      FeaturePCRelativeMemops, FeatureP10Vector];
 346   list<SubtargetFeature> P10SpecificFeatures = [];
 347   list<SubtargetFeature> P10InheritableFeatures =
 348     !listconcat(P9InheritableFeatures, P10AdditionalFeatures);
 349   list<SubtargetFeature> P10Features =
 350     !listconcat(P10InheritableFeatures, P10SpecificFeatures);
 351
 352   // Future
 353   // For future CPU we assume that all of the existing features from Power10
 354   // still exist with the exception of those we know are Power10 specific.
 355   list<SubtargetFeature> FutureAdditionalFeatures = [];
 356   list<SubtargetFeature> FutureSpecificFeatures = [];
 357   list<SubtargetFeature> FutureInheritableFeatures =
 358     !listconcat(P10InheritableFeatures, FutureAdditionalFeatures);
 359   list<SubtargetFeature> FutureFeatures =
 360     !listconcat(FutureInheritableFeatures, FutureSpecificFeatures);
 361 }
 362
 363 // Note: Future features to add when support is extended to more
 364 // recent ISA levels:
 365 //
 366 // DFP          p6, p6x, p7        decimal floating-point instructions
 367 // POPCNTB      p5 through p7      popcntb and related instructions
 368
 369 //===----------------------------------------------------------------------===//
 370 // Classes used for relation maps.
 371 //===----------------------------------------------------------------------===//
 372 // RecFormRel - Filter class used to relate non-record-form instructions with
 373 // their record-form variants.
 374 class RecFormRel;
 375
 376 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
 377 // FMA instruction forms with their corresponding factor-killing forms.
 378 class AltVSXFMARel {
 379   bit IsVSXFMAAlt = 0;
 380 }
 381
 382 //===----------------------------------------------------------------------===//
 383 // Relation Map Definitions.
 384 //===----------------------------------------------------------------------===//
 385
 386 def getRecordFormOpcode : InstrMapping {
 387   let FilterClass = "RecFormRel";
 388   // Instructions with the same BaseName and Interpretation64Bit values
 389   // form a row.
 390   let RowFields = ["BaseName", "Interpretation64Bit"];
 391   // Instructions with the same RC value form a column.
 392   let ColFields = ["RC"];
 393   // The key column are the non-record-form instructions.
 394   let KeyCol = ["0"];
 395   // Value columns RC=1
 396   let ValueCols = [["1"]];
 397 }
 398
 399 def getNonRecordFormOpcode : InstrMapping {
 400   let FilterClass = "RecFormRel";
 401   // Instructions with the same BaseName and Interpretation64Bit values
 402   // form a row.
 403   let RowFields = ["BaseName", "Interpretation64Bit"];
 404   // Instructions with the same RC value form a column.
 405   let ColFields = ["RC"];
 406   // The key column are the record-form instructions.
 407   let KeyCol = ["1"];
 408   // Value columns are RC=0
 409   let ValueCols = [["0"]];
 410 }
 411
 412 def getAltVSXFMAOpcode : InstrMapping {
 413   let FilterClass = "AltVSXFMARel";
 414   // Instructions with the same BaseName value form a row.
 415   let RowFields = ["BaseName"];
 416   // Instructions with the same IsVSXFMAAlt value form a column.
 417   let ColFields = ["IsVSXFMAAlt"];
 418   // The key column are the (default) addend-killing instructions.
 419   let KeyCol = ["0"];
 420   // Value columns IsVSXFMAAlt=1
 421   let ValueCols = [["1"]];
 422 }
 423
 424 //===----------------------------------------------------------------------===//
 425 // Register File Description
 426 //===----------------------------------------------------------------------===//
 427
 428 include "PPCRegisterInfo.td"
 429 include "PPCSchedule.td"
 430
 431 //===----------------------------------------------------------------------===//
 432 // PowerPC processors supported.
 433 //
 434
 435 def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
 436                                            FeatureMFTB]>;
 437 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
 438                                           FeatureFRES, FeatureFRSQRTE,
 439                                           FeatureICBT, FeatureBookE,
 440                                           FeatureMSYNC, FeatureMFTB]>;
 441 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
 442                                           FeatureFRES, FeatureFRSQRTE,
 443                                           FeatureICBT, FeatureBookE,
 444                                           FeatureMSYNC, FeatureMFTB]>;
 445 def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
 446 def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
 447                                        FeatureMFTB]>;
 448 def : Processor<"603", G3Itineraries, [Directive603,
 449                                        FeatureFRES, FeatureFRSQRTE,
 450                                        FeatureMFTB]>;
 451 def : Processor<"603e", G3Itineraries, [Directive603,
 452                                         FeatureFRES, FeatureFRSQRTE,
 453                                         FeatureMFTB]>;
 454 def : Processor<"603ev", G3Itineraries, [Directive603,
 455                                          FeatureFRES, FeatureFRSQRTE,
 456                                          FeatureMFTB]>;
 457 def : Processor<"604", G3Itineraries, [Directive604,
 458                                        FeatureFRES, FeatureFRSQRTE,
 459                                        FeatureMFTB]>;
 460 def : Processor<"604e", G3Itineraries, [Directive604,
 461                                         FeatureFRES, FeatureFRSQRTE,
 462                                         FeatureMFTB]>;
 463 def : Processor<"620", G3Itineraries, [Directive620,
 464                                        FeatureFRES, FeatureFRSQRTE,
 465                                        FeatureMFTB]>;
 466 def : Processor<"750", G4Itineraries, [Directive750,
 467                                        FeatureFRES, FeatureFRSQRTE,
 468                                        FeatureMFTB]>;
 469 def : Processor<"g3", G3Itineraries, [Directive750,
 470                                       FeatureFRES, FeatureFRSQRTE,
 471                                       FeatureMFTB]>;
 472 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
 473                                         FeatureFRES, FeatureFRSQRTE,
 474                                         FeatureMFTB]>;
 475 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
 476                                       FeatureFRES, FeatureFRSQRTE,
 477                                       FeatureMFTB]>;
 478 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
 479                                             FeatureFRES, FeatureFRSQRTE,
 480                                             FeatureMFTB]>;
 481 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
 482                                            FeatureFRES, FeatureFRSQRTE,
 483                                            FeatureMFTB]>;
 484
 485 def : ProcessorModel<"970", G5Model,
 486                   [Directive970, FeatureAltivec,
 487                    FeatureMFOCRF, FeatureFSqrt,
 488                    FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
 489                    Feature64Bit /*, Feature64BitRegs */,
 490                    FeatureMFTB]>;
 491 def : ProcessorModel<"g5", G5Model,
 492                   [Directive970, FeatureAltivec,
 493                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 494                    FeatureFRES, FeatureFRSQRTE,
 495                    Feature64Bit /*, Feature64BitRegs */,
 496                    FeatureMFTB, DeprecatedDST]>;
 497 def : ProcessorModel<"e500", PPCE500Model,
 498                   [DirectiveE500,
 499                    FeatureICBT, FeatureBookE,
 500                    FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>;
 501 def : ProcessorModel<"e500mc", PPCE500mcModel,
 502                   [DirectiveE500mc,
 503                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
 504                    FeatureISEL, FeatureMFTB]>;
 505 def : ProcessorModel<"e5500", PPCE5500Model,
 506                   [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
 507                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
 508                    FeatureISEL, FeatureMFTB]>;
 509 def : ProcessorModel<"a2", PPCA2Model,
 510                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
 511                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 512                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 513                    FeatureSTFIWX, FeatureLFIWAX,
 514                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 515                    FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
 516                    Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>;
 517 def : ProcessorModel<"a2q", PPCA2Model,
 518                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
 519                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 520                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 521                    FeatureSTFIWX, FeatureLFIWAX,
 522                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 523                    FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
 524                    Feature64Bit /*, Feature64BitRegs */, FeatureQPX,
 525                    FeatureMFTB]>;
 526 def : ProcessorModel<"pwr3", G5Model,
 527                   [DirectivePwr3, FeatureAltivec,
 528                    FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
 529                    FeatureSTFIWX, Feature64Bit]>;
 530 def : ProcessorModel<"pwr4", G5Model,
 531                   [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
 532                    FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
 533                    FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
 534 def : ProcessorModel<"pwr5", G5Model,
 535                   [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
 536                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 537                    FeatureFRSQRTE, FeatureFRSQRTES,
 538                    FeatureSTFIWX, Feature64Bit,
 539                    FeatureMFTB, DeprecatedDST]>;
 540 def : ProcessorModel<"pwr5x", G5Model,
 541                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 542                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 543                    FeatureFRSQRTE, FeatureFRSQRTES,
 544                    FeatureSTFIWX, FeatureFPRND, Feature64Bit,
 545                    FeatureMFTB, DeprecatedDST]>;
 546 def : ProcessorModel<"pwr6", G5Model,
 547                   [DirectivePwr6, FeatureAltivec,
 548                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 549                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 550                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
 551                    FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
 552                    FeatureMFTB, DeprecatedDST]>;
 553 def : ProcessorModel<"pwr6x", G5Model,
 554                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 555                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 556                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 557                    FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
 558                    FeatureFPRND, Feature64Bit,
 559                    FeatureMFTB, DeprecatedDST]>;
 560 def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;
 561 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
 562 def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;
 563 // No scheduler model yet.
 564 def : ProcessorModel<"pwr10", NoSchedModel, ProcessorFeatures.P10Features>;
 565 // No scheduler model for future CPU.
 566 def : ProcessorModel<"future", NoSchedModel,
 567                   ProcessorFeatures.FutureFeatures>;
 568 def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
 569                                        FeatureMFTB]>;
 570 def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
 571                                          FeatureMFTB]>;
 572 def : ProcessorModel<"ppc64", G5Model,
 573                   [Directive64, FeatureAltivec,
 574                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
 575                    FeatureFRSQRTE, FeatureSTFIWX,
 576                    Feature64Bit /*, Feature64BitRegs */,
 577                    FeatureMFTB]>;
 578 def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>;
 579
 580 //===----------------------------------------------------------------------===//
 581 // Calling Conventions
 582 //===----------------------------------------------------------------------===//
 583
 584 include "PPCCallingConv.td"
 585
 586 def PPCInstrInfo : InstrInfo {
 587   let isLittleEndianEncoding = 1;
 588
 589   // FIXME: Unset this when no longer needed!
 590   let decodePositionallyEncodedOperands = 1;
 591
 592   let noNamedPositionallyEncodedOperands = 1;
 593 }
 594
 595 def PPCAsmParser : AsmParser {
 596   let ShouldEmitMatchRegisterName = 0;
 597 }
 598
 599 def PPCAsmParserVariant : AsmParserVariant {
 600   int Variant = 0;
 601
 602   // We do not use hard coded registers in asm strings.  However, some
 603   // InstAlias definitions use immediate literals.  Set RegisterPrefix
 604   // so that those are not misinterpreted as registers.
 605   string RegisterPrefix = "%";
 606   string BreakCharacters = ".";
 607 }
 608
 609 def PPC : Target {
 610   // Information about the instructions.
 611   let InstructionSet = PPCInstrInfo;
 612
 613   let AssemblyParsers = [PPCAsmParser];
 614   let AssemblyParserVariants = [PPCAsmParserVariant];
 615   let AllowRegisterRenaming = 1;
 616 }
 617
 618 //===----------------------------------------------------------------------===//
 619 // Pfm Counters
 620 //===----------------------------------------------------------------------===//
 621
 622 include "PPCPfmCounters.td"