1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that PPC uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
17 #include "PPCInstrInfo.h"
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGNodes.h"
23 #include "llvm/CodeGen/TargetLowering.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/IR/Attributes.h"
26 #include "llvm/IR/CallingConv.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/InlineAsm.h"
29 #include "llvm/IR/Metadata.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/MachineValueType.h"
38 // When adding a NEW PPCISD node please add it to the correct position in
39 // the enum. The order of elements in this enum matters!
40 // Values that are added after this entry:
41 // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE
42 // are considered memory opcodes and are treated differently than entries
43 // that come before it. For example, ADD or MUL should be placed before
44 // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come
46 enum NodeType : unsigned {
47 // Start the numbering where the builtin ops and target ops leave off.
48 FIRST_NUMBER = ISD::BUILTIN_OP_END,
50 /// FSEL - Traditional three-operand fsel node.
54 /// FCFID - The FCFID instruction, taking an f64 operand and producing
55 /// and f64 value containing the FP representation of the integer that
56 /// was temporarily in the f64 operand.
59 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
60 /// unsigned integers and single-precision outputs.
61 FCFIDU, FCFIDS, FCFIDUS,
63 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
64 /// operand, producing an f64 value containing the integer representation
68 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
69 /// unsigned integers with round toward zero.
72 /// Floating-point-to-interger conversion instructions
73 FP_TO_UINT_IN_VSR, FP_TO_SINT_IN_VSR,
75 /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
76 /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
79 /// SExtVElems, takes an input vector of a smaller type and sign
80 /// extends to an output vector of a larger type.
83 /// Reciprocal estimate instructions (unary FP ops).
86 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
87 // three v4f32 operands and producing a v4f32 result.
90 /// VPERM - The PPC VPERM Instruction.
94 /// XXSPLT - The PPC VSX splat instructions
98 /// VECINSERT - The PPC vector insert instruction
102 /// XXREVERSE - The PPC VSX reverse instruction
106 /// VECSHL - The PPC vector shift left instruction
110 /// XXPERMDI - The PPC XXPERMDI instruction
114 /// The CMPB instruction (takes two operands of i32 or i64).
117 /// Hi/Lo - These represent the high and low 16-bit parts of a global
118 /// address respectively. These nodes have two operands, the first of
119 /// which must be a TargetGlobalAddress, and the second of which must be a
120 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
121 /// though these are usually folded into other nodes.
124 /// The following two target-specific nodes are used for calls through
125 /// function pointers in the 64-bit SVR4 ABI.
127 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
128 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
129 /// compute an allocation on the stack.
132 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
133 /// compute an offset from native SP to the address of the most recent
137 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
138 /// at function entry, used for PIC code.
141 /// These nodes represent PPC shifts.
143 /// For scalar types, only the last `n + 1` bits of the shift amounts
144 /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc.
145 /// for exact behaviors.
147 /// For vector types, only the last n bits are used. See vsld.
150 /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign
151 /// word and shift left immediate.
154 /// The combination of sra[wd]i and addze used to implemented signed
155 /// integer division by a power of 2. The first operand is the dividend,
156 /// and the second is the constant shift amount (representing the
160 /// CALL - A direct function call.
161 /// CALL_NOP is a call with the special NOP which follows 64-bit
162 /// SVR4 calls and 32-bit/64-bit AIX calls.
165 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
166 /// MTCTR instruction.
169 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
170 /// BCTRL instruction.
173 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
174 /// instruction and the TOC reload required on SVR4 PPC64.
177 /// Return with a flag operand, matched by 'blr'
180 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
181 /// This copies the bits corresponding to the specified CRREG into the
182 /// resultant GPR. Bits corresponding to other CR regs are undefined.
185 /// Direct move from a VSX register to a GPR
188 /// Direct move from a GPR to a VSX register (algebraic)
191 /// Direct move from a GPR to a VSX register (zero)
194 /// Direct move of 2 consecutive GPR to a VSX register.
197 /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and
198 /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is
199 /// unsupported for this target.
200 /// Merge 2 GPRs to a single SPE register.
203 /// Extract SPE register component, second argument is high or low.
206 /// Extract a subvector from signed integer vector and convert to FP.
207 /// It is primarily used to convert a (widened) illegal integer vector
208 /// type to a legal floating point vector type.
209 /// For example v2i32 -> widened to v4i32 -> v2f64
212 /// Extract a subvector from unsigned integer vector and convert to FP.
213 /// As with SINT_VEC_TO_FP, used for converting illegal types.
216 // FIXME: Remove these once the ANDI glue bug is fixed:
217 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
218 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
219 /// implement truncation of i32 or i64 to i1.
220 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
222 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
223 // target (returns (Lo, Hi)). It takes a chain operand.
226 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
229 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
232 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
233 /// instructions. For lack of better number, we use the opcode number
234 /// encoding for the OPC field to identify the compare. For example, 838
238 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
239 /// altivec VCMP*o instructions. For lack of better number, we use the
240 /// opcode number encoding for the OPC field to identify the compare. For
241 /// example, 838 is VCMPGTSH.
244 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
245 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
246 /// condition register to branch on, OPC is the branch opcode to use (e.g.
247 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
248 /// an optional input flag argument.
251 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
255 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
256 /// towards zero. Used only as part of the long double-to-int
257 /// conversion sequence.
260 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
263 /// TC_RETURN - A tail call return.
265 /// operand #1 callee (register or absolute)
266 /// operand #2 stack adjustment
267 /// operand #3 optional in flag
270 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
274 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
275 /// for non-position independent code on PPC32.
278 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
279 /// local dynamic TLS and position indendepent code on PPC32.
282 /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec
283 /// TLS model, produces an ADDIS8 instruction that adds the GOT
284 /// base to sym\@got\@tprel\@ha.
287 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
288 /// TLS model, produces a LD instruction with base register G8RReg
289 /// and offset sym\@got\@tprel\@l. This completes the addition that
290 /// finds the offset of "sym" relative to the thread pointer.
293 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
294 /// model, produces an ADD instruction that adds the contents of
295 /// G8RReg to the thread pointer. Symbol contains a relocation
296 /// sym\@tls which is to be replaced by the thread pointer and
297 /// identifies to the linker that the instruction is part of a
301 /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS
302 /// model, produces an ADDIS8 instruction that adds the GOT base
303 /// register to sym\@got\@tlsgd\@ha.
306 /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
307 /// model, produces an ADDI8 instruction that adds G8RReg to
308 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by
309 /// ADDIS_TLSGD_L_ADDR until after register assignment.
312 /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS
313 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by
314 /// ADDIS_TLSGD_L_ADDR until after register assignment.
317 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
318 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
319 /// register assignment.
322 /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS
323 /// model, produces an ADDIS8 instruction that adds the GOT base
324 /// register to sym\@got\@tlsld\@ha.
327 /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
328 /// model, produces an ADDI8 instruction that adds G8RReg to
329 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by
330 /// ADDIS_TLSLD_L_ADDR until after register assignment.
333 /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS
334 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by
335 /// ADDIS_TLSLD_L_ADDR until after register assignment.
338 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
339 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
340 /// following register assignment.
343 /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS
344 /// model, produces an ADDIS8 instruction that adds X3 to
348 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
349 /// model, produces an ADDI8 instruction that adds G8RReg to
350 /// sym\@got\@dtprel\@l.
353 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
354 /// during instruction selection to optimize a BUILD_VECTOR into
355 /// operations on splats. This is necessary to avoid losing these
356 /// optimizations due to constant folding.
359 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
360 /// operand identifies the operating system entry point.
363 /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
366 /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
367 /// history rolling buffer entry.
370 /// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
373 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
374 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
375 /// or stxvd2x instruction. The chain is necessary because the
376 /// sequence replaces a load and needs to provide the same number
380 /// An SDNode for swaps that are not associated with any loads/stores
381 /// and thereby have no chain.
384 /// An SDNode for Power9 vector absolute value difference.
385 /// operand #0 vector
386 /// operand #1 vector
387 /// operand #2 constant i32 0 or 1, to indicate whether needs to patch
388 /// the most significant bit for signed i32
390 /// Power9 VABSD* instructions are designed to support unsigned integer
391 /// vectors (byte/halfword/word), if we want to make use of them for signed
392 /// integer vectors, we have to flip their sign bits first. To flip sign bit
393 /// for byte/halfword integer vector would become inefficient, but for word
394 /// integer vector, we can leverage XVNEGSP to make it efficiently. eg:
395 /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000)
396 /// => VABSDUW((XVNEGSP a), (XVNEGSP b))
399 /// QVFPERM = This corresponds to the QPX qvfperm instruction.
402 /// QVGPCI = This corresponds to the QPX qvgpci instruction.
405 /// QVALIGNI = This corresponds to the QPX qvaligni instruction.
408 /// QVESPLATI = This corresponds to the QPX qvesplati instruction.
411 /// QBFLT = Access the underlying QPX floating-point boolean
415 /// Custom extend v4f32 to v2f64.
418 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
419 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
420 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
422 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
424 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
425 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
426 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
430 /// STFIWX - The STFIWX instruction. The first operand is an input token
431 /// chain, then an f64 value to store, then an address to store it to.
434 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
435 /// load which sign-extends from a 32-bit integer value into the
436 /// destination 64-bit register.
439 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
440 /// load which zero-extends from a 32-bit integer value into the
441 /// destination 64-bit register.
444 /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an
445 /// integer smaller than 64 bits into a VSR. The integer is zero-extended.
446 /// This can be used for converting loaded integers to floating point.
449 /// STXSIX - The STXSI[bh]X instruction. The first operand is an input
450 /// chain, then an f64 value to store, then an address to store it to,
451 /// followed by a byte-width for the store.
454 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
455 /// Maps directly to an lxvd2x instruction that will be followed by
459 /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a
460 /// v2f32 value into the lower half of a VSR register.
463 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
464 /// Maps directly to an stxvd2x instruction that will be preceded by
468 /// Store scalar integers from VSR.
471 /// QBRC, CHAIN = QVLFSb CHAIN, Ptr
472 /// The 4xf32 load used for v4i1 constants.
475 /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes
476 /// except they ensure that the compare input is zero-extended for
477 /// sub-word versions because the atomic loads zero-extend.
478 ATOMIC_CMP_SWAP_8, ATOMIC_CMP_SWAP_16,
480 /// GPRC = TOC_ENTRY GA, TOC
481 /// Loads the entry for GA from the TOC, where the TOC base is given by
482 /// the last operand.
486 } // end namespace PPCISD
488 /// Define some predicates that are used for node matching.
491 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
492 /// VPKUHUM instruction.
493 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
496 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
497 /// VPKUWUM instruction.
498 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
501 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
502 /// VPKUDUM instruction.
503 bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
506 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
507 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
508 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
509 unsigned ShuffleKind, SelectionDAG &DAG);
511 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
512 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
513 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
514 unsigned ShuffleKind, SelectionDAG &DAG);
516 /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for
517 /// a VMRGEW or VMRGOW instruction
518 bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
519 unsigned ShuffleKind, SelectionDAG &DAG);
520 /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable
521 /// for a XXSLDWI instruction.
522 bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
523 bool &Swap, bool IsLE);
525 /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable
526 /// for a XXBRH instruction.
527 bool isXXBRHShuffleMask(ShuffleVectorSDNode *N);
529 /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable
530 /// for a XXBRW instruction.
531 bool isXXBRWShuffleMask(ShuffleVectorSDNode *N);
533 /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable
534 /// for a XXBRD instruction.
535 bool isXXBRDShuffleMask(ShuffleVectorSDNode *N);
537 /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable
538 /// for a XXBRQ instruction.
539 bool isXXBRQShuffleMask(ShuffleVectorSDNode *N);
541 /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable
542 /// for a XXPERMDI instruction.
543 bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
544 bool &Swap, bool IsLE);
546 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
547 /// shift amount, otherwise return -1.
548 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
551 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
552 /// specifies a splat of a single element that is suitable for input to
553 /// VSPLTB/VSPLTH/VSPLTW.
554 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
556 /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by
557 /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any
558 /// shuffle of v4f32/v4i32 vectors that just inserts one element from one
559 /// vector into the other. This function will also set a couple of
560 /// output parameters for how much the source vector needs to be shifted and
561 /// what byte number needs to be specified for the instruction to put the
562 /// element in the desired location of the target vector.
563 bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
564 unsigned &InsertAtByte, bool &Swap, bool IsLE);
566 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
567 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
568 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
570 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
571 /// formed by using a vspltis[bhw] instruction of the specified element
572 /// size, return the constant being splatted. The ByteSize field indicates
573 /// the number of bytes of each element [124] -> [bhw].
574 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
576 /// If this is a qvaligni shuffle mask, return the shift
577 /// amount, otherwise return -1.
578 int isQVALIGNIShuffleMask(SDNode *N);
580 } // end namespace PPC
582 class PPCTargetLowering : public TargetLowering {
583 const PPCSubtarget &Subtarget;
586 explicit PPCTargetLowering(const PPCTargetMachine &TM,
587 const PPCSubtarget &STI);
589 /// getTargetNodeName() - This method returns the name of a target specific
591 const char *getTargetNodeName(unsigned Opcode) const override;
593 bool isSelectSupported(SelectSupportKind Kind) const override {
594 // PowerPC does not support scalar condition selects on vectors.
595 return (Kind != SelectSupportKind::ScalarCondVectorVal);
598 /// getPreferredVectorAction - The code we generate when vector types are
599 /// legalized by promoting the integer element type is often much worse
600 /// than code we generate if we widen the type for applicable vector types.
601 /// The issue with promoting is that the vector is scalaraized, individual
602 /// elements promoted and then the vector is rebuilt. So say we load a pair
603 /// of v4i8's and shuffle them. This will turn into a mess of 8 extending
604 /// loads, moves back into VSR's (or memory ops if we don't have moves) and
605 /// then the VPERM for the shuffle. All in all a very slow sequence.
606 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
608 if (VT.getScalarSizeInBits() % 8 == 0)
609 return TypeWidenVector;
610 return TargetLoweringBase::getPreferredVectorAction(VT);
613 bool useSoftFloat() const override;
617 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
621 bool isCheapToSpeculateCttz() const override {
625 bool isCheapToSpeculateCtlz() const override {
629 bool isCtlzFast() const override {
633 bool hasAndNotCompare(SDValue) const override {
637 bool preferIncOfAddToSubOfNot(EVT VT) const override;
639 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
640 return VT.isScalarInteger();
643 bool supportSplitCSR(MachineFunction *MF) const override {
645 MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
646 MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
649 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
651 void insertCopiesSplitCSR(
652 MachineBasicBlock *Entry,
653 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
655 /// getSetCCResultType - Return the ISD::SETCC ValueType
656 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
657 EVT VT) const override;
659 /// Return true if target always beneficiates from combining into FMA for a
660 /// given value type. This must typically return false on targets where FMA
661 /// takes more cycles to execute than FADD.
662 bool enableAggressiveFMAFusion(EVT VT) const override;
664 /// getPreIndexedAddressParts - returns true by value, base pointer and
665 /// offset pointer and addressing mode by reference if the node's address
666 /// can be legally represented as pre-indexed load / store address.
667 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
669 ISD::MemIndexedMode &AM,
670 SelectionDAG &DAG) const override;
672 /// SelectAddressEVXRegReg - Given the specified addressed, check to see if
673 /// it can be more efficiently represented as [r+imm].
674 bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index,
675 SelectionDAG &DAG) const;
677 /// SelectAddressRegReg - Given the specified addressed, check to see if it
678 /// can be more efficiently represented as [r+imm]. If \p EncodingAlignment
679 /// is non-zero, only accept displacement which is not suitable for [r+imm].
680 /// Returns false if it can be represented by [r+imm], which are preferred.
681 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
683 unsigned EncodingAlignment = 0) const;
685 /// SelectAddressRegImm - Returns true if the address N can be represented
686 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
687 /// is not better represented as reg+reg. If \p EncodingAlignment is
688 /// non-zero, only accept displacements suitable for instruction encoding
689 /// requirement, i.e. multiples of 4 for DS form.
690 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
692 unsigned EncodingAlignment) const;
694 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
695 /// represented as an indexed [r+r] operation.
696 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
697 SelectionDAG &DAG) const;
699 Sched::Preference getSchedulingPreference(SDNode *N) const override;
701 /// LowerOperation - Provide custom lowering hooks for some operations.
703 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
705 /// ReplaceNodeResults - Replace the results of node with an illegal result
706 /// type with new values built out of custom code.
708 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
709 SelectionDAG &DAG) const override;
711 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
712 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
714 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
716 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
717 SmallVectorImpl<SDNode *> &Created) const override;
719 unsigned getRegisterByName(const char* RegName, EVT VT,
720 SelectionDAG &DAG) const override;
722 void computeKnownBitsForTargetNode(const SDValue Op,
724 const APInt &DemandedElts,
725 const SelectionDAG &DAG,
726 unsigned Depth = 0) const override;
728 unsigned getPrefLoopAlignment(MachineLoop *ML) const override;
730 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
734 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
735 AtomicOrdering Ord) const override;
736 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
737 AtomicOrdering Ord) const override;
740 EmitInstrWithCustomInserter(MachineInstr &MI,
741 MachineBasicBlock *MBB) const override;
742 MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI,
743 MachineBasicBlock *MBB,
746 unsigned CmpOpcode = 0,
747 unsigned CmpPred = 0) const;
748 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI,
749 MachineBasicBlock *MBB,
752 unsigned CmpOpcode = 0,
753 unsigned CmpPred = 0) const;
755 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
756 MachineBasicBlock *MBB) const;
758 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
759 MachineBasicBlock *MBB) const;
761 ConstraintType getConstraintType(StringRef Constraint) const override;
763 /// Examine constraint string and operand type and determine a weight value.
764 /// The operand object must already have been set up with the operand type.
765 ConstraintWeight getSingleConstraintMatchWeight(
766 AsmOperandInfo &info, const char *constraint) const override;
768 std::pair<unsigned, const TargetRegisterClass *>
769 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
770 StringRef Constraint, MVT VT) const override;
772 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
773 /// function arguments in the caller parameter area. This is the actual
774 /// alignment, not its logarithm.
775 unsigned getByValTypeAlignment(Type *Ty,
776 const DataLayout &DL) const override;
778 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
779 /// vector. If it is invalid, don't add anything to Ops.
780 void LowerAsmOperandForConstraint(SDValue Op,
781 std::string &Constraint,
782 std::vector<SDValue> &Ops,
783 SelectionDAG &DAG) const override;
786 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
787 if (ConstraintCode == "es")
788 return InlineAsm::Constraint_es;
789 else if (ConstraintCode == "o")
790 return InlineAsm::Constraint_o;
791 else if (ConstraintCode == "Q")
792 return InlineAsm::Constraint_Q;
793 else if (ConstraintCode == "Z")
794 return InlineAsm::Constraint_Z;
795 else if (ConstraintCode == "Zy")
796 return InlineAsm::Constraint_Zy;
797 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
800 /// isLegalAddressingMode - Return true if the addressing mode represented
801 /// by AM is legal for this target, for a load/store of the specified type.
802 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
803 Type *Ty, unsigned AS,
804 Instruction *I = nullptr) const override;
806 /// isLegalICmpImmediate - Return true if the specified immediate is legal
807 /// icmp immediate, that is the target has icmp instructions which can
808 /// compare a register against the immediate without having to materialize
809 /// the immediate into a register.
810 bool isLegalICmpImmediate(int64_t Imm) const override;
812 /// isLegalAddImmediate - Return true if the specified immediate is legal
813 /// add immediate, that is the target has add instructions which can
814 /// add a register and the immediate without having to materialize
815 /// the immediate into a register.
816 bool isLegalAddImmediate(int64_t Imm) const override;
818 /// isTruncateFree - Return true if it's free to truncate a value of
819 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
820 /// register X1 to i32 by referencing its sub-register R1.
821 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
822 bool isTruncateFree(EVT VT1, EVT VT2) const override;
824 bool isZExtFree(SDValue Val, EVT VT2) const override;
826 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
828 /// Returns true if it is beneficial to convert a load of a constant
829 /// to just the constant itself.
830 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
831 Type *Ty) const override;
833 bool convertSelectOfConstantsToMath(EVT VT) const override {
837 // Returns true if the address of the global is stored in TOC entry.
838 bool isAccessedAsGotIndirect(SDValue N) const;
840 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
842 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
845 unsigned Intrinsic) const override;
847 /// getOptimalMemOpType - Returns the target specific optimal type for load
848 /// and store operations as a result of memset, memcpy, and memmove
849 /// lowering. If DstAlign is zero that means it's safe to destination
850 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
851 /// means there isn't a need to check it against alignment requirement,
852 /// probably because the source does not need to be loaded. If 'IsMemset' is
853 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
854 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
855 /// source is constant so it does not need to be loaded.
856 /// It returns EVT::Other if the type should be determined using generic
857 /// target-independent logic.
859 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
860 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
861 const AttributeList &FuncAttributes) const override;
863 /// Is unaligned memory access allowed for the given type, and is it fast
864 /// relative to software emulation.
865 bool allowsMisalignedMemoryAccesses(
866 EVT VT, unsigned AddrSpace, unsigned Align = 1,
867 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
868 bool *Fast = nullptr) const override;
870 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
871 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
872 /// expanded to FMAs when this method returns true, otherwise fmuladd is
873 /// expanded to fmul + fadd.
874 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
876 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
878 // Should we expand the build vector with shuffles?
880 shouldExpandBuildVectorWithShuffles(EVT VT,
881 unsigned DefinedValues) const override;
883 /// createFastISel - This method returns a target-specific FastISel object,
884 /// or null if the target does not support "fast" instruction selection.
885 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
886 const TargetLibraryInfo *LibInfo) const override;
888 /// Returns true if an argument of type Ty needs to be passed in a
889 /// contiguous block of registers in calling convention CallConv.
890 bool functionArgumentNeedsConsecutiveRegisters(
891 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
892 // We support any array type as "consecutive" block in the parameter
893 // save area. The element type defines the alignment requirement and
894 // whether the argument should go in GPRs, FPRs, or VRs if available.
896 // Note that clang uses this capability both to implement the ELFv2
897 // homogeneous float/vector aggregate ABI, and to avoid having to use
898 // "byval" when passing aggregates that might fully fit in registers.
899 return Ty->isArrayTy();
902 /// If a physical register, this returns the register that receives the
903 /// exception address on entry to an EH pad.
905 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
907 /// If a physical register, this returns the register that receives the
908 /// exception typeid on entry to a landing pad.
910 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
912 /// Override to support customized stack guard loading.
913 bool useLoadStackGuardNode() const override;
914 void insertSSPDeclarations(Module &M) const override;
916 bool isFPImmLegal(const APFloat &Imm, EVT VT,
917 bool ForCodeSize) const override;
919 unsigned getJumpTableEncoding() const override;
920 bool isJumpTableRelative() const override;
921 SDValue getPICJumpTableRelocBase(SDValue Table,
922 SelectionDAG &DAG) const override;
923 const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
925 MCContext &Ctx) const override;
928 struct ReuseLoadInfo {
932 MachinePointerInfo MPI;
933 bool IsDereferenceable = false;
934 bool IsInvariant = false;
935 unsigned Alignment = 0;
937 const MDNode *Ranges = nullptr;
939 ReuseLoadInfo() = default;
941 MachineMemOperand::Flags MMOFlags() const {
942 MachineMemOperand::Flags F = MachineMemOperand::MONone;
943 if (IsDereferenceable)
944 F |= MachineMemOperand::MODereferenceable;
946 F |= MachineMemOperand::MOInvariant;
951 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
952 // Addrspacecasts are always noops.
956 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
958 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;
959 void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
960 SelectionDAG &DAG) const;
962 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
963 SelectionDAG &DAG, const SDLoc &dl) const;
964 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
965 const SDLoc &dl) const;
967 bool directMoveIsProfitable(const SDValue &Op) const;
968 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
969 const SDLoc &dl) const;
971 SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
972 const SDLoc &dl) const;
974 SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const;
976 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
977 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
980 IsEligibleForTailCallOptimization(SDValue Callee,
981 CallingConv::ID CalleeCC,
983 const SmallVectorImpl<ISD::InputArg> &Ins,
984 SelectionDAG& DAG) const;
987 IsEligibleForTailCallOptimization_64SVR4(
989 CallingConv::ID CalleeCC,
990 ImmutableCallSite CS,
992 const SmallVectorImpl<ISD::OutputArg> &Outs,
993 const SmallVectorImpl<ISD::InputArg> &Ins,
994 SelectionDAG& DAG) const;
996 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff,
997 SDValue Chain, SDValue &LROpOut,
999 const SDLoc &dl) const;
1001 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1002 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1003 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1004 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1005 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1006 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1007 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1008 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1009 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1010 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1011 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1012 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1013 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
1014 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
1015 SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1016 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1017 SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
1018 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
1019 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
1020 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1021 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
1022 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
1023 const SDLoc &dl) const;
1024 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1025 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1026 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1027 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1028 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
1029 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1030 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
1031 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1032 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1033 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1034 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
1035 SDValue LowerREM(SDValue Op, SelectionDAG &DAG) const;
1036 SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
1037 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
1038 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1039 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
1040 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
1041 SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
1042 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1044 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
1045 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
1047 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1048 CallingConv::ID CallConv, bool isVarArg,
1049 const SmallVectorImpl<ISD::InputArg> &Ins,
1050 const SDLoc &dl, SelectionDAG &DAG,
1051 SmallVectorImpl<SDValue> &InVals) const;
1052 SDValue FinishCall(CallingConv::ID CallConv, const SDLoc &dl,
1053 bool isTailCall, bool isVarArg, bool isPatchPoint,
1054 bool hasNest, SelectionDAG &DAG,
1055 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
1056 SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
1057 SDValue &Callee, int SPDiff, unsigned NumBytes,
1058 const SmallVectorImpl<ISD::InputArg> &Ins,
1059 SmallVectorImpl<SDValue> &InVals,
1060 ImmutableCallSite CS) const;
1063 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1064 const SmallVectorImpl<ISD::InputArg> &Ins,
1065 const SDLoc &dl, SelectionDAG &DAG,
1066 SmallVectorImpl<SDValue> &InVals) const override;
1068 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
1069 SmallVectorImpl<SDValue> &InVals) const override;
1071 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1073 const SmallVectorImpl<ISD::OutputArg> &Outs,
1074 LLVMContext &Context) const override;
1076 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1077 const SmallVectorImpl<ISD::OutputArg> &Outs,
1078 const SmallVectorImpl<SDValue> &OutVals,
1079 const SDLoc &dl, SelectionDAG &DAG) const override;
1081 SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
1082 SelectionDAG &DAG, SDValue ArgVal,
1083 const SDLoc &dl) const;
1085 SDValue LowerFormalArguments_Darwin(
1086 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1087 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1088 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1089 SDValue LowerFormalArguments_64SVR4(
1090 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1091 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1092 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1093 SDValue LowerFormalArguments_32SVR4(
1094 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1095 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1096 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1098 SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
1099 SDValue CallSeqStart,
1100 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1101 const SDLoc &dl) const;
1103 SDValue LowerCall_Darwin(SDValue Chain, SDValue Callee,
1104 CallingConv::ID CallConv, bool isVarArg,
1105 bool isTailCall, bool isPatchPoint,
1106 const SmallVectorImpl<ISD::OutputArg> &Outs,
1107 const SmallVectorImpl<SDValue> &OutVals,
1108 const SmallVectorImpl<ISD::InputArg> &Ins,
1109 const SDLoc &dl, SelectionDAG &DAG,
1110 SmallVectorImpl<SDValue> &InVals,
1111 ImmutableCallSite CS) const;
1112 SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee,
1113 CallingConv::ID CallConv, bool isVarArg,
1114 bool isTailCall, bool isPatchPoint,
1115 const SmallVectorImpl<ISD::OutputArg> &Outs,
1116 const SmallVectorImpl<SDValue> &OutVals,
1117 const SmallVectorImpl<ISD::InputArg> &Ins,
1118 const SDLoc &dl, SelectionDAG &DAG,
1119 SmallVectorImpl<SDValue> &InVals,
1120 ImmutableCallSite CS) const;
1121 SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee,
1122 CallingConv::ID CallConv, bool isVarArg,
1123 bool isTailCall, bool isPatchPoint,
1124 const SmallVectorImpl<ISD::OutputArg> &Outs,
1125 const SmallVectorImpl<SDValue> &OutVals,
1126 const SmallVectorImpl<ISD::InputArg> &Ins,
1127 const SDLoc &dl, SelectionDAG &DAG,
1128 SmallVectorImpl<SDValue> &InVals,
1129 ImmutableCallSite CS) const;
1130 SDValue LowerCall_AIX(SDValue Chain, SDValue Callee,
1131 CallingConv::ID CallConv, bool isVarArg,
1132 bool isTailCall, bool isPatchPoint,
1133 const SmallVectorImpl<ISD::OutputArg> &Outs,
1134 const SmallVectorImpl<SDValue> &OutVals,
1135 const SmallVectorImpl<ISD::InputArg> &Ins,
1136 const SDLoc &dl, SelectionDAG &DAG,
1137 SmallVectorImpl<SDValue> &InVals,
1138 ImmutableCallSite CS) const;
1140 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1141 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1142 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
1144 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
1145 SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const;
1146 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
1147 SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const;
1148 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
1149 SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
1150 SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
1151 SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
1152 SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const;
1153 SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const;
1154 SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
1155 SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
1156 SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const;
1157 SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const;
1159 /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
1160 /// SETCC with integer subtraction when (1) there is a legal way of doing it
1161 /// (2) keeping the result of comparison in GPR has performance benefit.
1162 SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const;
1164 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1165 int &RefinementSteps, bool &UseOneConstNR,
1166 bool Reciprocal) const override;
1167 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1168 int &RefinementSteps) const override;
1169 unsigned combineRepeatedFPDivisors() const override;
1172 combineElementTruncationToVectorTruncation(SDNode *N,
1173 DAGCombinerInfo &DCI) const;
1175 /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be
1176 /// handled by the VINSERTH instruction introduced in ISA 3.0. This is
1177 /// essentially any shuffle of v8i16 vectors that just inserts one element
1178 /// from one vector into the other.
1179 SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1181 /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be
1182 /// handled by the VINSERTB instruction introduced in ISA 3.0. This is
1183 /// essentially v16i8 vector version of VINSERTH.
1184 SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1186 // Return whether the call instruction can potentially be optimized to a
1187 // tail call. This will cause the optimizers to attempt to move, or
1188 // duplicate return instructions to help enable tail call optimizations.
1189 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1190 bool hasBitPreservingFPLogic(EVT VT) const override;
1191 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
1192 }; // end class PPCTargetLowering
1196 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
1197 const TargetLibraryInfo *LibInfo);
1199 } // end namespace PPC
1201 bool isIntS16Immediate(SDNode *N, int16_t &Imm);
1202 bool isIntS16Immediate(SDValue Op, int16_t &Imm);
1204 } // end namespace llvm
1206 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H