1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 // PowerPC instruction formats
13 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
16 field bits<32> SoftFail = 0;
19 bit PPC64 = 0; // Default value, override with isPPC64
21 let Namespace = "PPC";
22 let Inst{0-5} = opcode;
23 let OutOperandList = OOL;
24 let InOperandList = IOL;
25 let AsmString = asmstr;
28 bits<1> PPC970_First = 0;
29 bits<1> PPC970_Single = 0;
30 bits<1> PPC970_Cracked = 0;
31 bits<3> PPC970_Unit = 0;
33 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
34 /// these must be reflected there! See comments there for what these are.
35 let TSFlags{0} = PPC970_First;
36 let TSFlags{1} = PPC970_Single;
37 let TSFlags{2} = PPC970_Cracked;
38 let TSFlags{5-3} = PPC970_Unit;
40 // Indicate that this instruction is of type X-Form Load or Store
41 bits<1> XFormMemOp = 0;
42 let TSFlags{7} = XFormMemOp;
44 // Fields used for relation models.
47 // For cases where multiple instruction definitions really represent the
48 // same underlying instruction but with one definition for 64-bit arguments
49 // and one for 32-bit arguments, this bit breaks the degeneracy between
50 // the two forms and allows TableGen to generate mapping tables.
51 bit Interpretation64Bit = 0;
54 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
55 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
56 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
57 class PPC970_MicroCode;
59 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
60 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
61 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
62 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
63 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
64 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
65 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
66 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
68 class XFormMemOp { bits<1> XFormMemOp = 1; }
70 // Two joined instructions; used to emit two adjacent instructions as one.
71 // The itinerary from the first instruction is used for scheduling and
73 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
77 field bits<64> SoftFail = 0;
80 bit PPC64 = 0; // Default value, override with isPPC64
82 let Namespace = "PPC";
83 let Inst{0-5} = opcode1;
84 let Inst{32-37} = opcode2;
85 let OutOperandList = OOL;
86 let InOperandList = IOL;
87 let AsmString = asmstr;
90 bits<1> PPC970_First = 0;
91 bits<1> PPC970_Single = 0;
92 bits<1> PPC970_Cracked = 0;
93 bits<3> PPC970_Unit = 0;
95 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
96 /// these must be reflected there! See comments there for what these are.
97 let TSFlags{0} = PPC970_First;
98 let TSFlags{1} = PPC970_Single;
99 let TSFlags{2} = PPC970_Cracked;
100 let TSFlags{5-3} = PPC970_Unit;
102 // Fields used for relation models.
103 string BaseName = "";
104 bit Interpretation64Bit = 0;
107 // Base class for all X-Form memory instructions
108 class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr,
110 :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp;
113 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
114 InstrItinClass itin, list<dag> pattern>
115 : I<opcode, OOL, IOL, asmstr, itin> {
116 let Pattern = pattern;
125 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
126 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
127 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
132 let BI{0-1} = BIBO{5-6};
133 let BI{2-4} = CR{0-2};
135 let Inst{6-10} = BIBO{4-0};
136 let Inst{11-15} = BI;
137 let Inst{16-29} = BD;
142 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
144 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
150 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
151 dag OOL, dag IOL, string asmstr>
152 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
156 let Inst{11-15} = bi;
157 let Inst{16-29} = BD;
162 class BForm_3<bits<6> opcode, bit aa, bit lk,
163 dag OOL, dag IOL, string asmstr>
164 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
170 let Inst{11-15} = BI;
171 let Inst{16-29} = BD;
176 class BForm_3_at<bits<6> opcode, bit aa, bit lk,
177 dag OOL, dag IOL, string asmstr>
178 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
184 let Inst{6-8} = BO{4-2};
186 let Inst{11-15} = BI;
187 let Inst{16-29} = BD;
192 class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
193 dag OOL, dag IOL, string asmstr>
194 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
199 let Inst{11-15} = BI;
200 let Inst{16-29} = BD;
206 class SCForm<bits<6> opcode, bits<1> xo,
207 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
209 : I<opcode, OOL, IOL, asmstr, itin> {
212 let Pattern = pattern;
214 let Inst{20-26} = LEV;
219 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
220 InstrItinClass itin, list<dag> pattern>
221 : I<opcode, OOL, IOL, asmstr, itin> {
226 let Pattern = pattern;
233 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
234 InstrItinClass itin, list<dag> pattern>
235 : I<opcode, OOL, IOL, asmstr, itin> {
239 let Pattern = pattern;
242 let Inst{11-15} = Addr{20-16}; // Base Reg
243 let Inst{16-31} = Addr{15-0}; // Displacement
246 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
247 InstrItinClass itin, list<dag> pattern>
248 : I<opcode, OOL, IOL, asmstr, itin> {
253 let Pattern = pattern;
261 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
262 InstrItinClass itin, list<dag> pattern>
263 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
265 // Even though ADDIC_rec does not really have an RC bit, provide
266 // the declaration of one here so that isRecordForm has something to set.
270 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
271 InstrItinClass itin, list<dag> pattern>
272 : I<opcode, OOL, IOL, asmstr, itin> {
276 let Pattern = pattern;
283 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
284 InstrItinClass itin, list<dag> pattern>
285 : I<opcode, OOL, IOL, asmstr, itin> {
290 let Pattern = pattern;
297 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
298 InstrItinClass itin, list<dag> pattern>
299 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
304 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
305 string asmstr, InstrItinClass itin,
307 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
313 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
314 dag OOL, dag IOL, string asmstr,
315 InstrItinClass itin, list<dag> pattern>
316 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
320 let Pattern = pattern;
328 let Inst{43-47} = Addr{20-16}; // Base Reg
329 let Inst{48-63} = Addr{15-0}; // Displacement
332 // This is used to emit BL8+NOP.
333 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
334 dag OOL, dag IOL, string asmstr,
335 InstrItinClass itin, list<dag> pattern>
336 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
337 OOL, IOL, asmstr, itin, pattern> {
342 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
344 : I<opcode, OOL, IOL, asmstr, itin> {
353 let Inst{11-15} = RA;
357 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
359 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
363 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
365 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
367 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
369 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
375 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
376 InstrItinClass itin, list<dag> pattern>
377 : I<opcode, OOL, IOL, asmstr, itin> {
381 let Pattern = pattern;
383 let Inst{6-10} = RST;
384 let Inst{11-15} = DS_RA{18-14}; // Register #
385 let Inst{16-29} = DS_RA{13-0}; // Displacement.
386 let Inst{30-31} = xo;
389 // ISA V3.0B 1.6.6 DX-Form
390 class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
391 InstrItinClass itin, list<dag> pattern>
392 : I<opcode, OOL, IOL, asmstr, itin> {
396 let Pattern = pattern;
399 let Inst{11-15} = D{5-1}; // d1
400 let Inst{16-25} = D{15-6}; // d0
401 let Inst{26-30} = xo;
402 let Inst{31} = D{0}; // d2
405 // DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO]
406 class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
407 string asmstr, InstrItinClass itin, list<dag> pattern>
408 : I<opcode, OOL, IOL, asmstr, itin> {
412 let Pattern = pattern;
414 let Inst{6-10} = XT{4-0};
415 let Inst{11-15} = DS_RA{16-12}; // Register #
416 let Inst{16-27} = DS_RA{11-0}; // Displacement.
417 let Inst{28} = XT{5};
418 let Inst{29-31} = xo;
422 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
423 InstrItinClass itin, list<dag> pattern>
424 : I<opcode, OOL, IOL, asmstr, itin> {
429 let Pattern = pattern;
431 bit RC = 0; // set by isRecordForm
433 let Inst{6-10} = RST;
436 let Inst{21-30} = xo;
440 class XForm_base_r3xo_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
441 string asmstr, InstrItinClass itin,
443 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp;
445 class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr,
446 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> {
450 class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
452 : I<opcode, OOL, IOL, asmstr, itin> {
453 let Inst{21-30} = xo;
456 // This is the same as XForm_base_r3xo, but the first two operands are swapped
457 // when code is emitted.
458 class XForm_base_r3xo_swapped
459 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
461 : I<opcode, OOL, IOL, asmstr, itin> {
466 bit RC = 0; // set by isRecordForm
468 let Inst{6-10} = RST;
471 let Inst{21-30} = xo;
476 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
477 InstrItinClass itin, list<dag> pattern>
478 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
480 class XForm_1_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
481 InstrItinClass itin, list<dag> pattern>
482 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
484 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
485 InstrItinClass itin, list<dag> pattern>
486 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
490 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
491 InstrItinClass itin, list<dag> pattern>
492 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
497 class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
498 InstrItinClass itin, list<dag> pattern>
499 : I<opcode, OOL, IOL, asmstr, itin> {
504 let Pattern = pattern;
506 let Inst{6-10} = RST;
509 let Inst{21-30} = xo;
513 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
514 InstrItinClass itin, list<dag> pattern>
515 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
516 let Pattern = pattern;
519 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
520 InstrItinClass itin, list<dag> pattern>
521 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
523 class XForm_8_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
524 InstrItinClass itin, list<dag> pattern>
525 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
527 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
528 InstrItinClass itin, list<dag> pattern>
529 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
530 let Pattern = pattern;
533 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
534 InstrItinClass itin, list<dag> pattern>
535 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
537 let Pattern = pattern;
540 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
542 : I<opcode, OOL, IOL, asmstr, itin> {
551 let Inst{11-15} = RA;
552 let Inst{16-20} = RB;
553 let Inst{21-30} = xo;
557 class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
559 : I<opcode, OOL, IOL, asmstr, itin> {
566 let Inst{11-15} = RA;
567 let Inst{16-20} = RB;
568 let Inst{21-30} = xo;
572 class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
574 : I<opcode, OOL, IOL, asmstr, itin> {
579 let Inst{12-15} = SR;
580 let Inst{21-30} = xo;
583 class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
585 : I<opcode, OOL, IOL, asmstr, itin> {
589 let Inst{21-30} = xo;
592 class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
594 : I<opcode, OOL, IOL, asmstr, itin> {
599 let Inst{16-20} = RB;
600 let Inst{21-30} = xo;
603 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
605 : I<opcode, OOL, IOL, asmstr, itin> {
611 let Inst{21-30} = xo;
614 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
616 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
620 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
622 : I<opcode, OOL, IOL, asmstr, itin> {
629 let Inst{11-15} = FRA;
630 let Inst{16-20} = FRB;
631 let Inst{21-30} = xo;
635 class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
637 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin > {
642 class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
643 InstrItinClass itin, list<dag> pattern>
644 : I<opcode, OOL, IOL, asmstr, itin> {
649 let Pattern = pattern;
651 let Inst{6-10} = FRT;
652 let Inst{11-15} = FRA;
653 let Inst{16-20} = FRB;
654 let Inst{21-30} = xo;
658 class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
659 InstrItinClass itin, list<dag> pattern>
660 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
664 class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr,
665 InstrItinClass itin, list<dag> pattern>
666 : I<opcode, OOL, IOL, asmstr, itin> {
672 let Pattern = pattern;
674 let Inst{6-10} = FRT;
675 let Inst{11-15} = FRA;
676 let Inst{16-20} = FRB;
677 let Inst{21-24} = tttt;
678 let Inst{25-30} = xo;
682 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
683 InstrItinClass itin, list<dag> pattern>
684 : I<opcode, OOL, IOL, asmstr, itin> {
685 let Pattern = pattern;
689 let Inst{21-30} = xo;
693 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
694 string asmstr, InstrItinClass itin, list<dag> pattern>
695 : I<opcode, OOL, IOL, asmstr, itin> {
698 let Pattern = pattern;
703 let Inst{21-30} = xo;
707 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
708 string asmstr, InstrItinClass itin, list<dag> pattern>
709 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
713 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
714 InstrItinClass itin, list<dag> pattern>
715 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
718 class XForm_25_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
719 string asmstr, InstrItinClass itin, list<dag> pattern>
720 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
723 // [PO RT /// RB XO RC]
724 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
725 InstrItinClass itin, list<dag> pattern>
726 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
730 class XForm_28_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
731 string asmstr, InstrItinClass itin, list<dag> pattern>
732 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
735 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
736 InstrItinClass itin, list<dag> pattern>
737 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
740 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
741 // numbers presumably relates to some document, but I haven't found it.
742 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
743 InstrItinClass itin, list<dag> pattern>
744 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
745 let Pattern = pattern;
747 bit RC = 0; // set by isRecordForm
749 let Inst{6-10} = RST;
751 let Inst{21-30} = xo;
754 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
755 InstrItinClass itin, list<dag> pattern>
756 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
757 let Pattern = pattern;
760 bit RC = 0; // set by isRecordForm
764 let Inst{21-30} = xo;
768 class XForm_44<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
770 : I<opcode, OOL, IOL, asmstr, itin> {
775 let Inst{11-13} = BFA;
778 let Inst{21-30} = xo;
782 class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
784 : I<opcode, OOL, IOL, asmstr, itin> {
792 let Inst{21-30} = xo;
796 class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo,
797 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
799 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
800 let Pattern = pattern;
802 let Inst{6-10} = RST;
803 let Inst{11-12} = xo1;
804 let Inst{13-15} = xo2;
806 let Inst{21-30} = xo;
810 class X_FRT5_XO2_XO3_FRB5_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
811 bits<10> xo, dag OOL, dag IOL, string asmstr,
812 InstrItinClass itin, list<dag> pattern>
813 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
814 let Pattern = pattern;
817 let Inst{6-10} = RST;
818 let Inst{11-12} = xo1;
819 let Inst{13-15} = xo2;
820 let Inst{16-20} = FRB;
821 let Inst{21-30} = xo;
825 class X_FRT5_XO2_XO3_DRM3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
826 bits<10> xo, dag OOL, dag IOL, string asmstr,
827 InstrItinClass itin, list<dag> pattern>
828 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
829 let Pattern = pattern;
832 let Inst{6-10} = RST;
833 let Inst{11-12} = xo1;
834 let Inst{13-15} = xo2;
836 let Inst{18-20} = DRM;
837 let Inst{21-30} = xo;
841 class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
842 bits<10> xo, dag OOL, dag IOL, string asmstr,
843 InstrItinClass itin, list<dag> pattern>
844 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
845 let Pattern = pattern;
848 let Inst{6-10} = RST;
849 let Inst{11-12} = xo1;
850 let Inst{13-15} = xo2;
852 let Inst{19-20} = RM;
853 let Inst{21-30} = xo;
858 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
859 InstrItinClass itin, list<dag> pattern>
860 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
866 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
867 InstrItinClass itin, list<dag> pattern>
868 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
873 class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
874 string asmstr, InstrItinClass itin, list<dag> pattern>
875 : I<opcode, OOL, IOL, asmstr, itin> {
883 let Inst{21-30} = xo;
887 class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
888 string asmstr, InstrItinClass itin, list<dag> pattern>
889 : I<opcode, OOL, IOL, asmstr, itin> {
896 let Inst{21-30} = xo;
900 class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
901 InstrItinClass itin, list<dag> pattern>
902 : I<opcode, OOL, IOL, asmstr, itin> {
905 bit RC = 0; // set by isRecordForm
910 let Inst{21-30} = xo;
914 class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
915 InstrItinClass itin, list<dag> pattern>
916 : I<opcode, OOL, IOL, asmstr, itin> {
923 let Inst{21-30} = xo;
927 // [PO RT RA RB XO /]
928 class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
929 string asmstr, InstrItinClass itin, list<dag> pattern>
930 : I<opcode, OOL, IOL, asmstr, itin> {
936 let Pattern = pattern;
941 let Inst{11-15} = RA;
942 let Inst{16-20} = RB;
943 let Inst{21-30} = xo;
947 // Same as XForm_17 but with GPR's and new naming convention
948 class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
949 string asmstr, InstrItinClass itin, list<dag> pattern>
950 : I<opcode, OOL, IOL, asmstr, itin> {
955 let Pattern = pattern;
959 let Inst{11-15} = RA;
960 let Inst{16-20} = RB;
961 let Inst{21-30} = xo;
965 // e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO]
966 class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
967 string asmstr, InstrItinClass itin, list<dag> pattern>
968 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
972 class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
973 string asmstr, InstrItinClass itin, list<dag> pattern>
974 : I<opcode, OOL, IOL, asmstr, itin> {
979 let Pattern = pattern;
982 let Inst{9-15} = DCMX;
983 let Inst{16-20} = VB;
984 let Inst{21-30} = xo;
988 class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
989 string asmstr, InstrItinClass itin, list<dag> pattern>
990 : I<opcode, OOL, IOL, asmstr, itin> {
994 let Pattern = pattern;
996 let Inst{6-10} = XT{4-0};
998 let Inst{13-20} = IMM8;
999 let Inst{21-30} = xo;
1000 let Inst{31} = XT{5};
1003 // XForm_base_r3xo for instructions such as P9 atomics where we don't want
1004 // to specify an SDAG pattern for matching.
1005 class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1006 string asmstr, InstrItinClass itin>
1007 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, []> {
1010 class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1011 InstrItinClass itin>
1012 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> {
1017 // [PO /// L RA RB XO /]
1018 class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1019 string asmstr, InstrItinClass itin, list<dag> pattern>
1020 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
1022 let Pattern = pattern;
1029 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1030 InstrItinClass itin, list<dag> pattern>
1031 : I<opcode, OOL, IOL, asmstr, itin> {
1036 let Pattern = pattern;
1038 let Inst{6-10} = XT{4-0};
1039 let Inst{11-15} = A;
1040 let Inst{16-20} = B;
1041 let Inst{21-30} = xo;
1042 let Inst{31} = XT{5};
1045 class XX1Form_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1046 string asmstr, InstrItinClass itin, list<dag> pattern>
1047 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp;
1049 class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1050 string asmstr, InstrItinClass itin, list<dag> pattern>
1051 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1055 class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1056 InstrItinClass itin, list<dag> pattern>
1057 : I<opcode, OOL, IOL, asmstr, itin> {
1061 let Pattern = pattern;
1063 let Inst{6-10} = XT{4-0};
1064 let Inst{11-15} = 0;
1065 let Inst{16-20} = XB{4-0};
1066 let Inst{21-29} = xo;
1067 let Inst{30} = XB{5};
1068 let Inst{31} = XT{5};
1071 class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1072 InstrItinClass itin, list<dag> pattern>
1073 : I<opcode, OOL, IOL, asmstr, itin> {
1077 let Pattern = pattern;
1081 let Inst{16-20} = XB{4-0};
1082 let Inst{21-29} = xo;
1083 let Inst{30} = XB{5};
1087 class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1088 InstrItinClass itin, list<dag> pattern>
1089 : I<opcode, OOL, IOL, asmstr, itin> {
1094 let Pattern = pattern;
1096 let Inst{6-10} = XT{4-0};
1097 let Inst{11-13} = 0;
1098 let Inst{14-15} = D;
1099 let Inst{16-20} = XB{4-0};
1100 let Inst{21-29} = xo;
1101 let Inst{30} = XB{5};
1102 let Inst{31} = XT{5};
1105 class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
1106 string asmstr, InstrItinClass itin, list<dag> pattern>
1107 : I<opcode, OOL, IOL, asmstr, itin> {
1112 let Pattern = pattern;
1114 let Inst{6-10} = XT{4-0};
1115 let Inst{11-15} = UIM5;
1116 let Inst{16-20} = XB{4-0};
1117 let Inst{21-29} = xo;
1118 let Inst{30} = XB{5};
1119 let Inst{31} = XT{5};
1122 // [PO T XO B XO BX /]
1123 class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
1124 string asmstr, InstrItinClass itin, list<dag> pattern>
1125 : I<opcode, OOL, IOL, asmstr, itin> {
1129 let Pattern = pattern;
1131 let Inst{6-10} = RT;
1132 let Inst{11-15} = xo2;
1133 let Inst{16-20} = XB{4-0};
1134 let Inst{21-29} = xo;
1135 let Inst{30} = XB{5};
1139 // [PO T XO B XO BX TX]
1140 class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
1141 string asmstr, InstrItinClass itin, list<dag> pattern>
1142 : I<opcode, OOL, IOL, asmstr, itin> {
1146 let Pattern = pattern;
1148 let Inst{6-10} = XT{4-0};
1149 let Inst{11-15} = xo2;
1150 let Inst{16-20} = XB{4-0};
1151 let Inst{21-29} = xo;
1152 let Inst{30} = XB{5};
1153 let Inst{31} = XT{5};
1156 class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
1157 string asmstr, InstrItinClass itin, list<dag> pattern>
1158 : I<opcode, OOL, IOL, asmstr, itin> {
1163 let Pattern = pattern;
1166 let Inst{9-15} = DCMX;
1167 let Inst{16-20} = XB{4-0};
1168 let Inst{21-29} = xo;
1169 let Inst{30} = XB{5};
1173 class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2,
1174 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
1176 : I<opcode, OOL, IOL, asmstr, itin> {
1181 let Pattern = pattern;
1183 let Inst{6-10} = XT{4-0};
1184 let Inst{11-15} = DCMX{4-0};
1185 let Inst{16-20} = XB{4-0};
1186 let Inst{21-24} = xo1;
1187 let Inst{25} = DCMX{6};
1188 let Inst{26-28} = xo2;
1189 let Inst{29} = DCMX{5};
1190 let Inst{30} = XB{5};
1191 let Inst{31} = XT{5};
1194 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1195 InstrItinClass itin, list<dag> pattern>
1196 : I<opcode, OOL, IOL, asmstr, itin> {
1201 let Pattern = pattern;
1203 let Inst{6-10} = XT{4-0};
1204 let Inst{11-15} = XA{4-0};
1205 let Inst{16-20} = XB{4-0};
1206 let Inst{21-28} = xo;
1207 let Inst{29} = XA{5};
1208 let Inst{30} = XB{5};
1209 let Inst{31} = XT{5};
1212 class XX3Form_SameOp<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1213 InstrItinClass itin, list<dag> pattern>
1214 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1219 class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1220 InstrItinClass itin, list<dag> pattern>
1221 : I<opcode, OOL, IOL, asmstr, itin> {
1226 let Pattern = pattern;
1230 let Inst{11-15} = XA{4-0};
1231 let Inst{16-20} = XB{4-0};
1232 let Inst{21-28} = xo;
1233 let Inst{29} = XA{5};
1234 let Inst{30} = XB{5};
1238 class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1239 InstrItinClass itin, list<dag> pattern>
1240 : I<opcode, OOL, IOL, asmstr, itin> {
1246 let Pattern = pattern;
1248 let Inst{6-10} = XT{4-0};
1249 let Inst{11-15} = XA{4-0};
1250 let Inst{16-20} = XB{4-0};
1252 let Inst{22-23} = D;
1253 let Inst{24-28} = xo;
1254 let Inst{29} = XA{5};
1255 let Inst{30} = XB{5};
1256 let Inst{31} = XT{5};
1259 class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr,
1260 InstrItinClass itin, list<dag> pattern>
1261 : I<opcode, OOL, IOL, asmstr, itin> {
1266 let Pattern = pattern;
1268 bit RC = 0; // set by isRecordForm
1270 let Inst{6-10} = XT{4-0};
1271 let Inst{11-15} = XA{4-0};
1272 let Inst{16-20} = XB{4-0};
1274 let Inst{22-28} = xo;
1275 let Inst{29} = XA{5};
1276 let Inst{30} = XB{5};
1277 let Inst{31} = XT{5};
1280 class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
1281 InstrItinClass itin, list<dag> pattern>
1282 : I<opcode, OOL, IOL, asmstr, itin> {
1288 let Pattern = pattern;
1290 let Inst{6-10} = XT{4-0};
1291 let Inst{11-15} = XA{4-0};
1292 let Inst{16-20} = XB{4-0};
1293 let Inst{21-25} = XC{4-0};
1294 let Inst{26-27} = xo;
1295 let Inst{28} = XC{5};
1296 let Inst{29} = XA{5};
1297 let Inst{30} = XB{5};
1298 let Inst{31} = XT{5};
1301 // DCB_Form - Form X instruction, used for dcb* instructions.
1302 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
1303 InstrItinClass itin, list<dag> pattern>
1304 : I<31, OOL, IOL, asmstr, itin> {
1308 let Pattern = pattern;
1310 let Inst{6-10} = immfield;
1311 let Inst{11-15} = A;
1312 let Inst{16-20} = B;
1313 let Inst{21-30} = xo;
1317 class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr,
1318 InstrItinClass itin, list<dag> pattern>
1319 : I<31, OOL, IOL, asmstr, itin> {
1324 let Pattern = pattern;
1326 let Inst{6-10} = TH;
1327 let Inst{11-15} = A;
1328 let Inst{16-20} = B;
1329 let Inst{21-30} = xo;
1333 // DSS_Form - Form X instruction, used for altivec dss* instructions.
1334 class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr,
1335 InstrItinClass itin, list<dag> pattern>
1336 : I<31, OOL, IOL, asmstr, itin> {
1341 let Pattern = pattern;
1345 let Inst{9-10} = STRM;
1346 let Inst{11-15} = A;
1347 let Inst{16-20} = B;
1348 let Inst{21-30} = xo;
1353 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1354 InstrItinClass itin, list<dag> pattern>
1355 : I<opcode, OOL, IOL, asmstr, itin> {
1360 let Pattern = pattern;
1362 let Inst{6-10} = CRD;
1363 let Inst{11-15} = CRA;
1364 let Inst{16-20} = CRB;
1365 let Inst{21-30} = xo;
1369 class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1370 InstrItinClass itin, list<dag> pattern>
1371 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1377 class XLForm_1_gen<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1378 InstrItinClass itin, list<dag> pattern>
1379 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1388 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1389 InstrItinClass itin, list<dag> pattern>
1390 : I<opcode, OOL, IOL, asmstr, itin> {
1393 let Pattern = pattern;
1395 let Inst{6-10} = CRD;
1396 let Inst{11-15} = CRD;
1397 let Inst{16-20} = CRD;
1398 let Inst{21-30} = xo;
1402 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
1403 InstrItinClass itin, list<dag> pattern>
1404 : I<opcode, OOL, IOL, asmstr, itin> {
1409 let Pattern = pattern;
1411 let Inst{6-10} = BO;
1412 let Inst{11-15} = BI;
1413 let Inst{16-18} = 0;
1414 let Inst{19-20} = BH;
1415 let Inst{21-30} = xo;
1419 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
1420 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1421 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1422 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
1426 let BI{0-1} = BIBO{5-6};
1427 let BI{2-4} = CR{0-2};
1431 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
1432 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1433 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1438 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
1439 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1440 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1446 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1447 InstrItinClass itin>
1448 : I<opcode, OOL, IOL, asmstr, itin> {
1454 let Inst{11-13} = BFA;
1455 let Inst{14-15} = 0;
1456 let Inst{16-20} = 0;
1457 let Inst{21-30} = xo;
1461 class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1462 InstrItinClass itin>
1463 : I<opcode, OOL, IOL, asmstr, itin> {
1472 let Inst{11-14} = 0;
1474 let Inst{16-19} = U;
1476 let Inst{21-30} = xo;
1480 class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1481 InstrItinClass itin, list<dag> pattern>
1482 : I<opcode, OOL, IOL, asmstr, itin> {
1485 let Pattern = pattern;
1489 let Inst{21-30} = xo;
1493 class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
1494 bits<6> opcode2, bits<2> xo2,
1495 dag OOL, dag IOL, string asmstr,
1496 InstrItinClass itin, list<dag> pattern>
1497 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
1505 let Pattern = pattern;
1507 let Inst{6-10} = BO;
1508 let Inst{11-15} = BI;
1509 let Inst{16-18} = 0;
1510 let Inst{19-20} = BH;
1511 let Inst{21-30} = xo1;
1514 let Inst{38-42} = RST;
1515 let Inst{43-47} = DS_RA{18-14}; // Register #
1516 let Inst{48-61} = DS_RA{13-0}; // Displacement.
1517 let Inst{62-63} = xo2;
1520 class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
1521 bits<5> bo, bits<5> bi, bit lk,
1522 bits<6> opcode2, bits<2> xo2,
1523 dag OOL, dag IOL, string asmstr,
1524 InstrItinClass itin, list<dag> pattern>
1525 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2,
1526 OOL, IOL, asmstr, itin, pattern> {
1532 class XLForm_2_ext_and_DForm_1<bits<6> opcode1, bits<10> xo1, bits<5> bo,
1533 bits<5> bi, bit lk, bits<6> opcode2, dag OOL,
1534 dag IOL, string asmstr, InstrItinClass itin,
1536 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
1541 let Pattern = pattern;
1543 let Inst{6-10} = bo;
1544 let Inst{11-15} = bi;
1545 let Inst{16-18} = 0;
1546 let Inst{19-20} = 0; // Unused (BH)
1547 let Inst{21-30} = xo1;
1550 let Inst{38-42} = RST;
1551 let Inst{43-47} = D_RA{20-16}; // Base Register
1552 let Inst{48-63} = D_RA{15-0}; // Displacement
1556 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1557 InstrItinClass itin>
1558 : I<opcode, OOL, IOL, asmstr, itin> {
1562 let Inst{6-10} = RT;
1563 let Inst{11} = SPR{4};
1564 let Inst{12} = SPR{3};
1565 let Inst{13} = SPR{2};
1566 let Inst{14} = SPR{1};
1567 let Inst{15} = SPR{0};
1568 let Inst{16} = SPR{9};
1569 let Inst{17} = SPR{8};
1570 let Inst{18} = SPR{7};
1571 let Inst{19} = SPR{6};
1572 let Inst{20} = SPR{5};
1573 let Inst{21-30} = xo;
1577 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1578 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1579 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
1583 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1584 InstrItinClass itin>
1585 : I<opcode, OOL, IOL, asmstr, itin> {
1588 let Inst{6-10} = RT;
1589 let Inst{11-20} = 0;
1590 let Inst{21-30} = xo;
1594 class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1595 InstrItinClass itin, list<dag> pattern>
1596 : I<opcode, OOL, IOL, asmstr, itin> {
1599 let Pattern = pattern;
1601 let Inst{6-10} = RT;
1602 let Inst{11-20} = Entry;
1603 let Inst{21-30} = xo;
1607 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1608 InstrItinClass itin>
1609 : I<opcode, OOL, IOL, asmstr, itin> {
1613 let Inst{6-10} = rS;
1615 let Inst{12-19} = FXM;
1617 let Inst{21-30} = xo;
1621 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1622 InstrItinClass itin>
1623 : I<opcode, OOL, IOL, asmstr, itin> {
1627 let Inst{6-10} = ST;
1629 let Inst{12-19} = FXM;
1631 let Inst{21-30} = xo;
1635 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1636 InstrItinClass itin>
1637 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
1639 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1640 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1641 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
1646 // This is probably 1.7.9, but I don't have the reference that uses this
1647 // numbering scheme...
1648 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1649 InstrItinClass itin, list<dag>pattern>
1650 : I<opcode, OOL, IOL, asmstr, itin> {
1654 bit RC = 0; // set by isRecordForm
1655 let Pattern = pattern;
1658 let Inst{7-14} = FM;
1660 let Inst{16-20} = rT;
1661 let Inst{21-30} = xo;
1665 class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1666 InstrItinClass itin, list<dag>pattern>
1667 : I<opcode, OOL, IOL, asmstr, itin> {
1673 bit RC = 0; // set by isRecordForm
1674 let Pattern = pattern;
1677 let Inst{7-14} = FLM;
1679 let Inst{16-20} = FRB;
1680 let Inst{21-30} = xo;
1684 // 1.7.10 XS-Form - SRADI.
1685 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1686 InstrItinClass itin, list<dag> pattern>
1687 : I<opcode, OOL, IOL, asmstr, itin> {
1692 bit RC = 0; // set by isRecordForm
1693 let Pattern = pattern;
1695 let Inst{6-10} = RS;
1696 let Inst{11-15} = A;
1697 let Inst{16-20} = SH{4,3,2,1,0};
1698 let Inst{21-29} = xo;
1699 let Inst{30} = SH{5};
1704 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
1705 InstrItinClass itin, list<dag> pattern>
1706 : I<opcode, OOL, IOL, asmstr, itin> {
1711 let Pattern = pattern;
1713 bit RC = 0; // set by isRecordForm
1715 let Inst{6-10} = RT;
1716 let Inst{11-15} = RA;
1717 let Inst{16-20} = RB;
1719 let Inst{22-30} = xo;
1723 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
1724 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1725 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
1730 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1731 InstrItinClass itin, list<dag> pattern>
1732 : I<opcode, OOL, IOL, asmstr, itin> {
1738 let Pattern = pattern;
1740 bit RC = 0; // set by isRecordForm
1742 let Inst{6-10} = FRT;
1743 let Inst{11-15} = FRA;
1744 let Inst{16-20} = FRB;
1745 let Inst{21-25} = FRC;
1746 let Inst{26-30} = xo;
1750 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1751 InstrItinClass itin, list<dag> pattern>
1752 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1756 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1757 InstrItinClass itin, list<dag> pattern>
1758 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1762 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1763 InstrItinClass itin, list<dag> pattern>
1764 : I<opcode, OOL, IOL, asmstr, itin> {
1770 let Pattern = pattern;
1772 let Inst{6-10} = RT;
1773 let Inst{11-15} = RA;
1774 let Inst{16-20} = RB;
1775 let Inst{21-25} = COND;
1776 let Inst{26-30} = xo;
1781 class AForm_4a<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1782 InstrItinClass itin, list<dag> pattern>
1783 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1789 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1790 InstrItinClass itin, list<dag> pattern>
1791 : I<opcode, OOL, IOL, asmstr, itin> {
1798 let Pattern = pattern;
1800 bit RC = 0; // set by isRecordForm
1802 let Inst{6-10} = RS;
1803 let Inst{11-15} = RA;
1804 let Inst{16-20} = RB;
1805 let Inst{21-25} = MB;
1806 let Inst{26-30} = ME;
1810 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1811 InstrItinClass itin, list<dag> pattern>
1812 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
1816 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
1817 InstrItinClass itin, list<dag> pattern>
1818 : I<opcode, OOL, IOL, asmstr, itin> {
1824 let Pattern = pattern;
1826 bit RC = 0; // set by isRecordForm
1828 let Inst{6-10} = RS;
1829 let Inst{11-15} = RA;
1830 let Inst{16-20} = SH{4,3,2,1,0};
1831 let Inst{21-26} = MBE{4,3,2,1,0,5};
1832 let Inst{27-29} = xo;
1833 let Inst{30} = SH{5};
1837 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
1838 InstrItinClass itin, list<dag> pattern>
1839 : I<opcode, OOL, IOL, asmstr, itin> {
1845 let Pattern = pattern;
1847 bit RC = 0; // set by isRecordForm
1849 let Inst{6-10} = RS;
1850 let Inst{11-15} = RA;
1851 let Inst{16-20} = RB;
1852 let Inst{21-26} = MBE{4,3,2,1,0,5};
1853 let Inst{27-30} = xo;
1860 // VAForm_1 - DACB ordering.
1861 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
1862 InstrItinClass itin, list<dag> pattern>
1863 : I<4, OOL, IOL, asmstr, itin> {
1869 let Pattern = pattern;
1871 let Inst{6-10} = VD;
1872 let Inst{11-15} = VA;
1873 let Inst{16-20} = VB;
1874 let Inst{21-25} = VC;
1875 let Inst{26-31} = xo;
1878 // VAForm_1a - DABC ordering.
1879 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
1880 InstrItinClass itin, list<dag> pattern>
1881 : I<4, OOL, IOL, asmstr, itin> {
1887 let Pattern = pattern;
1889 let Inst{6-10} = VD;
1890 let Inst{11-15} = VA;
1891 let Inst{16-20} = VB;
1892 let Inst{21-25} = VC;
1893 let Inst{26-31} = xo;
1896 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1897 InstrItinClass itin, list<dag> pattern>
1898 : I<4, OOL, IOL, asmstr, itin> {
1904 let Pattern = pattern;
1906 let Inst{6-10} = VD;
1907 let Inst{11-15} = VA;
1908 let Inst{16-20} = VB;
1910 let Inst{22-25} = SH;
1911 let Inst{26-31} = xo;
1915 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1916 InstrItinClass itin, list<dag> pattern>
1917 : I<4, OOL, IOL, asmstr, itin> {
1922 let Pattern = pattern;
1924 let Inst{6-10} = VD;
1925 let Inst{11-15} = VA;
1926 let Inst{16-20} = VB;
1927 let Inst{21-31} = xo;
1930 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1931 InstrItinClass itin, list<dag> pattern>
1932 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1938 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1939 InstrItinClass itin, list<dag> pattern>
1940 : I<4, OOL, IOL, asmstr, itin> {
1944 let Pattern = pattern;
1946 let Inst{6-10} = VD;
1947 let Inst{11-15} = 0;
1948 let Inst{16-20} = VB;
1949 let Inst{21-31} = xo;
1952 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1953 InstrItinClass itin, list<dag> pattern>
1954 : I<4, OOL, IOL, asmstr, itin> {
1958 let Pattern = pattern;
1960 let Inst{6-10} = VD;
1961 let Inst{11-15} = IMM;
1962 let Inst{16-20} = 0;
1963 let Inst{21-31} = xo;
1966 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1967 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1968 InstrItinClass itin, list<dag> pattern>
1969 : I<4, OOL, IOL, asmstr, itin> {
1972 let Pattern = pattern;
1974 let Inst{6-10} = VD;
1975 let Inst{11-15} = 0;
1976 let Inst{16-20} = 0;
1977 let Inst{21-31} = xo;
1980 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1981 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1982 InstrItinClass itin, list<dag> pattern>
1983 : I<4, OOL, IOL, asmstr, itin> {
1986 let Pattern = pattern;
1989 let Inst{11-15} = 0;
1990 let Inst{16-20} = VB;
1991 let Inst{21-31} = xo;
1994 // e.g. [PO VRT EO VRB XO]
1995 class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL,
1996 string asmstr, InstrItinClass itin, list<dag> pattern>
1997 : I<4, OOL, IOL, asmstr, itin> {
2001 let Pattern = pattern;
2003 let Inst{6-10} = RD;
2004 let Inst{11-15} = eo;
2005 let Inst{16-20} = VB;
2006 let Inst{21-31} = xo;
2009 /// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX"
2010 class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr,
2011 InstrItinClass itin, list<dag> pattern>
2012 : I<4, OOL, IOL, asmstr, itin> {
2018 let Pattern = pattern;
2020 let Inst{6-10} = VD;
2021 let Inst{11-15} = VA;
2023 let Inst{17-20} = SIX;
2024 let Inst{21-31} = xo;
2027 /// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox"
2028 class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr,
2029 InstrItinClass itin, list<dag> pattern>
2030 : I<4, OOL, IOL, asmstr, itin> {
2034 let Pattern = pattern;
2036 let Inst{6-10} = VD;
2037 let Inst{11-15} = VA;
2038 let Inst{16-20} = 0;
2039 let Inst{21-31} = xo;
2043 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
2044 InstrItinClass itin, list<dag> pattern>
2045 : I<4, OOL, IOL, asmstr, itin> {
2051 let Pattern = pattern;
2053 let Inst{6-10} = VD;
2054 let Inst{11-15} = VA;
2055 let Inst{16-20} = VB;
2057 let Inst{22-31} = xo;
2060 // VX-Form: [PO VRT EO VRB 1 PS XO]
2061 class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo,
2062 dag OOL, dag IOL, string asmstr,
2063 InstrItinClass itin, list<dag> pattern>
2064 : I<4, OOL, IOL, asmstr, itin> {
2069 let Pattern = pattern;
2071 let Inst{6-10} = VD;
2072 let Inst{11-15} = eo;
2073 let Inst{16-20} = VB;
2076 let Inst{23-31} = xo;
2079 // VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO]
2080 class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr,
2081 InstrItinClass itin, list<dag> pattern>
2082 : I<4, OOL, IOL, asmstr, itin> {
2088 let Pattern = pattern;
2090 let Inst{6-10} = VD;
2091 let Inst{11-15} = VA;
2092 let Inst{16-20} = VB;
2095 let Inst{23-31} = xo;
2098 // Z23-Form (used by QPX)
2099 class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
2100 InstrItinClass itin, list<dag> pattern>
2101 : I<opcode, OOL, IOL, asmstr, itin> {
2107 let Pattern = pattern;
2109 bit RC = 0; // set by isRecordForm
2111 let Inst{6-10} = FRT;
2112 let Inst{11-15} = FRA;
2113 let Inst{16-20} = FRB;
2114 let Inst{21-22} = idx;
2115 let Inst{23-30} = xo;
2119 class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
2120 InstrItinClass itin, list<dag> pattern>
2121 : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
2125 class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
2126 InstrItinClass itin, list<dag> pattern>
2127 : I<opcode, OOL, IOL, asmstr, itin> {
2131 let Pattern = pattern;
2133 bit RC = 0; // set by isRecordForm
2135 let Inst{6-10} = FRT;
2136 let Inst{11-22} = idx;
2137 let Inst{23-30} = xo;
2141 class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
2142 InstrItinClass itin, list<dag> pattern>
2143 : I<opcode, OOL, IOL, asmstr, itin> {
2149 let Pattern = pattern;
2151 bit RC = 0; // set by isRecordForm
2153 let Inst{6-10} = VRT;
2154 let Inst{11-14} = 0;
2156 let Inst{16-20} = VRB;
2157 let Inst{21-22} = idx;
2158 let Inst{23-30} = xo;
2162 //===----------------------------------------------------------------------===//
2163 // EmitTimePseudo won't have encoding information for the [MC]CodeEmitter
2165 class PPCEmitTimePseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
2166 : I<0, OOL, IOL, asmstr, NoItinerary> {
2167 let isCodeGenOnly = 1;
2169 let Pattern = pattern;
2171 let hasNoSchedulingInfo = 1;
2174 // Instruction that require custom insertion support
2175 // a.k.a. ISelPseudos, however, these won't have isPseudo set
2176 class PPCCustomInserterPseudo<dag OOL, dag IOL, string asmstr,
2178 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> {
2179 let usesCustomInserter = 1;
2182 // PostRAPseudo will be expanded in expandPostRAPseudo, isPseudo flag in td
2183 // files is set only for PostRAPseudo
2184 class PPCPostRAExpPseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
2185 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> {
2189 class PseudoXFormMemOp<dag OOL, dag IOL, string asmstr, list<dag> pattern>
2190 : PPCPostRAExpPseudo<OOL, IOL, asmstr, pattern>, XFormMemOp;