1 //===- PPCInstrVSX.td - The PowerPC VSX Extension --*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the VSX extension to the PowerPC instruction set.
11 //===----------------------------------------------------------------------===//
13 // *********************************** NOTE ***********************************
14 // ** For POWER8 Little Endian, the VSX swap optimization relies on knowing **
15 // ** which VMX and VSX instructions are lane-sensitive and which are not. **
16 // ** A lane-sensitive instruction relies, implicitly or explicitly, on **
17 // ** whether lanes are numbered from left to right. An instruction like **
18 // ** VADDFP is not lane-sensitive, because each lane of the result vector **
19 // ** relies only on the corresponding lane of the source vectors. However, **
20 // ** an instruction like VMULESB is lane-sensitive, because "even" and **
21 // ** "odd" lanes are different for big-endian and little-endian numbering. **
23 // ** When adding new VMX and VSX instructions, please consider whether they **
24 // ** are lane-sensitive. If so, they must be added to a switch statement **
25 // ** in PPCVSXSwapRemoval::gatherVectorInstructions(). **
26 // ****************************************************************************
28 // *********************************** NOTE ***********************************
29 // ** When adding new anonymous patterns to this file, please add them to **
30 // ** the section titled Anonymous Patterns. Chances are that the existing **
31 // ** predicate blocks already contain a combination of features that you **
32 // ** are after. There is a list of blocks at the top of the section. If **
33 // ** you definitely need a new combination of predicates, please add that **
34 // ** combination to the list. **
35 // ** File Structure: **
36 // ** - Custom PPCISD node definitions **
37 // ** - Predicate definitions: predicates to specify the subtargets for **
38 // ** which an instruction or pattern can be emitted. **
39 // ** - Instruction formats: classes instantiated by the instructions. **
40 // ** These generally correspond to instruction formats in section 1.6 of **
41 // ** the ISA document. **
42 // ** - Instruction definitions: the actual definitions of the instructions **
43 // ** often including input patterns that they match. **
44 // ** - Helper DAG definitions: We define a number of dag objects to use as **
45 // ** input or output patterns for consciseness of the code. **
46 // ** - Anonymous patterns: input patterns that an instruction matches can **
47 // ** often not be specified as part of the instruction definition, so an **
48 // ** anonymous pattern must be specified mapping an input pattern to an **
49 // ** output pattern. These are generally guarded by subtarget predicates. **
50 // ** - Instruction aliases: used to define extended mnemonics for assembly **
51 // ** printing (for example: xxswapd for xxpermdi with 0x2 as the imm). **
52 // ****************************************************************************
54 def PPCRegVSRCAsmOperand : AsmOperandClass {
55 let Name = "RegVSRC"; let PredicateMethod = "isVSRegNumber";
57 def vsrc : RegisterOperand<VSRC> {
58 let ParserMatchClass = PPCRegVSRCAsmOperand;
61 def PPCRegVSFRCAsmOperand : AsmOperandClass {
62 let Name = "RegVSFRC"; let PredicateMethod = "isVSRegNumber";
64 def vsfrc : RegisterOperand<VSFRC> {
65 let ParserMatchClass = PPCRegVSFRCAsmOperand;
68 def PPCRegVSSRCAsmOperand : AsmOperandClass {
69 let Name = "RegVSSRC"; let PredicateMethod = "isVSRegNumber";
71 def vssrc : RegisterOperand<VSSRC> {
72 let ParserMatchClass = PPCRegVSSRCAsmOperand;
75 def PPCRegSPILLTOVSRRCAsmOperand : AsmOperandClass {
76 let Name = "RegSPILLTOVSRRC"; let PredicateMethod = "isVSRegNumber";
79 def spilltovsrrc : RegisterOperand<SPILLTOVSRRC> {
80 let ParserMatchClass = PPCRegSPILLTOVSRRCAsmOperand;
83 def SDT_PPCldvsxlh : SDTypeProfile<1, 1, [
84 SDTCisVT<0, v4f32>, SDTCisPtrTy<1>
87 def SDT_PPCfpexth : SDTypeProfile<1, 2, [
88 SDTCisVT<0, v2f64>, SDTCisVT<1, v4f32>, SDTCisPtrTy<2>
91 def SDT_PPCldsplat : SDTypeProfile<1, 1, [
92 SDTCisVec<0>, SDTCisPtrTy<1>
95 // Little-endian-specific nodes.
96 def SDT_PPClxvd2x : SDTypeProfile<1, 1, [
97 SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
99 def SDT_PPCstxvd2x : SDTypeProfile<0, 2, [
100 SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
102 def SDT_PPCxxswapd : SDTypeProfile<1, 1, [
105 def SDTVecConv : SDTypeProfile<1, 2, [
106 SDTCisVec<0>, SDTCisVec<1>, SDTCisPtrTy<2>
108 def SDTVabsd : SDTypeProfile<1, 3, [
109 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<3, i32>
111 def SDT_PPCld_vec_be : SDTypeProfile<1, 1, [
112 SDTCisVec<0>, SDTCisPtrTy<1>
114 def SDT_PPCst_vec_be : SDTypeProfile<0, 2, [
115 SDTCisVec<0>, SDTCisPtrTy<1>
118 //--------------------------- Custom PPC nodes -------------------------------//
119 def PPClxvd2x : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x,
120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
121 def PPCstxvd2x : SDNode<"PPCISD::STXVD2X", SDT_PPCstxvd2x,
122 [SDNPHasChain, SDNPMayStore]>;
123 def PPCld_vec_be : SDNode<"PPCISD::LOAD_VEC_BE", SDT_PPCld_vec_be,
124 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
125 def PPCst_vec_be : SDNode<"PPCISD::STORE_VEC_BE", SDT_PPCst_vec_be,
126 [SDNPHasChain, SDNPMayStore]>;
127 def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>;
128 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
129 def PPCmtvsra : SDNode<"PPCISD::MTVSRA", SDTUnaryOp, []>;
130 def PPCmtvsrz : SDNode<"PPCISD::MTVSRZ", SDTUnaryOp, []>;
131 def PPCsvec2fp : SDNode<"PPCISD::SINT_VEC_TO_FP", SDTVecConv, []>;
132 def PPCuvec2fp: SDNode<"PPCISD::UINT_VEC_TO_FP", SDTVecConv, []>;
133 def PPCswapNoChain : SDNode<"PPCISD::SWAP_NO_CHAIN", SDT_PPCxxswapd>;
134 def PPCvabsd : SDNode<"PPCISD::VABSD", SDTVabsd, []>;
136 def PPCfpexth : SDNode<"PPCISD::FP_EXTEND_HALF", SDT_PPCfpexth, []>;
137 def PPCldvsxlh : SDNode<"PPCISD::LD_VSX_LH", SDT_PPCldvsxlh,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def PPCldsplat : SDNode<"PPCISD::LD_SPLAT", SDT_PPCldsplat,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def PPCzextldsplat : SDNode<"PPCISD::ZEXT_LD_SPLAT", SDT_PPCldsplat,
142 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
143 def PPCsextldsplat : SDNode<"PPCISD::SEXT_LD_SPLAT", SDT_PPCldsplat,
144 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
145 def PPCSToV : SDNode<"PPCISD::SCALAR_TO_VECTOR_PERMUTED",
146 SDTypeProfile<1, 1, []>, []>;
148 //-------------------------- Predicate definitions ---------------------------//
149 def HasVSX : Predicate<"Subtarget->hasVSX()">;
150 def IsLittleEndian : Predicate<"Subtarget->isLittleEndian()">;
151 def IsBigEndian : Predicate<"!Subtarget->isLittleEndian()">;
152 def IsPPC64 : Predicate<"Subtarget->isPPC64()">;
153 def HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">;
154 def HasP8Vector : Predicate<"Subtarget->hasP8Vector()">;
155 def HasDirectMove : Predicate<"Subtarget->hasDirectMove()">;
156 def NoP9Vector : Predicate<"!Subtarget->hasP9Vector()">;
157 def HasP9Vector : Predicate<"Subtarget->hasP9Vector()">;
158 def NoP9Altivec : Predicate<"!Subtarget->hasP9Altivec()">;
159 def NoP10Vector: Predicate<"!Subtarget->hasP10Vector()">;
161 def PPCldsplatAlign16 : PatFrag<(ops node:$ptr), (PPCldsplat node:$ptr), [{
162 return cast<MemIntrinsicSDNode>(N)->getAlign() >= Align(16) &&
163 isOffsetMultipleOf(N, 16);
166 //--------------------- VSX-specific instruction formats ---------------------//
167 // By default, all VSX instructions are to be selected over their Altivec
168 // counter parts and they do not have unmodeled sideeffects.
169 let AddedComplexity = 400, hasSideEffects = 0 in {
170 multiclass XX3Form_Rcr<bits<6> opcode, bits<7> xo, string asmbase,
171 string asmstr, InstrItinClass itin, Intrinsic Int,
172 ValueType OutTy, ValueType InTy> {
173 let BaseName = asmbase in {
174 def NAME : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
175 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
176 [(set OutTy:$XT, (Int InTy:$XA, InTy:$XB))]>;
178 def _rec : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
179 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
181 (InTy (PPCvcmp_rec InTy:$XA, InTy:$XB, xo)))]>,
186 // Instruction form with a single input register for instructions such as
187 // XXPERMDI. The reason for defining this is that specifying multiple chained
188 // operands (such as loads) to an instruction will perform both chained
189 // operations rather than coalescing them into a single register - even though
190 // the source memory location is the same. This simply forces the instruction
191 // to use the same register for both inputs.
192 // For example, an output DAG such as this:
193 // (XXPERMDI (LXSIBZX xoaddr:$src), (LXSIBZX xoaddr:$src ), 0))
194 // would result in two load instructions emitted and used as separate inputs
195 // to the XXPERMDI instruction.
196 class XX3Form_2s<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
197 InstrItinClass itin, list<dag> pattern>
198 : XX3Form_2<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
202 let Predicates = [HasVSX, HasP9Vector] in {
203 class X_VT5_XO5_VB5<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
205 : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vrrc:$vB),
206 !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
208 // [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /]
209 class X_VT5_XO5_VB5_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
211 : X_VT5_XO5_VB5<opcode, xo2, xo, opc, pattern>, isRecordForm;
213 // [PO VRT XO VRB XO /], but the VRB is only used the left 64 bits (or less),
214 // So we use different operand class for VRB
215 class X_VT5_XO5_VB5_TyVB<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
216 RegisterOperand vbtype, list<dag> pattern>
217 : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vbtype:$vB),
218 !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
220 // [PO VRT XO VRB XO /]
221 class X_VT5_XO5_VB5_VSFR<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
223 : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vfrc:$vT), (ins vrrc:$vB),
224 !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
226 // [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /]
227 class X_VT5_XO5_VB5_VSFR_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
229 : X_VT5_XO5_VB5_VSFR<opcode, xo2, xo, opc, pattern>, isRecordForm;
231 // [PO T XO B XO BX /]
232 class XX2_RT5_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,
234 : XX2_RD5_XO5_RS6<opcode, xo2, xo, (outs g8rc:$rT), (ins vsfrc:$XB),
235 !strconcat(opc, " $rT, $XB"), IIC_VecFP, pattern>;
237 // [PO T XO B XO BX TX]
238 class XX2_XT6_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,
239 RegisterOperand vtype, list<dag> pattern>
240 : XX2_RD6_XO5_RS6<opcode, xo2, xo, (outs vtype:$XT), (ins vtype:$XB),
241 !strconcat(opc, " $XT, $XB"), IIC_VecFP, pattern>;
243 // [PO T A B XO AX BX TX], src and dest register use different operand class
244 class XX3_XT5_XA5_XB5<bits<6> opcode, bits<8> xo, string opc,
245 RegisterOperand xty, RegisterOperand aty, RegisterOperand bty,
246 InstrItinClass itin, list<dag> pattern>
247 : XX3Form<opcode, xo, (outs xty:$XT), (ins aty:$XA, bty:$XB),
248 !strconcat(opc, " $XT, $XA, $XB"), itin, pattern>;
250 // [PO VRT VRA VRB XO /]
251 class X_VT5_VA5_VB5<bits<6> opcode, bits<10> xo, string opc,
253 : XForm_1<opcode, xo, (outs vrrc:$vT), (ins vrrc:$vA, vrrc:$vB),
254 !strconcat(opc, " $vT, $vA, $vB"), IIC_VecFP, pattern>;
256 // [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /]
257 class X_VT5_VA5_VB5_Ro<bits<6> opcode, bits<10> xo, string opc,
259 : X_VT5_VA5_VB5<opcode, xo, opc, pattern>, isRecordForm;
261 // [PO VRT VRA VRB XO /]
262 class X_VT5_VA5_VB5_FMA<bits<6> opcode, bits<10> xo, string opc,
264 : XForm_1<opcode, xo, (outs vrrc:$vT), (ins vrrc:$vTi, vrrc:$vA, vrrc:$vB),
265 !strconcat(opc, " $vT, $vA, $vB"), IIC_VecFP, pattern>,
266 RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">;
268 // [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /]
269 class X_VT5_VA5_VB5_FMA_Ro<bits<6> opcode, bits<10> xo, string opc,
271 : X_VT5_VA5_VB5_FMA<opcode, xo, opc, pattern>, isRecordForm;
273 class Z23_VT5_R1_VB5_RMC2_EX1<bits<6> opcode, bits<8> xo, bit ex, string opc,
275 : Z23Form_8<opcode, xo,
276 (outs vrrc:$vT), (ins u1imm:$r, vrrc:$vB, u2imm:$rmc),
277 !strconcat(opc, " $r, $vT, $vB, $rmc"), IIC_VecFP, pattern> {
281 // [PO BF // VRA VRB XO /]
282 class X_BF3_VA5_VB5<bits<6> opcode, bits<10> xo, string opc,
284 : XForm_17<opcode, xo, (outs crrc:$crD), (ins vrrc:$VA, vrrc:$VB),
285 !strconcat(opc, " $crD, $VA, $VB"), IIC_FPCompare> {
286 let Pattern = pattern;
289 // [PO T RA RB XO TX] almost equal to [PO S RA RB XO SX], but has different
290 // "out" and "in" dag
291 class X_XT6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc,
292 RegisterOperand vtype, list<dag> pattern>
293 : XX1Form_memOp<opcode, xo, (outs vtype:$XT), (ins memrr:$src),
294 !strconcat(opc, " $XT, $src"), IIC_LdStLFD, pattern>;
296 // [PO S RA RB XO SX]
297 class X_XS6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc,
298 RegisterOperand vtype, list<dag> pattern>
299 : XX1Form_memOp<opcode, xo, (outs), (ins vtype:$XT, memrr:$dst),
300 !strconcat(opc, " $XT, $dst"), IIC_LdStSTFD, pattern>;
301 } // Predicates = HasP9Vector
302 } // AddedComplexity = 400, hasSideEffects = 0
304 multiclass ScalToVecWPermute<ValueType Ty, dag In, dag NonPermOut, dag PermOut> {
305 def : Pat<(Ty (scalar_to_vector In)), (Ty NonPermOut)>;
306 def : Pat<(Ty (PPCSToV In)), (Ty PermOut)>;
309 //-------------------------- Instruction definitions -------------------------//
310 // VSX instructions require the VSX feature, they are to be selected over
311 // equivalent Altivec patterns (as they address a larger register set) and
312 // they do not have unmodeled side effects.
313 let Predicates = [HasVSX], AddedComplexity = 400 in {
314 let hasSideEffects = 0 in {
316 // Load indexed instructions
317 let mayLoad = 1, mayStore = 0 in {
319 def LXSDX : XX1Form_memOp<31, 588,
320 (outs vsfrc:$XT), (ins memrr:$src),
321 "lxsdx $XT, $src", IIC_LdStLFD,
324 // Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later
326 def XFLOADf64 : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),
328 [(set f64:$XT, (load XForm:$src))]>;
330 let Predicates = [HasVSX, HasOnlySwappingMemOps] in
331 def LXVD2X : XX1Form_memOp<31, 844,
332 (outs vsrc:$XT), (ins memrr:$src),
333 "lxvd2x $XT, $src", IIC_LdStLFD,
336 def LXVDSX : XX1Form_memOp<31, 332,
337 (outs vsrc:$XT), (ins memrr:$src),
338 "lxvdsx $XT, $src", IIC_LdStLFD, []>;
340 let Predicates = [HasVSX, HasOnlySwappingMemOps] in
341 def LXVW4X : XX1Form_memOp<31, 780,
342 (outs vsrc:$XT), (ins memrr:$src),
343 "lxvw4x $XT, $src", IIC_LdStLFD,
347 // Store indexed instructions
348 let mayStore = 1, mayLoad = 0 in {
350 def STXSDX : XX1Form_memOp<31, 716,
351 (outs), (ins vsfrc:$XT, memrr:$dst),
352 "stxsdx $XT, $dst", IIC_LdStSTFD,
355 // Pseudo instruction XFSTOREf64 will be expanded to STXSDX or STFDX later
357 def XFSTOREf64 : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst),
359 [(store f64:$XT, XForm:$dst)]>;
361 let Predicates = [HasVSX, HasOnlySwappingMemOps] in {
362 // The behaviour of this instruction is endianness-specific so we provide no
363 // pattern to match it without considering endianness.
364 def STXVD2X : XX1Form_memOp<31, 972,
365 (outs), (ins vsrc:$XT, memrr:$dst),
366 "stxvd2x $XT, $dst", IIC_LdStSTFD,
369 def STXVW4X : XX1Form_memOp<31, 908,
370 (outs), (ins vsrc:$XT, memrr:$dst),
371 "stxvw4x $XT, $dst", IIC_LdStSTFD,
376 let mayRaiseFPException = 1 in {
378 // Add/Mul Instructions
379 let isCommutable = 1 in {
380 def XSADDDP : XX3Form<60, 32,
381 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
382 "xsadddp $XT, $XA, $XB", IIC_VecFP,
383 [(set f64:$XT, (any_fadd f64:$XA, f64:$XB))]>;
384 def XSMULDP : XX3Form<60, 48,
385 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
386 "xsmuldp $XT, $XA, $XB", IIC_VecFP,
387 [(set f64:$XT, (any_fmul f64:$XA, f64:$XB))]>;
389 def XVADDDP : XX3Form<60, 96,
390 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
391 "xvadddp $XT, $XA, $XB", IIC_VecFP,
392 [(set v2f64:$XT, (any_fadd v2f64:$XA, v2f64:$XB))]>;
394 def XVADDSP : XX3Form<60, 64,
395 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
396 "xvaddsp $XT, $XA, $XB", IIC_VecFP,
397 [(set v4f32:$XT, (any_fadd v4f32:$XA, v4f32:$XB))]>;
399 def XVMULDP : XX3Form<60, 112,
400 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
401 "xvmuldp $XT, $XA, $XB", IIC_VecFP,
402 [(set v2f64:$XT, (any_fmul v2f64:$XA, v2f64:$XB))]>;
404 def XVMULSP : XX3Form<60, 80,
405 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
406 "xvmulsp $XT, $XA, $XB", IIC_VecFP,
407 [(set v4f32:$XT, (any_fmul v4f32:$XA, v4f32:$XB))]>;
410 // Subtract Instructions
411 def XSSUBDP : XX3Form<60, 40,
412 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
413 "xssubdp $XT, $XA, $XB", IIC_VecFP,
414 [(set f64:$XT, (any_fsub f64:$XA, f64:$XB))]>;
416 def XVSUBDP : XX3Form<60, 104,
417 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
418 "xvsubdp $XT, $XA, $XB", IIC_VecFP,
419 [(set v2f64:$XT, (any_fsub v2f64:$XA, v2f64:$XB))]>;
420 def XVSUBSP : XX3Form<60, 72,
421 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
422 "xvsubsp $XT, $XA, $XB", IIC_VecFP,
423 [(set v4f32:$XT, (any_fsub v4f32:$XA, v4f32:$XB))]>;
426 let BaseName = "XSMADDADP" in {
427 let isCommutable = 1 in
428 def XSMADDADP : XX3Form<60, 33,
429 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
430 "xsmaddadp $XT, $XA, $XB", IIC_VecFP,
431 [(set f64:$XT, (any_fma f64:$XA, f64:$XB, f64:$XTi))]>,
432 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
434 let IsVSXFMAAlt = 1 in
435 def XSMADDMDP : XX3Form<60, 41,
436 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
437 "xsmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
438 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
442 let BaseName = "XSMSUBADP" in {
443 let isCommutable = 1 in
444 def XSMSUBADP : XX3Form<60, 49,
445 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
446 "xsmsubadp $XT, $XA, $XB", IIC_VecFP,
447 [(set f64:$XT, (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>,
448 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
450 let IsVSXFMAAlt = 1 in
451 def XSMSUBMDP : XX3Form<60, 57,
452 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
453 "xsmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
454 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
458 let BaseName = "XSNMADDADP" in {
459 let isCommutable = 1 in
460 def XSNMADDADP : XX3Form<60, 161,
461 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
462 "xsnmaddadp $XT, $XA, $XB", IIC_VecFP,
463 [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, f64:$XTi)))]>,
464 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
466 let IsVSXFMAAlt = 1 in
467 def XSNMADDMDP : XX3Form<60, 169,
468 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
469 "xsnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
470 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
474 let BaseName = "XSNMSUBADP" in {
475 let isCommutable = 1 in
476 def XSNMSUBADP : XX3Form<60, 177,
477 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
478 "xsnmsubadp $XT, $XA, $XB", IIC_VecFP,
479 [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>,
480 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
482 let IsVSXFMAAlt = 1 in
483 def XSNMSUBMDP : XX3Form<60, 185,
484 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
485 "xsnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
486 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
490 let BaseName = "XVMADDADP" in {
491 let isCommutable = 1 in
492 def XVMADDADP : XX3Form<60, 97,
493 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
494 "xvmaddadp $XT, $XA, $XB", IIC_VecFP,
495 [(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>,
496 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
498 let IsVSXFMAAlt = 1 in
499 def XVMADDMDP : XX3Form<60, 105,
500 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
501 "xvmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
502 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
506 let BaseName = "XVMADDASP" in {
507 let isCommutable = 1 in
508 def XVMADDASP : XX3Form<60, 65,
509 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
510 "xvmaddasp $XT, $XA, $XB", IIC_VecFP,
511 [(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>,
512 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
514 let IsVSXFMAAlt = 1 in
515 def XVMADDMSP : XX3Form<60, 73,
516 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
517 "xvmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
518 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
522 let BaseName = "XVMSUBADP" in {
523 let isCommutable = 1 in
524 def XVMSUBADP : XX3Form<60, 113,
525 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
526 "xvmsubadp $XT, $XA, $XB", IIC_VecFP,
527 [(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>,
528 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
530 let IsVSXFMAAlt = 1 in
531 def XVMSUBMDP : XX3Form<60, 121,
532 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
533 "xvmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
534 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
538 let BaseName = "XVMSUBASP" in {
539 let isCommutable = 1 in
540 def XVMSUBASP : XX3Form<60, 81,
541 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
542 "xvmsubasp $XT, $XA, $XB", IIC_VecFP,
543 [(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>,
544 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
546 let IsVSXFMAAlt = 1 in
547 def XVMSUBMSP : XX3Form<60, 89,
548 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
549 "xvmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
550 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
554 let BaseName = "XVNMADDADP" in {
555 let isCommutable = 1 in
556 def XVNMADDADP : XX3Form<60, 225,
557 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
558 "xvnmaddadp $XT, $XA, $XB", IIC_VecFP,
559 [(set v2f64:$XT, (fneg (any_fma v2f64:$XA, v2f64:$XB, v2f64:$XTi)))]>,
560 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
562 let IsVSXFMAAlt = 1 in
563 def XVNMADDMDP : XX3Form<60, 233,
564 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
565 "xvnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
566 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
570 let BaseName = "XVNMADDASP" in {
571 let isCommutable = 1 in
572 def XVNMADDASP : XX3Form<60, 193,
573 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
574 "xvnmaddasp $XT, $XA, $XB", IIC_VecFP,
575 [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>,
576 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
578 let IsVSXFMAAlt = 1 in
579 def XVNMADDMSP : XX3Form<60, 201,
580 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
581 "xvnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
582 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
586 let BaseName = "XVNMSUBADP" in {
587 let isCommutable = 1 in
588 def XVNMSUBADP : XX3Form<60, 241,
589 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
590 "xvnmsubadp $XT, $XA, $XB", IIC_VecFP,
591 [(set v2f64:$XT, (fneg (any_fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi))))]>,
592 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
594 let IsVSXFMAAlt = 1 in
595 def XVNMSUBMDP : XX3Form<60, 249,
596 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
597 "xvnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
598 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
602 let BaseName = "XVNMSUBASP" in {
603 let isCommutable = 1 in
604 def XVNMSUBASP : XX3Form<60, 209,
605 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
606 "xvnmsubasp $XT, $XA, $XB", IIC_VecFP,
607 [(set v4f32:$XT, (fneg (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>,
608 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
610 let IsVSXFMAAlt = 1 in
611 def XVNMSUBMSP : XX3Form<60, 217,
612 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
613 "xvnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
614 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
618 // Division Instructions
619 def XSDIVDP : XX3Form<60, 56,
620 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
621 "xsdivdp $XT, $XA, $XB", IIC_FPDivD,
622 [(set f64:$XT, (any_fdiv f64:$XA, f64:$XB))]>;
623 def XSSQRTDP : XX2Form<60, 75,
624 (outs vsfrc:$XT), (ins vsfrc:$XB),
625 "xssqrtdp $XT, $XB", IIC_FPSqrtD,
626 [(set f64:$XT, (any_fsqrt f64:$XB))]>;
628 def XSREDP : XX2Form<60, 90,
629 (outs vsfrc:$XT), (ins vsfrc:$XB),
630 "xsredp $XT, $XB", IIC_VecFP,
631 [(set f64:$XT, (PPCfre f64:$XB))]>;
632 def XSRSQRTEDP : XX2Form<60, 74,
633 (outs vsfrc:$XT), (ins vsfrc:$XB),
634 "xsrsqrtedp $XT, $XB", IIC_VecFP,
635 [(set f64:$XT, (PPCfrsqrte f64:$XB))]>;
637 let mayRaiseFPException = 0 in {
638 def XSTDIVDP : XX3Form_1<60, 61,
639 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
640 "xstdivdp $crD, $XA, $XB", IIC_FPCompare, []>;
641 def XSTSQRTDP : XX2Form_1<60, 106,
642 (outs crrc:$crD), (ins vsfrc:$XB),
643 "xstsqrtdp $crD, $XB", IIC_FPCompare,
644 [(set i32:$crD, (PPCftsqrt f64:$XB))]>;
645 def XVTDIVDP : XX3Form_1<60, 125,
646 (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
647 "xvtdivdp $crD, $XA, $XB", IIC_FPCompare, []>;
648 def XVTDIVSP : XX3Form_1<60, 93,
649 (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
650 "xvtdivsp $crD, $XA, $XB", IIC_FPCompare, []>;
652 def XVTSQRTDP : XX2Form_1<60, 234,
653 (outs crrc:$crD), (ins vsrc:$XB),
654 "xvtsqrtdp $crD, $XB", IIC_FPCompare,
655 [(set i32:$crD, (PPCftsqrt v2f64:$XB))]>;
656 def XVTSQRTSP : XX2Form_1<60, 170,
657 (outs crrc:$crD), (ins vsrc:$XB),
658 "xvtsqrtsp $crD, $XB", IIC_FPCompare,
659 [(set i32:$crD, (PPCftsqrt v4f32:$XB))]>;
662 def XVDIVDP : XX3Form<60, 120,
663 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
664 "xvdivdp $XT, $XA, $XB", IIC_FPDivD,
665 [(set v2f64:$XT, (any_fdiv v2f64:$XA, v2f64:$XB))]>;
666 def XVDIVSP : XX3Form<60, 88,
667 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
668 "xvdivsp $XT, $XA, $XB", IIC_FPDivS,
669 [(set v4f32:$XT, (any_fdiv v4f32:$XA, v4f32:$XB))]>;
671 def XVSQRTDP : XX2Form<60, 203,
672 (outs vsrc:$XT), (ins vsrc:$XB),
673 "xvsqrtdp $XT, $XB", IIC_FPSqrtD,
674 [(set v2f64:$XT, (any_fsqrt v2f64:$XB))]>;
675 def XVSQRTSP : XX2Form<60, 139,
676 (outs vsrc:$XT), (ins vsrc:$XB),
677 "xvsqrtsp $XT, $XB", IIC_FPSqrtS,
678 [(set v4f32:$XT, (any_fsqrt v4f32:$XB))]>;
680 def XVREDP : XX2Form<60, 218,
681 (outs vsrc:$XT), (ins vsrc:$XB),
682 "xvredp $XT, $XB", IIC_VecFP,
683 [(set v2f64:$XT, (PPCfre v2f64:$XB))]>;
684 def XVRESP : XX2Form<60, 154,
685 (outs vsrc:$XT), (ins vsrc:$XB),
686 "xvresp $XT, $XB", IIC_VecFP,
687 [(set v4f32:$XT, (PPCfre v4f32:$XB))]>;
689 def XVRSQRTEDP : XX2Form<60, 202,
690 (outs vsrc:$XT), (ins vsrc:$XB),
691 "xvrsqrtedp $XT, $XB", IIC_VecFP,
692 [(set v2f64:$XT, (PPCfrsqrte v2f64:$XB))]>;
693 def XVRSQRTESP : XX2Form<60, 138,
694 (outs vsrc:$XT), (ins vsrc:$XB),
695 "xvrsqrtesp $XT, $XB", IIC_VecFP,
696 [(set v4f32:$XT, (PPCfrsqrte v4f32:$XB))]>;
698 // Compare Instructions
699 def XSCMPODP : XX3Form_1<60, 43,
700 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
701 "xscmpodp $crD, $XA, $XB", IIC_FPCompare, []>;
702 def XSCMPUDP : XX3Form_1<60, 35,
703 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
704 "xscmpudp $crD, $XA, $XB", IIC_FPCompare, []>;
706 defm XVCMPEQDP : XX3Form_Rcr<60, 99,
707 "xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare,
708 int_ppc_vsx_xvcmpeqdp, v2i64, v2f64>;
709 defm XVCMPEQSP : XX3Form_Rcr<60, 67,
710 "xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare,
711 int_ppc_vsx_xvcmpeqsp, v4i32, v4f32>;
712 defm XVCMPGEDP : XX3Form_Rcr<60, 115,
713 "xvcmpgedp", "$XT, $XA, $XB", IIC_VecFPCompare,
714 int_ppc_vsx_xvcmpgedp, v2i64, v2f64>;
715 defm XVCMPGESP : XX3Form_Rcr<60, 83,
716 "xvcmpgesp", "$XT, $XA, $XB", IIC_VecFPCompare,
717 int_ppc_vsx_xvcmpgesp, v4i32, v4f32>;
718 defm XVCMPGTDP : XX3Form_Rcr<60, 107,
719 "xvcmpgtdp", "$XT, $XA, $XB", IIC_VecFPCompare,
720 int_ppc_vsx_xvcmpgtdp, v2i64, v2f64>;
721 defm XVCMPGTSP : XX3Form_Rcr<60, 75,
722 "xvcmpgtsp", "$XT, $XA, $XB", IIC_VecFPCompare,
723 int_ppc_vsx_xvcmpgtsp, v4i32, v4f32>;
726 let mayRaiseFPException = 0 in {
727 def XSABSDP : XX2Form<60, 345,
728 (outs vsfrc:$XT), (ins vsfrc:$XB),
729 "xsabsdp $XT, $XB", IIC_VecFP,
730 [(set f64:$XT, (fabs f64:$XB))]>;
731 def XSNABSDP : XX2Form<60, 361,
732 (outs vsfrc:$XT), (ins vsfrc:$XB),
733 "xsnabsdp $XT, $XB", IIC_VecFP,
734 [(set f64:$XT, (fneg (fabs f64:$XB)))]>;
735 def XSNEGDP : XX2Form<60, 377,
736 (outs vsfrc:$XT), (ins vsfrc:$XB),
737 "xsnegdp $XT, $XB", IIC_VecFP,
738 [(set f64:$XT, (fneg f64:$XB))]>;
739 def XSCPSGNDP : XX3Form<60, 176,
740 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
741 "xscpsgndp $XT, $XA, $XB", IIC_VecFP,
742 [(set f64:$XT, (fcopysign f64:$XB, f64:$XA))]>;
744 def XVABSDP : XX2Form<60, 473,
745 (outs vsrc:$XT), (ins vsrc:$XB),
746 "xvabsdp $XT, $XB", IIC_VecFP,
747 [(set v2f64:$XT, (fabs v2f64:$XB))]>;
749 def XVABSSP : XX2Form<60, 409,
750 (outs vsrc:$XT), (ins vsrc:$XB),
751 "xvabssp $XT, $XB", IIC_VecFP,
752 [(set v4f32:$XT, (fabs v4f32:$XB))]>;
754 def XVCPSGNDP : XX3Form<60, 240,
755 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
756 "xvcpsgndp $XT, $XA, $XB", IIC_VecFP,
757 [(set v2f64:$XT, (fcopysign v2f64:$XB, v2f64:$XA))]>;
758 def XVCPSGNSP : XX3Form<60, 208,
759 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
760 "xvcpsgnsp $XT, $XA, $XB", IIC_VecFP,
761 [(set v4f32:$XT, (fcopysign v4f32:$XB, v4f32:$XA))]>;
763 def XVNABSDP : XX2Form<60, 489,
764 (outs vsrc:$XT), (ins vsrc:$XB),
765 "xvnabsdp $XT, $XB", IIC_VecFP,
766 [(set v2f64:$XT, (fneg (fabs v2f64:$XB)))]>;
767 def XVNABSSP : XX2Form<60, 425,
768 (outs vsrc:$XT), (ins vsrc:$XB),
769 "xvnabssp $XT, $XB", IIC_VecFP,
770 [(set v4f32:$XT, (fneg (fabs v4f32:$XB)))]>;
772 def XVNEGDP : XX2Form<60, 505,
773 (outs vsrc:$XT), (ins vsrc:$XB),
774 "xvnegdp $XT, $XB", IIC_VecFP,
775 [(set v2f64:$XT, (fneg v2f64:$XB))]>;
776 def XVNEGSP : XX2Form<60, 441,
777 (outs vsrc:$XT), (ins vsrc:$XB),
778 "xvnegsp $XT, $XB", IIC_VecFP,
779 [(set v4f32:$XT, (fneg v4f32:$XB))]>;
782 // Conversion Instructions
783 def XSCVDPSP : XX2Form<60, 265,
784 (outs vsfrc:$XT), (ins vsfrc:$XB),
785 "xscvdpsp $XT, $XB", IIC_VecFP, []>;
786 def XSCVDPSXDS : XX2Form<60, 344,
787 (outs vsfrc:$XT), (ins vsfrc:$XB),
788 "xscvdpsxds $XT, $XB", IIC_VecFP,
789 [(set f64:$XT, (PPCany_fctidz f64:$XB))]>;
790 let isCodeGenOnly = 1 in
791 def XSCVDPSXDSs : XX2Form<60, 344,
792 (outs vssrc:$XT), (ins vssrc:$XB),
793 "xscvdpsxds $XT, $XB", IIC_VecFP,
794 [(set f32:$XT, (PPCany_fctidz f32:$XB))]>;
795 def XSCVDPSXWS : XX2Form<60, 88,
796 (outs vsfrc:$XT), (ins vsfrc:$XB),
797 "xscvdpsxws $XT, $XB", IIC_VecFP,
798 [(set f64:$XT, (PPCany_fctiwz f64:$XB))]>;
799 let isCodeGenOnly = 1 in
800 def XSCVDPSXWSs : XX2Form<60, 88,
801 (outs vssrc:$XT), (ins vssrc:$XB),
802 "xscvdpsxws $XT, $XB", IIC_VecFP,
803 [(set f32:$XT, (PPCany_fctiwz f32:$XB))]>;
804 def XSCVDPUXDS : XX2Form<60, 328,
805 (outs vsfrc:$XT), (ins vsfrc:$XB),
806 "xscvdpuxds $XT, $XB", IIC_VecFP,
807 [(set f64:$XT, (PPCany_fctiduz f64:$XB))]>;
808 let isCodeGenOnly = 1 in
809 def XSCVDPUXDSs : XX2Form<60, 328,
810 (outs vssrc:$XT), (ins vssrc:$XB),
811 "xscvdpuxds $XT, $XB", IIC_VecFP,
812 [(set f32:$XT, (PPCany_fctiduz f32:$XB))]>;
813 def XSCVDPUXWS : XX2Form<60, 72,
814 (outs vsfrc:$XT), (ins vsfrc:$XB),
815 "xscvdpuxws $XT, $XB", IIC_VecFP,
816 [(set f64:$XT, (PPCany_fctiwuz f64:$XB))]>;
817 let isCodeGenOnly = 1 in
818 def XSCVDPUXWSs : XX2Form<60, 72,
819 (outs vssrc:$XT), (ins vssrc:$XB),
820 "xscvdpuxws $XT, $XB", IIC_VecFP,
821 [(set f32:$XT, (PPCany_fctiwuz f32:$XB))]>;
822 def XSCVSPDP : XX2Form<60, 329,
823 (outs vsfrc:$XT), (ins vsfrc:$XB),
824 "xscvspdp $XT, $XB", IIC_VecFP, []>;
825 def XSCVSXDDP : XX2Form<60, 376,
826 (outs vsfrc:$XT), (ins vsfrc:$XB),
827 "xscvsxddp $XT, $XB", IIC_VecFP,
828 [(set f64:$XT, (PPCany_fcfid f64:$XB))]>;
829 def XSCVUXDDP : XX2Form<60, 360,
830 (outs vsfrc:$XT), (ins vsfrc:$XB),
831 "xscvuxddp $XT, $XB", IIC_VecFP,
832 [(set f64:$XT, (PPCany_fcfidu f64:$XB))]>;
834 def XVCVDPSP : XX2Form<60, 393,
835 (outs vsrc:$XT), (ins vsrc:$XB),
836 "xvcvdpsp $XT, $XB", IIC_VecFP,
837 [(set v4f32:$XT, (int_ppc_vsx_xvcvdpsp v2f64:$XB))]>;
838 def XVCVDPSXDS : XX2Form<60, 472,
839 (outs vsrc:$XT), (ins vsrc:$XB),
840 "xvcvdpsxds $XT, $XB", IIC_VecFP,
841 [(set v2i64:$XT, (any_fp_to_sint v2f64:$XB))]>;
842 def XVCVDPSXWS : XX2Form<60, 216,
843 (outs vsrc:$XT), (ins vsrc:$XB),
844 "xvcvdpsxws $XT, $XB", IIC_VecFP,
845 [(set v4i32:$XT, (int_ppc_vsx_xvcvdpsxws v2f64:$XB))]>;
846 def XVCVDPUXDS : XX2Form<60, 456,
847 (outs vsrc:$XT), (ins vsrc:$XB),
848 "xvcvdpuxds $XT, $XB", IIC_VecFP,
849 [(set v2i64:$XT, (any_fp_to_uint v2f64:$XB))]>;
850 def XVCVDPUXWS : XX2Form<60, 200,
851 (outs vsrc:$XT), (ins vsrc:$XB),
852 "xvcvdpuxws $XT, $XB", IIC_VecFP,
853 [(set v4i32:$XT, (int_ppc_vsx_xvcvdpuxws v2f64:$XB))]>;
855 def XVCVSPDP : XX2Form<60, 457,
856 (outs vsrc:$XT), (ins vsrc:$XB),
857 "xvcvspdp $XT, $XB", IIC_VecFP,
858 [(set v2f64:$XT, (int_ppc_vsx_xvcvspdp v4f32:$XB))]>;
859 def XVCVSPSXDS : XX2Form<60, 408,
860 (outs vsrc:$XT), (ins vsrc:$XB),
861 "xvcvspsxds $XT, $XB", IIC_VecFP,
862 [(set v2i64:$XT, (int_ppc_vsx_xvcvspsxds v4f32:$XB))]>;
863 def XVCVSPSXWS : XX2Form<60, 152,
864 (outs vsrc:$XT), (ins vsrc:$XB),
865 "xvcvspsxws $XT, $XB", IIC_VecFP,
866 [(set v4i32:$XT, (any_fp_to_sint v4f32:$XB))]>;
867 def XVCVSPUXDS : XX2Form<60, 392,
868 (outs vsrc:$XT), (ins vsrc:$XB),
869 "xvcvspuxds $XT, $XB", IIC_VecFP,
870 [(set v2i64:$XT, (int_ppc_vsx_xvcvspuxds v4f32:$XB))]>;
871 def XVCVSPUXWS : XX2Form<60, 136,
872 (outs vsrc:$XT), (ins vsrc:$XB),
873 "xvcvspuxws $XT, $XB", IIC_VecFP,
874 [(set v4i32:$XT, (any_fp_to_uint v4f32:$XB))]>;
875 def XVCVSXDDP : XX2Form<60, 504,
876 (outs vsrc:$XT), (ins vsrc:$XB),
877 "xvcvsxddp $XT, $XB", IIC_VecFP,
878 [(set v2f64:$XT, (any_sint_to_fp v2i64:$XB))]>;
879 def XVCVSXDSP : XX2Form<60, 440,
880 (outs vsrc:$XT), (ins vsrc:$XB),
881 "xvcvsxdsp $XT, $XB", IIC_VecFP,
882 [(set v4f32:$XT, (int_ppc_vsx_xvcvsxdsp v2i64:$XB))]>;
883 def XVCVSXWSP : XX2Form<60, 184,
884 (outs vsrc:$XT), (ins vsrc:$XB),
885 "xvcvsxwsp $XT, $XB", IIC_VecFP,
886 [(set v4f32:$XT, (any_sint_to_fp v4i32:$XB))]>;
887 def XVCVUXDDP : XX2Form<60, 488,
888 (outs vsrc:$XT), (ins vsrc:$XB),
889 "xvcvuxddp $XT, $XB", IIC_VecFP,
890 [(set v2f64:$XT, (any_uint_to_fp v2i64:$XB))]>;
891 def XVCVUXDSP : XX2Form<60, 424,
892 (outs vsrc:$XT), (ins vsrc:$XB),
893 "xvcvuxdsp $XT, $XB", IIC_VecFP,
894 [(set v4f32:$XT, (int_ppc_vsx_xvcvuxdsp v2i64:$XB))]>;
895 def XVCVUXWSP : XX2Form<60, 168,
896 (outs vsrc:$XT), (ins vsrc:$XB),
897 "xvcvuxwsp $XT, $XB", IIC_VecFP,
898 [(set v4f32:$XT, (any_uint_to_fp v4i32:$XB))]>;
900 let mayRaiseFPException = 0 in {
901 def XVCVSXWDP : XX2Form<60, 248,
902 (outs vsrc:$XT), (ins vsrc:$XB),
903 "xvcvsxwdp $XT, $XB", IIC_VecFP,
904 [(set v2f64:$XT, (int_ppc_vsx_xvcvsxwdp v4i32:$XB))]>;
905 def XVCVUXWDP : XX2Form<60, 232,
906 (outs vsrc:$XT), (ins vsrc:$XB),
907 "xvcvuxwdp $XT, $XB", IIC_VecFP,
908 [(set v2f64:$XT, (int_ppc_vsx_xvcvuxwdp v4i32:$XB))]>;
911 // Rounding Instructions respecting current rounding mode
912 def XSRDPIC : XX2Form<60, 107,
913 (outs vsfrc:$XT), (ins vsfrc:$XB),
914 "xsrdpic $XT, $XB", IIC_VecFP, []>;
915 def XVRDPIC : XX2Form<60, 235,
916 (outs vsrc:$XT), (ins vsrc:$XB),
917 "xvrdpic $XT, $XB", IIC_VecFP, []>;
918 def XVRSPIC : XX2Form<60, 171,
919 (outs vsrc:$XT), (ins vsrc:$XB),
920 "xvrspic $XT, $XB", IIC_VecFP, []>;
921 // Max/Min Instructions
922 let isCommutable = 1 in {
923 def XSMAXDP : XX3Form<60, 160,
924 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
925 "xsmaxdp $XT, $XA, $XB", IIC_VecFP,
927 (int_ppc_vsx_xsmaxdp vsfrc:$XA, vsfrc:$XB))]>;
928 def XSMINDP : XX3Form<60, 168,
929 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
930 "xsmindp $XT, $XA, $XB", IIC_VecFP,
932 (int_ppc_vsx_xsmindp vsfrc:$XA, vsfrc:$XB))]>;
934 def XVMAXDP : XX3Form<60, 224,
935 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
936 "xvmaxdp $XT, $XA, $XB", IIC_VecFP,
938 (int_ppc_vsx_xvmaxdp vsrc:$XA, vsrc:$XB))]>;
939 def XVMINDP : XX3Form<60, 232,
940 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
941 "xvmindp $XT, $XA, $XB", IIC_VecFP,
943 (int_ppc_vsx_xvmindp vsrc:$XA, vsrc:$XB))]>;
945 def XVMAXSP : XX3Form<60, 192,
946 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
947 "xvmaxsp $XT, $XA, $XB", IIC_VecFP,
949 (int_ppc_vsx_xvmaxsp vsrc:$XA, vsrc:$XB))]>;
950 def XVMINSP : XX3Form<60, 200,
951 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
952 "xvminsp $XT, $XA, $XB", IIC_VecFP,
954 (int_ppc_vsx_xvminsp vsrc:$XA, vsrc:$XB))]>;
958 // Rounding Instructions with static direction.
959 def XSRDPI : XX2Form<60, 73,
960 (outs vsfrc:$XT), (ins vsfrc:$XB),
961 "xsrdpi $XT, $XB", IIC_VecFP,
962 [(set f64:$XT, (any_fround f64:$XB))]>;
963 def XSRDPIM : XX2Form<60, 121,
964 (outs vsfrc:$XT), (ins vsfrc:$XB),
965 "xsrdpim $XT, $XB", IIC_VecFP,
966 [(set f64:$XT, (any_ffloor f64:$XB))]>;
967 def XSRDPIP : XX2Form<60, 105,
968 (outs vsfrc:$XT), (ins vsfrc:$XB),
969 "xsrdpip $XT, $XB", IIC_VecFP,
970 [(set f64:$XT, (any_fceil f64:$XB))]>;
971 def XSRDPIZ : XX2Form<60, 89,
972 (outs vsfrc:$XT), (ins vsfrc:$XB),
973 "xsrdpiz $XT, $XB", IIC_VecFP,
974 [(set f64:$XT, (any_ftrunc f64:$XB))]>;
976 def XVRDPI : XX2Form<60, 201,
977 (outs vsrc:$XT), (ins vsrc:$XB),
978 "xvrdpi $XT, $XB", IIC_VecFP,
979 [(set v2f64:$XT, (any_fround v2f64:$XB))]>;
980 def XVRDPIM : XX2Form<60, 249,
981 (outs vsrc:$XT), (ins vsrc:$XB),
982 "xvrdpim $XT, $XB", IIC_VecFP,
983 [(set v2f64:$XT, (any_ffloor v2f64:$XB))]>;
984 def XVRDPIP : XX2Form<60, 233,
985 (outs vsrc:$XT), (ins vsrc:$XB),
986 "xvrdpip $XT, $XB", IIC_VecFP,
987 [(set v2f64:$XT, (any_fceil v2f64:$XB))]>;
988 def XVRDPIZ : XX2Form<60, 217,
989 (outs vsrc:$XT), (ins vsrc:$XB),
990 "xvrdpiz $XT, $XB", IIC_VecFP,
991 [(set v2f64:$XT, (any_ftrunc v2f64:$XB))]>;
993 def XVRSPI : XX2Form<60, 137,
994 (outs vsrc:$XT), (ins vsrc:$XB),
995 "xvrspi $XT, $XB", IIC_VecFP,
996 [(set v4f32:$XT, (any_fround v4f32:$XB))]>;
997 def XVRSPIM : XX2Form<60, 185,
998 (outs vsrc:$XT), (ins vsrc:$XB),
999 "xvrspim $XT, $XB", IIC_VecFP,
1000 [(set v4f32:$XT, (any_ffloor v4f32:$XB))]>;
1001 def XVRSPIP : XX2Form<60, 169,
1002 (outs vsrc:$XT), (ins vsrc:$XB),
1003 "xvrspip $XT, $XB", IIC_VecFP,
1004 [(set v4f32:$XT, (any_fceil v4f32:$XB))]>;
1005 def XVRSPIZ : XX2Form<60, 153,
1006 (outs vsrc:$XT), (ins vsrc:$XB),
1007 "xvrspiz $XT, $XB", IIC_VecFP,
1008 [(set v4f32:$XT, (any_ftrunc v4f32:$XB))]>;
1009 } // mayRaiseFPException
1011 // Logical Instructions
1012 let isCommutable = 1 in
1013 def XXLAND : XX3Form<60, 130,
1014 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1015 "xxland $XT, $XA, $XB", IIC_VecGeneral,
1016 [(set v4i32:$XT, (and v4i32:$XA, v4i32:$XB))]>;
1017 def XXLANDC : XX3Form<60, 138,
1018 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1019 "xxlandc $XT, $XA, $XB", IIC_VecGeneral,
1020 [(set v4i32:$XT, (and v4i32:$XA,
1021 (vnot v4i32:$XB)))]>;
1022 let isCommutable = 1 in {
1023 def XXLNOR : XX3Form<60, 162,
1024 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1025 "xxlnor $XT, $XA, $XB", IIC_VecGeneral,
1026 [(set v4i32:$XT, (vnot (or v4i32:$XA,
1028 def XXLOR : XX3Form<60, 146,
1029 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1030 "xxlor $XT, $XA, $XB", IIC_VecGeneral,
1031 [(set v4i32:$XT, (or v4i32:$XA, v4i32:$XB))]>;
1032 let isCodeGenOnly = 1 in
1033 def XXLORf: XX3Form<60, 146,
1034 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
1035 "xxlor $XT, $XA, $XB", IIC_VecGeneral, []>;
1036 def XXLXOR : XX3Form<60, 154,
1037 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1038 "xxlxor $XT, $XA, $XB", IIC_VecGeneral,
1039 [(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>;
1042 let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
1043 isReMaterializable = 1 in {
1044 def XXLXORz : XX3Form_SameOp<60, 154, (outs vsrc:$XT), (ins),
1045 "xxlxor $XT, $XT, $XT", IIC_VecGeneral,
1046 [(set v4i32:$XT, (v4i32 immAllZerosV))]>;
1047 def XXLXORdpz : XX3Form_SameOp<60, 154,
1048 (outs vsfrc:$XT), (ins),
1049 "xxlxor $XT, $XT, $XT", IIC_VecGeneral,
1050 [(set f64:$XT, (fpimm0))]>;
1051 def XXLXORspz : XX3Form_SameOp<60, 154,
1052 (outs vssrc:$XT), (ins),
1053 "xxlxor $XT, $XT, $XT", IIC_VecGeneral,
1054 [(set f32:$XT, (fpimm0))]>;
1057 // Permutation Instructions
1058 def XXMRGHW : XX3Form<60, 18,
1059 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1060 "xxmrghw $XT, $XA, $XB", IIC_VecPerm, []>;
1061 def XXMRGLW : XX3Form<60, 50,
1062 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1063 "xxmrglw $XT, $XA, $XB", IIC_VecPerm, []>;
1065 def XXPERMDI : XX3Form_2<60, 10,
1066 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM),
1067 "xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm,
1068 [(set v2i64:$XT, (PPCxxpermdi v2i64:$XA, v2i64:$XB,
1069 imm32SExt16:$DM))]>;
1070 let isCodeGenOnly = 1 in
1071 // Note that the input register class for `$XA` of XXPERMDIs is `vsfrc` which
1072 // is not the same with the input register class(`vsrc`) of XXPERMDI instruction.
1073 // We did this on purpose because:
1074 // 1: The input is primarily for loads that load a partial vector(LFIWZX,
1075 // etc.), no need for SUBREG_TO_REG.
1076 // 2: With `vsfrc` register class, in the final assembly, float registers
1077 // like `f0` are used instead of vector scalar register like `vs0`. This
1078 // helps readability.
1079 def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$DM),
1080 "xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>;
1081 def XXSEL : XX4Form<60, 3,
1082 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC),
1083 "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>;
1085 def XXSLDWI : XX3Form_2<60, 2,
1086 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$SHW),
1087 "xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm,
1088 [(set v4i32:$XT, (PPCvecshl v4i32:$XA, v4i32:$XB,
1089 imm32SExt16:$SHW))]>;
1091 let isCodeGenOnly = 1 in
1092 def XXSLDWIs : XX3Form_2s<60, 2,
1093 (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$SHW),
1094 "xxsldwi $XT, $XA, $XA, $SHW", IIC_VecPerm, []>;
1096 def XXSPLTW : XX2Form_2<60, 164,
1097 (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM),
1098 "xxspltw $XT, $XB, $UIM", IIC_VecPerm,
1100 (PPCxxsplt v4i32:$XB, imm32SExt16:$UIM))]>;
1101 let isCodeGenOnly = 1 in
1102 def XXSPLTWs : XX2Form_2<60, 164,
1103 (outs vsrc:$XT), (ins vsfrc:$XB, u2imm:$UIM),
1104 "xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>;
1106 // The following VSX instructions were introduced in Power ISA 2.07
1107 let Predicates = [HasVSX, HasP8Vector] in {
1108 let isCommutable = 1 in {
1109 def XXLEQV : XX3Form<60, 186,
1110 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1111 "xxleqv $XT, $XA, $XB", IIC_VecGeneral,
1112 [(set v4i32:$XT, (vnot (xor v4i32:$XA, v4i32:$XB)))]>;
1113 def XXLNAND : XX3Form<60, 178,
1114 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1115 "xxlnand $XT, $XA, $XB", IIC_VecGeneral,
1116 [(set v4i32:$XT, (vnot (and v4i32:$XA, v4i32:$XB)))]>;
1119 let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
1120 isReMaterializable = 1 in {
1121 def XXLEQVOnes : XX3Form_SameOp<60, 186, (outs vsrc:$XT), (ins),
1122 "xxleqv $XT, $XT, $XT", IIC_VecGeneral,
1123 [(set v4i32:$XT, (bitconvert (v16i8 immAllOnesV)))]>;
1126 def XXLORC : XX3Form<60, 170,
1127 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1128 "xxlorc $XT, $XA, $XB", IIC_VecGeneral,
1129 [(set v4i32:$XT, (or v4i32:$XA, (vnot v4i32:$XB)))]>;
1131 // VSX scalar loads introduced in ISA 2.07
1132 let mayLoad = 1, mayStore = 0 in {
1134 def LXSSPX : XX1Form_memOp<31, 524, (outs vssrc:$XT), (ins memrr:$src),
1135 "lxsspx $XT, $src", IIC_LdStLFD, []>;
1136 def LXSIWAX : XX1Form_memOp<31, 76, (outs vsfrc:$XT), (ins memrr:$src),
1137 "lxsiwax $XT, $src", IIC_LdStLFD, []>;
1138 def LXSIWZX : XX1Form_memOp<31, 12, (outs vsfrc:$XT), (ins memrr:$src),
1139 "lxsiwzx $XT, $src", IIC_LdStLFD, []>;
1141 // Pseudo instruction XFLOADf32 will be expanded to LXSSPX or LFSX later
1143 def XFLOADf32 : PseudoXFormMemOp<(outs vssrc:$XT), (ins memrr:$src),
1145 [(set f32:$XT, (load XForm:$src))]>;
1146 // Pseudo instruction LIWAX will be expanded to LXSIWAX or LFIWAX later
1147 def LIWAX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),
1149 [(set f64:$XT, (PPClfiwax ForceXForm:$src))]>;
1150 // Pseudo instruction LIWZX will be expanded to LXSIWZX or LFIWZX later
1151 def LIWZX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),
1153 [(set f64:$XT, (PPClfiwzx ForceXForm:$src))]>;
1156 // VSX scalar stores introduced in ISA 2.07
1157 let mayStore = 1, mayLoad = 0 in {
1159 def STXSSPX : XX1Form_memOp<31, 652, (outs), (ins vssrc:$XT, memrr:$dst),
1160 "stxsspx $XT, $dst", IIC_LdStSTFD, []>;
1161 def STXSIWX : XX1Form_memOp<31, 140, (outs), (ins vsfrc:$XT, memrr:$dst),
1162 "stxsiwx $XT, $dst", IIC_LdStSTFD, []>;
1164 // Pseudo instruction XFSTOREf32 will be expanded to STXSSPX or STFSX later
1166 def XFSTOREf32 : PseudoXFormMemOp<(outs), (ins vssrc:$XT, memrr:$dst),
1168 [(store f32:$XT, XForm:$dst)]>;
1169 // Pseudo instruction STIWX will be expanded to STXSIWX or STFIWX later
1170 def STIWX : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst),
1172 [(PPCstfiwx f64:$XT, ForceXForm:$dst)]>;
1175 // VSX Elementary Scalar FP arithmetic (SP)
1176 let mayRaiseFPException = 1 in {
1177 let isCommutable = 1 in {
1178 def XSADDSP : XX3Form<60, 0,
1179 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
1180 "xsaddsp $XT, $XA, $XB", IIC_VecFP,
1181 [(set f32:$XT, (any_fadd f32:$XA, f32:$XB))]>;
1182 def XSMULSP : XX3Form<60, 16,
1183 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
1184 "xsmulsp $XT, $XA, $XB", IIC_VecFP,
1185 [(set f32:$XT, (any_fmul f32:$XA, f32:$XB))]>;
1188 def XSSUBSP : XX3Form<60, 8,
1189 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
1190 "xssubsp $XT, $XA, $XB", IIC_VecFP,
1191 [(set f32:$XT, (any_fsub f32:$XA, f32:$XB))]>;
1192 def XSDIVSP : XX3Form<60, 24,
1193 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
1194 "xsdivsp $XT, $XA, $XB", IIC_FPDivS,
1195 [(set f32:$XT, (any_fdiv f32:$XA, f32:$XB))]>;
1197 def XSRESP : XX2Form<60, 26,
1198 (outs vssrc:$XT), (ins vssrc:$XB),
1199 "xsresp $XT, $XB", IIC_VecFP,
1200 [(set f32:$XT, (PPCfre f32:$XB))]>;
1201 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1202 let hasSideEffects = 1 in
1203 def XSRSP : XX2Form<60, 281,
1204 (outs vssrc:$XT), (ins vsfrc:$XB),
1205 "xsrsp $XT, $XB", IIC_VecFP,
1206 [(set f32:$XT, (any_fpround f64:$XB))]>;
1207 def XSSQRTSP : XX2Form<60, 11,
1208 (outs vssrc:$XT), (ins vssrc:$XB),
1209 "xssqrtsp $XT, $XB", IIC_FPSqrtS,
1210 [(set f32:$XT, (any_fsqrt f32:$XB))]>;
1211 def XSRSQRTESP : XX2Form<60, 10,
1212 (outs vssrc:$XT), (ins vssrc:$XB),
1213 "xsrsqrtesp $XT, $XB", IIC_VecFP,
1214 [(set f32:$XT, (PPCfrsqrte f32:$XB))]>;
1217 let BaseName = "XSMADDASP" in {
1218 let isCommutable = 1 in
1219 def XSMADDASP : XX3Form<60, 1,
1221 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1222 "xsmaddasp $XT, $XA, $XB", IIC_VecFP,
1223 [(set f32:$XT, (any_fma f32:$XA, f32:$XB, f32:$XTi))]>,
1224 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1226 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1227 let IsVSXFMAAlt = 1, hasSideEffects = 1 in
1228 def XSMADDMSP : XX3Form<60, 9,
1230 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1231 "xsmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
1232 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1236 let BaseName = "XSMSUBASP" in {
1237 let isCommutable = 1 in
1238 def XSMSUBASP : XX3Form<60, 17,
1240 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1241 "xsmsubasp $XT, $XA, $XB", IIC_VecFP,
1242 [(set f32:$XT, (any_fma f32:$XA, f32:$XB,
1243 (fneg f32:$XTi)))]>,
1244 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1246 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1247 let IsVSXFMAAlt = 1, hasSideEffects = 1 in
1248 def XSMSUBMSP : XX3Form<60, 25,
1250 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1251 "xsmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
1252 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1256 let BaseName = "XSNMADDASP" in {
1257 let isCommutable = 1 in
1258 def XSNMADDASP : XX3Form<60, 129,
1260 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1261 "xsnmaddasp $XT, $XA, $XB", IIC_VecFP,
1262 [(set f32:$XT, (fneg (any_fma f32:$XA, f32:$XB,
1264 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1266 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1267 let IsVSXFMAAlt = 1, hasSideEffects = 1 in
1268 def XSNMADDMSP : XX3Form<60, 137,
1270 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1271 "xsnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
1272 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1276 let BaseName = "XSNMSUBASP" in {
1277 let isCommutable = 1 in
1278 def XSNMSUBASP : XX3Form<60, 145,
1280 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1281 "xsnmsubasp $XT, $XA, $XB", IIC_VecFP,
1282 [(set f32:$XT, (fneg (any_fma f32:$XA, f32:$XB,
1283 (fneg f32:$XTi))))]>,
1284 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1286 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1287 let IsVSXFMAAlt = 1, hasSideEffects = 1 in
1288 def XSNMSUBMSP : XX3Form<60, 153,
1290 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1291 "xsnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
1292 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1296 // Single Precision Conversions (FP <-> INT)
1297 def XSCVSXDSP : XX2Form<60, 312,
1298 (outs vssrc:$XT), (ins vsfrc:$XB),
1299 "xscvsxdsp $XT, $XB", IIC_VecFP,
1300 [(set f32:$XT, (PPCany_fcfids f64:$XB))]>;
1301 def XSCVUXDSP : XX2Form<60, 296,
1302 (outs vssrc:$XT), (ins vsfrc:$XB),
1303 "xscvuxdsp $XT, $XB", IIC_VecFP,
1304 [(set f32:$XT, (PPCany_fcfidus f64:$XB))]>;
1305 } // mayRaiseFPException
1307 // Conversions between vector and scalar single precision
1308 def XSCVDPSPN : XX2Form<60, 267, (outs vsrc:$XT), (ins vssrc:$XB),
1309 "xscvdpspn $XT, $XB", IIC_VecFP, []>;
1310 def XSCVSPDPN : XX2Form<60, 331, (outs vssrc:$XT), (ins vsrc:$XB),
1311 "xscvspdpn $XT, $XB", IIC_VecFP, []>;
1313 let Predicates = [HasVSX, HasDirectMove] in {
1314 // VSX direct move instructions
1315 def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
1316 "mfvsrd $rA, $XT", IIC_VecGeneral,
1317 [(set i64:$rA, (PPCmfvsr f64:$XT))]>,
1318 Requires<[In64BitMode]>;
1319 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1320 let isCodeGenOnly = 1, hasSideEffects = 1 in
1321 def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsrc:$XT),
1322 "mfvsrd $rA, $XT", IIC_VecGeneral,
1324 Requires<[In64BitMode]>;
1325 def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
1326 "mfvsrwz $rA, $XT", IIC_VecGeneral,
1327 [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
1328 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1329 let isCodeGenOnly = 1, hasSideEffects = 1 in
1330 def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsrc:$XT),
1331 "mfvsrwz $rA, $XT", IIC_VecGeneral,
1333 def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA),
1334 "mtvsrd $XT, $rA", IIC_VecGeneral,
1335 [(set f64:$XT, (PPCmtvsra i64:$rA))]>,
1336 Requires<[In64BitMode]>;
1337 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1338 let isCodeGenOnly = 1, hasSideEffects = 1 in
1339 def MTVRD : XX1_RS6_RD5_XO<31, 179, (outs vsrc:$XT), (ins g8rc:$rA),
1340 "mtvsrd $XT, $rA", IIC_VecGeneral,
1342 Requires<[In64BitMode]>;
1343 def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA),
1344 "mtvsrwa $XT, $rA", IIC_VecGeneral,
1345 [(set f64:$XT, (PPCmtvsra i32:$rA))]>;
1346 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1347 let isCodeGenOnly = 1, hasSideEffects = 1 in
1348 def MTVRWA : XX1_RS6_RD5_XO<31, 211, (outs vsrc:$XT), (ins gprc:$rA),
1349 "mtvsrwa $XT, $rA", IIC_VecGeneral,
1351 def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA),
1352 "mtvsrwz $XT, $rA", IIC_VecGeneral,
1353 [(set f64:$XT, (PPCmtvsrz i32:$rA))]>;
1354 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1355 let isCodeGenOnly = 1, hasSideEffects = 1 in
1356 def MTVRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsrc:$XT), (ins gprc:$rA),
1357 "mtvsrwz $XT, $rA", IIC_VecGeneral,
1361 } // HasVSX, HasP8Vector
1363 let Predicates = [HasVSX, IsISA3_0, HasDirectMove] in {
1364 def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$rA),
1365 "mtvsrws $XT, $rA", IIC_VecGeneral, []>;
1367 def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc_nox0:$rA, g8rc:$rB),
1368 "mtvsrdd $XT, $rA, $rB", IIC_VecGeneral,
1369 []>, Requires<[In64BitMode]>;
1371 def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$rA), (ins vsrc:$XT),
1372 "mfvsrld $rA, $XT", IIC_VecGeneral,
1373 []>, Requires<[In64BitMode]>;
1375 } // HasVSX, IsISA3_0, HasDirectMove
1377 let Predicates = [HasVSX, HasP9Vector] in {
1378 // Quad-Precision Scalar Move Instructions:
1380 def XSCPSGNQP : X_VT5_VA5_VB5<63, 100, "xscpsgnqp",
1382 (fcopysign f128:$vB, f128:$vA))]>;
1384 // Absolute/Negative-Absolute/Negate
1385 def XSABSQP : X_VT5_XO5_VB5<63, 0, 804, "xsabsqp",
1386 [(set f128:$vT, (fabs f128:$vB))]>;
1387 def XSNABSQP : X_VT5_XO5_VB5<63, 8, 804, "xsnabsqp",
1388 [(set f128:$vT, (fneg (fabs f128:$vB)))]>;
1389 def XSNEGQP : X_VT5_XO5_VB5<63, 16, 804, "xsnegqp",
1390 [(set f128:$vT, (fneg f128:$vB))]>;
1392 //===--------------------------------------------------------------------===//
1393 // Quad-Precision Scalar Floating-Point Arithmetic Instructions:
1395 // Add/Divide/Multiply/Subtract
1396 let mayRaiseFPException = 1 in {
1397 let isCommutable = 1 in {
1398 def XSADDQP : X_VT5_VA5_VB5 <63, 4, "xsaddqp",
1399 [(set f128:$vT, (any_fadd f128:$vA, f128:$vB))]>;
1400 def XSMULQP : X_VT5_VA5_VB5 <63, 36, "xsmulqp",
1401 [(set f128:$vT, (any_fmul f128:$vA, f128:$vB))]>;
1403 def XSSUBQP : X_VT5_VA5_VB5 <63, 516, "xssubqp" ,
1404 [(set f128:$vT, (any_fsub f128:$vA, f128:$vB))]>;
1405 def XSDIVQP : X_VT5_VA5_VB5 <63, 548, "xsdivqp",
1406 [(set f128:$vT, (any_fdiv f128:$vA, f128:$vB))]>;
1408 def XSSQRTQP : X_VT5_XO5_VB5 <63, 27, 804, "xssqrtqp",
1409 [(set f128:$vT, (any_fsqrt f128:$vB))]>;
1410 // (Negative) Multiply-{Add/Subtract}
1411 def XSMADDQP : X_VT5_VA5_VB5_FMA <63, 388, "xsmaddqp",
1413 (any_fma f128:$vA, f128:$vB, f128:$vTi))]>;
1414 def XSMSUBQP : X_VT5_VA5_VB5_FMA <63, 420, "xsmsubqp" ,
1416 (any_fma f128:$vA, f128:$vB,
1417 (fneg f128:$vTi)))]>;
1418 def XSNMADDQP : X_VT5_VA5_VB5_FMA <63, 452, "xsnmaddqp",
1420 (fneg (any_fma f128:$vA, f128:$vB,
1422 def XSNMSUBQP : X_VT5_VA5_VB5_FMA <63, 484, "xsnmsubqp",
1424 (fneg (any_fma f128:$vA, f128:$vB,
1425 (fneg f128:$vTi))))]>;
1427 let isCommutable = 1 in {
1428 def XSADDQPO : X_VT5_VA5_VB5_Ro<63, 4, "xsaddqpo",
1430 (int_ppc_addf128_round_to_odd
1431 f128:$vA, f128:$vB))]>;
1432 def XSMULQPO : X_VT5_VA5_VB5_Ro<63, 36, "xsmulqpo",
1434 (int_ppc_mulf128_round_to_odd
1435 f128:$vA, f128:$vB))]>;
1437 def XSSUBQPO : X_VT5_VA5_VB5_Ro<63, 516, "xssubqpo",
1439 (int_ppc_subf128_round_to_odd
1440 f128:$vA, f128:$vB))]>;
1441 def XSDIVQPO : X_VT5_VA5_VB5_Ro<63, 548, "xsdivqpo",
1443 (int_ppc_divf128_round_to_odd
1444 f128:$vA, f128:$vB))]>;
1445 def XSSQRTQPO : X_VT5_XO5_VB5_Ro<63, 27, 804, "xssqrtqpo",
1447 (int_ppc_sqrtf128_round_to_odd f128:$vB))]>;
1450 def XSMADDQPO : X_VT5_VA5_VB5_FMA_Ro<63, 388, "xsmaddqpo",
1452 (int_ppc_fmaf128_round_to_odd
1453 f128:$vA,f128:$vB,f128:$vTi))]>;
1455 def XSMSUBQPO : X_VT5_VA5_VB5_FMA_Ro<63, 420, "xsmsubqpo" ,
1457 (int_ppc_fmaf128_round_to_odd
1458 f128:$vA, f128:$vB, (fneg f128:$vTi)))]>;
1459 def XSNMADDQPO: X_VT5_VA5_VB5_FMA_Ro<63, 452, "xsnmaddqpo",
1461 (fneg (int_ppc_fmaf128_round_to_odd
1462 f128:$vA, f128:$vB, f128:$vTi)))]>;
1463 def XSNMSUBQPO: X_VT5_VA5_VB5_FMA_Ro<63, 484, "xsnmsubqpo",
1465 (fneg (int_ppc_fmaf128_round_to_odd
1466 f128:$vA, f128:$vB, (fneg f128:$vTi))))]>;
1467 } // mayRaiseFPException
1469 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1470 // QP Compare Ordered/Unordered
1471 let hasSideEffects = 1 in {
1472 // DP/QP Compare Exponents
1473 def XSCMPEXPDP : XX3Form_1<60, 59,
1474 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
1475 "xscmpexpdp $crD, $XA, $XB", IIC_FPCompare, []>;
1476 def XSCMPEXPQP : X_BF3_VA5_VB5<63, 164, "xscmpexpqp", []>;
1478 let mayRaiseFPException = 1 in {
1479 def XSCMPOQP : X_BF3_VA5_VB5<63, 132, "xscmpoqp", []>;
1480 def XSCMPUQP : X_BF3_VA5_VB5<63, 644, "xscmpuqp", []>;
1482 // DP Compare ==, >=, >, !=
1483 // Use vsrc for XT, because the entire register of XT is set.
1484 // XT.dword[1] = 0x0000_0000_0000_0000
1485 def XSCMPEQDP : XX3_XT5_XA5_XB5<60, 3, "xscmpeqdp", vsrc, vsfrc, vsfrc,
1487 def XSCMPGEDP : XX3_XT5_XA5_XB5<60, 19, "xscmpgedp", vsrc, vsfrc, vsfrc,
1489 def XSCMPGTDP : XX3_XT5_XA5_XB5<60, 11, "xscmpgtdp", vsrc, vsfrc, vsfrc,
1494 //===--------------------------------------------------------------------===//
1495 // Quad-Precision Floating-Point Conversion Instructions:
1497 let mayRaiseFPException = 1 in {
1499 def XSCVDPQP : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc,
1500 [(set f128:$vT, (any_fpextend f64:$vB))]>;
1502 // Round & Convert QP -> DP (dword[1] is set to zero)
1503 def XSCVQPDP : X_VT5_XO5_VB5_VSFR<63, 20, 836, "xscvqpdp" , []>;
1504 def XSCVQPDPO : X_VT5_XO5_VB5_VSFR_Ro<63, 20, 836, "xscvqpdpo",
1506 (int_ppc_truncf128_round_to_odd
1510 // Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero)
1511 let mayRaiseFPException = 1 in {
1512 def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>;
1513 def XSCVQPSWZ : X_VT5_XO5_VB5<63, 9, 836, "xscvqpswz", []>;
1514 def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", []>;
1515 def XSCVQPUWZ : X_VT5_XO5_VB5<63, 1, 836, "xscvqpuwz", []>;
1518 // Convert (Un)Signed DWord -> QP.
1519 def XSCVSDQP : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>;
1520 def XSCVUDQP : X_VT5_XO5_VB5_TyVB<63, 2, 836, "xscvudqp", vfrc, []>;
1522 // (Round &) Convert DP <-> HP
1523 // Note! xscvdphp's src and dest register both use the left 64 bits, so we use
1524 // vsfrc for src and dest register. xscvhpdp's src only use the left 16 bits,
1525 // but we still use vsfrc for it.
1526 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1527 let hasSideEffects = 1, mayRaiseFPException = 1 in {
1528 def XSCVDPHP : XX2_XT6_XO5_XB6<60, 17, 347, "xscvdphp", vsfrc, []>;
1529 def XSCVHPDP : XX2_XT6_XO5_XB6<60, 16, 347, "xscvhpdp", vsfrc, []>;
1532 let mayRaiseFPException = 1 in {
1534 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1535 let hasSideEffects = 1 in
1536 def XVCVHPSP : XX2_XT6_XO5_XB6<60, 24, 475, "xvcvhpsp", vsrc, []>;
1537 def XVCVSPHP : XX2_XT6_XO5_XB6<60, 25, 475, "xvcvsphp", vsrc,
1539 (int_ppc_vsx_xvcvsphp v4f32:$XB))]>;
1541 // Round to Quad-Precision Integer [with Inexact]
1542 def XSRQPI : Z23_VT5_R1_VB5_RMC2_EX1<63, 5, 0, "xsrqpi" , []>;
1543 def XSRQPIX : Z23_VT5_R1_VB5_RMC2_EX1<63, 5, 1, "xsrqpix", []>;
1545 // Round Quad-Precision to Double-Extended Precision (fp80)
1546 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1547 let hasSideEffects = 1 in
1548 def XSRQPXP : Z23_VT5_R1_VB5_RMC2_EX1<63, 37, 0, "xsrqpxp", []>;
1551 //===--------------------------------------------------------------------===//
1552 // Insert/Extract Instructions
1554 // Insert Exponent DP/QP
1555 // XT NOTE: XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU
1556 def XSIEXPDP : XX1Form <60, 918, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB),
1557 "xsiexpdp $XT, $rA, $rB", IIC_VecFP, []>;
1558 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1559 let hasSideEffects = 1 in {
1560 // vB NOTE: only vB.dword[0] is used, that's why we don't use
1561 // X_VT5_VA5_VB5 form
1562 def XSIEXPQP : XForm_18<63, 868, (outs vrrc:$vT), (ins vrrc:$vA, vsfrc:$vB),
1563 "xsiexpqp $vT, $vA, $vB", IIC_VecFP, []>;
1566 // Extract Exponent/Significand DP/QP
1567 def XSXEXPDP : XX2_RT5_XO5_XB6<60, 0, 347, "xsxexpdp", []>;
1568 def XSXSIGDP : XX2_RT5_XO5_XB6<60, 1, 347, "xsxsigdp", []>;
1570 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1571 let hasSideEffects = 1 in {
1572 def XSXEXPQP : X_VT5_XO5_VB5 <63, 2, 804, "xsxexpqp", []>;
1573 def XSXSIGQP : X_VT5_XO5_VB5 <63, 18, 804, "xsxsigqp", []>;
1576 // Vector Insert Word
1577 // XB NOTE: Only XB.dword[1] is used, but we use vsrc on XB.
1579 XX2_RD6_UIM5_RS6<60, 181, (outs vsrc:$XT),
1580 (ins vsrc:$XTi, vsrc:$XB, u4imm:$UIM),
1581 "xxinsertw $XT, $XB, $UIM", IIC_VecFP,
1582 [(set v4i32:$XT, (PPCvecinsert v4i32:$XTi, v4i32:$XB,
1583 imm32SExt16:$UIM))]>,
1584 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
1586 // Vector Extract Unsigned Word
1587 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1588 let hasSideEffects = 1 in
1589 def XXEXTRACTUW : XX2_RD6_UIM5_RS6<60, 165,
1590 (outs vsfrc:$XT), (ins vsrc:$XB, u4imm:$UIMM),
1591 "xxextractuw $XT, $XB, $UIMM", IIC_VecFP, []>;
1593 // Vector Insert Exponent DP/SP
1594 def XVIEXPDP : XX3_XT5_XA5_XB5<60, 248, "xviexpdp", vsrc, vsrc, vsrc,
1595 IIC_VecFP, [(set v2f64: $XT,(int_ppc_vsx_xviexpdp v2i64:$XA, v2i64:$XB))]>;
1596 def XVIEXPSP : XX3_XT5_XA5_XB5<60, 216, "xviexpsp", vsrc, vsrc, vsrc,
1597 IIC_VecFP, [(set v4f32: $XT,(int_ppc_vsx_xviexpsp v4i32:$XA, v4i32:$XB))]>;
1599 // Vector Extract Exponent/Significand DP/SP
1600 def XVXEXPDP : XX2_XT6_XO5_XB6<60, 0, 475, "xvxexpdp", vsrc,
1602 (int_ppc_vsx_xvxexpdp v2f64:$XB))]>;
1603 def XVXEXPSP : XX2_XT6_XO5_XB6<60, 8, 475, "xvxexpsp", vsrc,
1605 (int_ppc_vsx_xvxexpsp v4f32:$XB))]>;
1606 def XVXSIGDP : XX2_XT6_XO5_XB6<60, 1, 475, "xvxsigdp", vsrc,
1608 (int_ppc_vsx_xvxsigdp v2f64:$XB))]>;
1609 def XVXSIGSP : XX2_XT6_XO5_XB6<60, 9, 475, "xvxsigsp", vsrc,
1611 (int_ppc_vsx_xvxsigsp v4f32:$XB))]>;
1613 // Test Data Class SP/DP/QP
1614 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1615 let hasSideEffects = 1 in {
1616 def XSTSTDCSP : XX2_BF3_DCMX7_RS6<60, 298,
1617 (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),
1618 "xststdcsp $BF, $XB, $DCMX", IIC_VecFP, []>;
1619 def XSTSTDCDP : XX2_BF3_DCMX7_RS6<60, 362,
1620 (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),
1621 "xststdcdp $BF, $XB, $DCMX", IIC_VecFP, []>;
1622 def XSTSTDCQP : X_BF3_DCMX7_RS5 <63, 708,
1623 (outs crrc:$BF), (ins u7imm:$DCMX, vrrc:$vB),
1624 "xststdcqp $BF, $vB, $DCMX", IIC_VecFP, []>;
1627 // Vector Test Data Class SP/DP
1628 def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5,
1629 (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),
1630 "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP,
1632 (int_ppc_vsx_xvtstdcsp v4f32:$XB, timm:$DCMX))]>;
1633 def XVTSTDCDP : XX2_RD6_DCMX7_RS6<60, 15, 5,
1634 (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),
1635 "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP,
1637 (int_ppc_vsx_xvtstdcdp v2f64:$XB, timm:$DCMX))]>;
1639 // Maximum/Minimum Type-C/Type-J DP
1640 let mayRaiseFPException = 1 in {
1641 def XSMAXCDP : XX3_XT5_XA5_XB5<60, 128, "xsmaxcdp", vsfrc, vsfrc, vsfrc,
1643 [(set f64:$XT, (PPCxsmaxc f64:$XA, f64:$XB))]>;
1644 def XSMINCDP : XX3_XT5_XA5_XB5<60, 136, "xsmincdp", vsfrc, vsfrc, vsfrc,
1646 [(set f64:$XT, (PPCxsminc f64:$XA, f64:$XB))]>;
1648 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1649 let hasSideEffects = 1 in {
1650 def XSMAXJDP : XX3_XT5_XA5_XB5<60, 144, "xsmaxjdp", vsrc, vsfrc, vsfrc,
1652 def XSMINJDP : XX3_XT5_XA5_XB5<60, 152, "xsminjdp", vsrc, vsfrc, vsfrc,
1657 // Vector Byte-Reverse H/W/D/Q Word
1658 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1659 let hasSideEffects = 1 in
1660 def XXBRH : XX2_XT6_XO5_XB6<60, 7, 475, "xxbrh", vsrc, []>;
1661 def XXBRW : XX2_XT6_XO5_XB6<60, 15, 475, "xxbrw", vsrc,
1662 [(set v4i32:$XT, (bswap v4i32:$XB))]>;
1663 def XXBRD : XX2_XT6_XO5_XB6<60, 23, 475, "xxbrd", vsrc,
1664 [(set v2i64:$XT, (bswap v2i64:$XB))]>;
1665 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1666 let hasSideEffects = 1 in
1667 def XXBRQ : XX2_XT6_XO5_XB6<60, 31, 475, "xxbrq", vsrc, []>;
1670 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1671 let hasSideEffects = 1 in {
1672 def XXPERM : XX3_XT5_XA5_XB5<60, 26, "xxperm" , vsrc, vsrc, vsrc,
1674 def XXPERMR : XX3_XT5_XA5_XB5<60, 58, "xxpermr", vsrc, vsrc, vsrc,
1678 // Vector Splat Immediate Byte
1679 // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1680 let hasSideEffects = 1 in
1681 def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8),
1682 "xxspltib $XT, $IMM8", IIC_VecPerm, []>;
1684 // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in
1685 // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging.
1686 let mayLoad = 1, mayStore = 0 in {
1688 def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins memrix16:$src),
1689 "lxv $XT, $src", IIC_LdStLFD, []>;
1691 def LXSD : DSForm_1<57, 2, (outs vfrc:$vD), (ins memrix:$src),
1692 "lxsd $vD, $src", IIC_LdStLFD, []>;
1693 // Load SP from src, convert it to DP, and place in dword[0]
1694 def LXSSP : DSForm_1<57, 3, (outs vfrc:$vD), (ins memrix:$src),
1695 "lxssp $vD, $src", IIC_LdStLFD, []>;
1697 // Load as Integer Byte/Halfword & Zero Indexed
1698 def LXSIBZX : X_XT6_RA5_RB5<31, 781, "lxsibzx", vsfrc,
1699 [(set f64:$XT, (PPClxsizx ForceXForm:$src, 1))]>;
1700 def LXSIHZX : X_XT6_RA5_RB5<31, 813, "lxsihzx", vsfrc,
1701 [(set f64:$XT, (PPClxsizx ForceXForm:$src, 2))]>;
1703 // Load Vector Halfword*8/Byte*16 Indexed
1704 def LXVH8X : X_XT6_RA5_RB5<31, 812, "lxvh8x" , vsrc, []>;
1705 def LXVB16X : X_XT6_RA5_RB5<31, 876, "lxvb16x", vsrc, []>;
1707 // Load Vector Indexed
1708 def LXVX : X_XT6_RA5_RB5<31, 268, "lxvx" , vsrc,
1709 [(set v2f64:$XT, (load XForm:$src))]>;
1710 // Load Vector (Left-justified) with Length
1711 def LXVL : XX1Form_memOp<31, 269, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
1712 "lxvl $XT, $src, $rB", IIC_LdStLoad,
1713 [(set v4i32:$XT, (int_ppc_vsx_lxvl addr:$src, i64:$rB))]>;
1714 def LXVLL : XX1Form_memOp<31,301, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
1715 "lxvll $XT, $src, $rB", IIC_LdStLoad,
1716 [(set v4i32:$XT, (int_ppc_vsx_lxvll addr:$src, i64:$rB))]>;
1718 // Load Vector Word & Splat Indexed
1719 def LXVWSX : X_XT6_RA5_RB5<31, 364, "lxvwsx" , vsrc, []>;
1722 // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in
1723 // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging.
1724 let mayStore = 1, mayLoad = 0 in {
1726 def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, memrix16:$dst),
1727 "stxv $XT, $dst", IIC_LdStSTFD, []>;
1729 def STXSD : DSForm_1<61, 2, (outs), (ins vfrc:$vS, memrix:$dst),
1730 "stxsd $vS, $dst", IIC_LdStSTFD, []>;
1731 // Convert DP of dword[0] to SP, and Store to dst
1732 def STXSSP : DSForm_1<61, 3, (outs), (ins vfrc:$vS, memrix:$dst),
1733 "stxssp $vS, $dst", IIC_LdStSTFD, []>;
1735 // Store as Integer Byte/Halfword Indexed
1736 def STXSIBX : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsfrc,
1737 [(PPCstxsix f64:$XT, ForceXForm:$dst, 1)]>;
1738 def STXSIHX : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsfrc,
1739 [(PPCstxsix f64:$XT, ForceXForm:$dst, 2)]>;
1740 let isCodeGenOnly = 1 in {
1741 def STXSIBXv : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsrc, []>;
1742 def STXSIHXv : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsrc, []>;
1745 // Store Vector Halfword*8/Byte*16 Indexed
1746 def STXVH8X : X_XS6_RA5_RB5<31, 940, "stxvh8x" , vsrc, []>;
1747 def STXVB16X : X_XS6_RA5_RB5<31, 1004, "stxvb16x", vsrc, []>;
1749 // Store Vector Indexed
1750 def STXVX : X_XS6_RA5_RB5<31, 396, "stxvx" , vsrc,
1751 [(store v2f64:$XT, XForm:$dst)]>;
1753 // Store Vector (Left-justified) with Length
1754 def STXVL : XX1Form_memOp<31, 397, (outs),
1755 (ins vsrc:$XT, memr:$dst, g8rc:$rB),
1756 "stxvl $XT, $dst, $rB", IIC_LdStLoad,
1757 [(int_ppc_vsx_stxvl v4i32:$XT, addr:$dst,
1759 def STXVLL : XX1Form_memOp<31, 429, (outs),
1760 (ins vsrc:$XT, memr:$dst, g8rc:$rB),
1761 "stxvll $XT, $dst, $rB", IIC_LdStLoad,
1762 [(int_ppc_vsx_stxvll v4i32:$XT, addr:$dst,
1766 def DFLOADf32 : PPCPostRAExpPseudo<(outs vssrc:$XT), (ins memrix:$src),
1768 [(set f32:$XT, (load DSForm:$src))]>;
1769 def DFLOADf64 : PPCPostRAExpPseudo<(outs vsfrc:$XT), (ins memrix:$src),
1771 [(set f64:$XT, (load DSForm:$src))]>;
1772 def DFSTOREf32 : PPCPostRAExpPseudo<(outs), (ins vssrc:$XT, memrix:$dst),
1774 [(store f32:$XT, DSForm:$dst)]>;
1775 def DFSTOREf64 : PPCPostRAExpPseudo<(outs), (ins vsfrc:$XT, memrix:$dst),
1777 [(store f64:$XT, DSForm:$dst)]>;
1779 let mayStore = 1 in {
1780 def SPILLTOVSR_STX : PseudoXFormMemOp<(outs),
1781 (ins spilltovsrrc:$XT, memrr:$dst),
1782 "#SPILLTOVSR_STX", []>;
1783 def SPILLTOVSR_ST : PPCPostRAExpPseudo<(outs), (ins spilltovsrrc:$XT, memrix:$dst),
1784 "#SPILLTOVSR_ST", []>;
1786 let mayLoad = 1 in {
1787 def SPILLTOVSR_LDX : PseudoXFormMemOp<(outs spilltovsrrc:$XT),
1789 "#SPILLTOVSR_LDX", []>;
1790 def SPILLTOVSR_LD : PPCPostRAExpPseudo<(outs spilltovsrrc:$XT), (ins memrix:$src),
1791 "#SPILLTOVSR_LD", []>;
1795 } // hasSideEffects = 0
1797 let PPC970_Single = 1, AddedComplexity = 400 in {
1799 def SELECT_CC_VSRC: PPCCustomInserterPseudo<(outs vsrc:$dst),
1800 (ins crrc:$cond, vsrc:$T, vsrc:$F, i32imm:$BROPC),
1803 def SELECT_VSRC: PPCCustomInserterPseudo<(outs vsrc:$dst),
1804 (ins crbitrc:$cond, vsrc:$T, vsrc:$F),
1807 (select i1:$cond, v2f64:$T, v2f64:$F))]>;
1808 def SELECT_CC_VSFRC: PPCCustomInserterPseudo<(outs f8rc:$dst),
1809 (ins crrc:$cond, f8rc:$T, f8rc:$F,
1810 i32imm:$BROPC), "#SELECT_CC_VSFRC",
1812 def SELECT_VSFRC: PPCCustomInserterPseudo<(outs f8rc:$dst),
1813 (ins crbitrc:$cond, f8rc:$T, f8rc:$F),
1816 (select i1:$cond, f64:$T, f64:$F))]>;
1817 def SELECT_CC_VSSRC: PPCCustomInserterPseudo<(outs f4rc:$dst),
1818 (ins crrc:$cond, f4rc:$T, f4rc:$F,
1819 i32imm:$BROPC), "#SELECT_CC_VSSRC",
1821 def SELECT_VSSRC: PPCCustomInserterPseudo<(outs f4rc:$dst),
1822 (ins crbitrc:$cond, f4rc:$T, f4rc:$F),
1825 (select i1:$cond, f32:$T, f32:$F))]>;
1829 //----------------------------- DAG Definitions ------------------------------//
1831 // Output dag used to bitcast f32 to i32 and f64 to i64
1833 dag FltToInt = (i32 (MFVSRWZ (EXTRACT_SUBREG (XSCVDPSPN $A), sub_64)));
1834 dag DblToLong = (i64 (MFVSRD $A));
1838 dag F32Min = (COPY_TO_REGCLASS (XSMINDP (COPY_TO_REGCLASS $A, VSFRC),
1839 (COPY_TO_REGCLASS $B, VSFRC)),
1841 dag F32Max = (COPY_TO_REGCLASS (XSMAXDP (COPY_TO_REGCLASS $A, VSFRC),
1842 (COPY_TO_REGCLASS $B, VSFRC)),
1847 dag Li8 = (i32 (extloadi8 ForceXForm:$src));
1848 dag ZELi8 = (i32 (zextloadi8 ForceXForm:$src));
1849 dag ZELi8i64 = (i64 (zextloadi8 ForceXForm:$src));
1850 dag SELi8 = (i32 (sext_inreg (extloadi8 ForceXForm:$src), i8));
1851 dag SELi8i64 = (i64 (sext_inreg (extloadi8 ForceXForm:$src), i8));
1853 dag Li16 = (i32 (extloadi16 ForceXForm:$src));
1854 dag ZELi16 = (i32 (zextloadi16 ForceXForm:$src));
1855 dag ZELi16i64 = (i64 (zextloadi16 ForceXForm:$src));
1856 dag SELi16 = (i32 (sextloadi16 ForceXForm:$src));
1857 dag SELi16i64 = (i64 (sextloadi16 ForceXForm:$src));
1859 dag Li32 = (i32 (load ForceXForm:$src));
1862 def DWToSPExtractConv {
1863 dag El0US1 = (f32 (PPCfcfidus
1864 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 0))))));
1865 dag El1US1 = (f32 (PPCfcfidus
1866 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 1))))));
1867 dag El0US2 = (f32 (PPCfcfidus
1868 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 0))))));
1869 dag El1US2 = (f32 (PPCfcfidus
1870 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 1))))));
1871 dag El0SS1 = (f32 (PPCfcfids
1872 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 0))))));
1873 dag El1SS1 = (f32 (PPCfcfids
1874 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 1))))));
1875 dag El0SS2 = (f32 (PPCfcfids
1876 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 0))))));
1877 dag El1SS2 = (f32 (PPCfcfids
1878 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 1))))));
1879 dag BVU = (v4f32 (build_vector El0US1, El1US1, El0US2, El1US2));
1880 dag BVS = (v4f32 (build_vector El0SS1, El1SS1, El0SS2, El1SS2));
1883 def WToDPExtractConv {
1884 dag El0S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 0))));
1885 dag El1S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 1))));
1886 dag El2S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 2))));
1887 dag El3S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 3))));
1888 dag El0U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 0))));
1889 dag El1U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 1))));
1890 dag El2U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 2))));
1891 dag El3U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 3))));
1892 dag BV02S = (v2f64 (build_vector El0S, El2S));
1893 dag BV13S = (v2f64 (build_vector El1S, El3S));
1894 dag BV02U = (v2f64 (build_vector El0U, El2U));
1895 dag BV13U = (v2f64 (build_vector El1U, El3U));
1898 /* Direct moves of various widths from GPR's into VSR's. Each move lines
1899 the value up into element 0 (both BE and LE). Namely, entities smaller than
1900 a doubleword are shifted left and moved for BE. For LE, they're moved, then
1901 swapped to go into the least significant element of the VSR.
1907 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 56, 7));
1911 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 48, 15));
1915 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 32, 31));
1916 dag BE_DWORD_0 = (MTVSRD $A);
1918 dag LE_MTVSRW = (MTVSRD (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32));
1919 dag LE_WORD_1 = (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1920 LE_MTVSRW, sub_64));
1921 dag LE_WORD_0 = (XXPERMDI LE_WORD_1, LE_WORD_1, 2);
1922 dag LE_DWORD_1 = (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1923 BE_DWORD_0, sub_64));
1924 dag LE_DWORD_0 = (XXPERMDI LE_DWORD_1, LE_DWORD_1, 2);
1927 /* Patterns for extracting elements out of vectors. Integer elements are
1928 extracted using direct move operations. Patterns for extracting elements
1929 whose indices are not available at compile time are also provided with
1930 various _VARIABLE_ patterns.
1931 The numbering for the DAG's is for LE, but when used on BE, the correct
1932 LE element can just be used (i.e. LE_BYTE_2 == BE_BYTE_13).
1934 def VectorExtractions {
1935 // Doubleword extraction
1939 (XXPERMDI (COPY_TO_REGCLASS $S, VSRC),
1940 (COPY_TO_REGCLASS $S, VSRC), 2), sub_64));
1941 dag LE_DWORD_1 = (MFVSRD
1943 (v2i64 (COPY_TO_REGCLASS $S, VSRC)), sub_64));
1946 dag LE_WORD_0 = (MFVSRWZ (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64));
1947 dag LE_WORD_1 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 1), sub_64));
1948 dag LE_WORD_2 = (MFVSRWZ (EXTRACT_SUBREG
1949 (v2i64 (COPY_TO_REGCLASS $S, VSRC)), sub_64));
1950 dag LE_WORD_3 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 3), sub_64));
1952 // Halfword extraction
1953 dag LE_HALF_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 48), sub_32));
1954 dag LE_HALF_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 48, 48), sub_32));
1955 dag LE_HALF_2 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 32, 48), sub_32));
1956 dag LE_HALF_3 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 16, 48), sub_32));
1957 dag LE_HALF_4 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 0, 48), sub_32));
1958 dag LE_HALF_5 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 48, 48), sub_32));
1959 dag LE_HALF_6 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 32, 48), sub_32));
1960 dag LE_HALF_7 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 16, 48), sub_32));
1963 dag LE_BYTE_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 56), sub_32));
1964 dag LE_BYTE_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 56, 56), sub_32));
1965 dag LE_BYTE_2 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 48, 56), sub_32));
1966 dag LE_BYTE_3 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 40, 56), sub_32));
1967 dag LE_BYTE_4 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 32, 56), sub_32));
1968 dag LE_BYTE_5 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 24, 56), sub_32));
1969 dag LE_BYTE_6 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 16, 56), sub_32));
1970 dag LE_BYTE_7 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 8, 56), sub_32));
1971 dag LE_BYTE_8 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 0, 56), sub_32));
1972 dag LE_BYTE_9 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 56, 56), sub_32));
1973 dag LE_BYTE_10 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 48, 56), sub_32));
1974 dag LE_BYTE_11 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 40, 56), sub_32));
1975 dag LE_BYTE_12 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 32, 56), sub_32));
1976 dag LE_BYTE_13 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 24, 56), sub_32));
1977 dag LE_BYTE_14 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 16, 56), sub_32));
1978 dag LE_BYTE_15 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 8, 56), sub_32));
1980 /* Variable element number (BE and LE patterns must be specified separately)
1981 This is a rather involved process.
1983 Conceptually, this is how the move is accomplished:
1984 1. Identify which doubleword contains the element
1985 2. Shift in the VMX register so that the correct doubleword is correctly
1986 lined up for the MFVSRD
1987 3. Perform the move so that the element (along with some extra stuff)
1989 4. Right shift within the GPR so that the element is right-justified
1991 Of course, the index is an element number which has a different meaning
1992 on LE/BE so the patterns have to be specified separately.
1994 Note: The final result will be the element right-justified with high
1995 order bits being arbitrarily defined (namely, whatever was in the
1996 vector register to the left of the value originally).
2001 - For elements 0-7, we shift left by 8 bytes since they're on the right
2002 - For elements 8-15, we need not shift (shift left by zero bytes)
2003 This is accomplished by inverting the bits of the index and AND-ing
2004 with 0x8 (i.e. clearing all bits of the index and inverting bit 60).
2006 dag LE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDC8 (LI8 8), $Idx)));
2009 // - Now that we set up the shift amount, we shift in the VMX register
2010 dag LE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, LE_VBYTE_PERM_VEC));
2013 // - The doubleword containing our element is moved to a GPR
2014 dag LE_MV_VBYTE = (MFVSRD
2016 (v2i64 (COPY_TO_REGCLASS LE_VBYTE_PERMUTE, VSRC)),
2020 - Truncate the element number to the range 0-7 (8-15 are symmetrical
2021 and out of range values are truncated accordingly)
2022 - Multiply by 8 as we need to shift right by the number of bits, not bytes
2023 - Shift right in the GPR by the calculated value
2025 dag LE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 7), $Idx), 3, 60),
2027 dag LE_VARIABLE_BYTE = (EXTRACT_SUBREG (SRD LE_MV_VBYTE, LE_VBYTE_SHIFT),
2030 /* LE variable halfword
2032 - For elements 0-3, we shift left by 8 since they're on the right
2033 - For elements 4-7, we need not shift (shift left by zero bytes)
2034 Similarly to the byte pattern, we invert the bits of the index, but we
2035 AND with 0x4 (i.e. clear all bits of the index and invert bit 61).
2036 Of course, the shift is still by 8 bytes, so we must multiply by 2.
2038 dag LE_VHALF_PERM_VEC =
2039 (v16i8 (LVSL ZERO8, (RLDICR (ANDC8 (LI8 4), $Idx), 1, 62)));
2042 // - Now that we set up the shift amount, we shift in the VMX register
2043 dag LE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, LE_VHALF_PERM_VEC));
2046 // - The doubleword containing our element is moved to a GPR
2047 dag LE_MV_VHALF = (MFVSRD
2049 (v2i64 (COPY_TO_REGCLASS LE_VHALF_PERMUTE, VSRC)),
2053 - Truncate the element number to the range 0-3 (4-7 are symmetrical
2054 and out of range values are truncated accordingly)
2055 - Multiply by 16 as we need to shift right by the number of bits
2056 - Shift right in the GPR by the calculated value
2058 dag LE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 3), $Idx), 4, 59),
2060 dag LE_VARIABLE_HALF = (EXTRACT_SUBREG (SRD LE_MV_VHALF, LE_VHALF_SHIFT),
2065 - For elements 0-1, we shift left by 8 since they're on the right
2066 - For elements 2-3, we need not shift
2068 dag LE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
2069 (RLDICR (ANDC8 (LI8 2), $Idx), 2, 61)));
2072 // - Now that we set up the shift amount, we shift in the VMX register
2073 dag LE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, LE_VWORD_PERM_VEC));
2076 // - The doubleword containing our element is moved to a GPR
2077 dag LE_MV_VWORD = (MFVSRD
2079 (v2i64 (COPY_TO_REGCLASS LE_VWORD_PERMUTE, VSRC)),
2083 - Truncate the element number to the range 0-1 (2-3 are symmetrical
2084 and out of range values are truncated accordingly)
2085 - Multiply by 32 as we need to shift right by the number of bits
2086 - Shift right in the GPR by the calculated value
2088 dag LE_VWORD_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 1), $Idx), 5, 58),
2090 dag LE_VARIABLE_WORD = (EXTRACT_SUBREG (SRD LE_MV_VWORD, LE_VWORD_SHIFT),
2093 /* LE variable doubleword
2095 - For element 0, we shift left by 8 since it's on the right
2096 - For element 1, we need not shift
2098 dag LE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
2099 (RLDICR (ANDC8 (LI8 1), $Idx), 3, 60)));
2102 // - Now that we set up the shift amount, we shift in the VMX register
2103 dag LE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, LE_VDWORD_PERM_VEC));
2106 // - The doubleword containing our element is moved to a GPR
2107 // - Number 4. is not needed for the doubleword as the value is 64-bits
2108 dag LE_VARIABLE_DWORD =
2109 (MFVSRD (EXTRACT_SUBREG
2110 (v2i64 (COPY_TO_REGCLASS LE_VDWORD_PERMUTE, VSRC)),
2113 /* LE variable float
2114 - Shift the vector to line up the desired element to BE Word 0
2115 - Convert 32-bit float to a 64-bit single precision float
2117 dag LE_VFLOAT_PERM_VEC = (v16i8 (LVSL ZERO8,
2118 (RLDICR (XOR8 (LI8 3), $Idx), 2, 61)));
2119 dag LE_VFLOAT_PERMUTE = (VPERM $S, $S, LE_VFLOAT_PERM_VEC);
2120 dag LE_VARIABLE_FLOAT = (XSCVSPDPN LE_VFLOAT_PERMUTE);
2122 /* LE variable double
2123 Same as the LE doubleword except there is no move.
2125 dag LE_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)),
2126 (v16i8 (COPY_TO_REGCLASS $S, VRRC)),
2127 LE_VDWORD_PERM_VEC));
2128 dag LE_VARIABLE_DOUBLE = (COPY_TO_REGCLASS LE_VDOUBLE_PERMUTE, VSRC);
2131 The algorithm here is the same as the LE variable byte except:
2132 - The shift in the VMX register is by 0/8 for opposite element numbers so
2133 we simply AND the element number with 0x8
2134 - The order of elements after the move to GPR is reversed, so we invert
2135 the bits of the index prior to truncating to the range 0-7
2137 dag BE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDI8_rec $Idx, 8)));
2138 dag BE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, BE_VBYTE_PERM_VEC));
2139 dag BE_MV_VBYTE = (MFVSRD
2141 (v2i64 (COPY_TO_REGCLASS BE_VBYTE_PERMUTE, VSRC)),
2143 dag BE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 7), $Idx), 3, 60),
2145 dag BE_VARIABLE_BYTE = (EXTRACT_SUBREG (SRD BE_MV_VBYTE, BE_VBYTE_SHIFT),
2148 /* BE variable halfword
2149 The algorithm here is the same as the LE variable halfword except:
2150 - The shift in the VMX register is by 0/8 for opposite element numbers so
2151 we simply AND the element number with 0x4 and multiply by 2
2152 - The order of elements after the move to GPR is reversed, so we invert
2153 the bits of the index prior to truncating to the range 0-3
2155 dag BE_VHALF_PERM_VEC = (v16i8 (LVSL ZERO8,
2156 (RLDICR (ANDI8_rec $Idx, 4), 1, 62)));
2157 dag BE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, BE_VHALF_PERM_VEC));
2158 dag BE_MV_VHALF = (MFVSRD
2160 (v2i64 (COPY_TO_REGCLASS BE_VHALF_PERMUTE, VSRC)),
2162 dag BE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 3), $Idx), 4, 59),
2164 dag BE_VARIABLE_HALF = (EXTRACT_SUBREG (SRD BE_MV_VHALF, BE_VHALF_SHIFT),
2168 The algorithm is the same as the LE variable word except:
2169 - The shift in the VMX register happens for opposite element numbers
2170 - The order of elements after the move to GPR is reversed, so we invert
2171 the bits of the index prior to truncating to the range 0-1
2173 dag BE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
2174 (RLDICR (ANDI8_rec $Idx, 2), 2, 61)));
2175 dag BE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VWORD_PERM_VEC));
2176 dag BE_MV_VWORD = (MFVSRD
2178 (v2i64 (COPY_TO_REGCLASS BE_VWORD_PERMUTE, VSRC)),
2180 dag BE_VWORD_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 1), $Idx), 5, 58),
2182 dag BE_VARIABLE_WORD = (EXTRACT_SUBREG (SRD BE_MV_VWORD, BE_VWORD_SHIFT),
2185 /* BE variable doubleword
2186 Same as the LE doubleword except we shift in the VMX register for opposite
2189 dag BE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
2190 (RLDICR (ANDI8_rec $Idx, 1), 3, 60)));
2191 dag BE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VDWORD_PERM_VEC));
2192 dag BE_VARIABLE_DWORD =
2193 (MFVSRD (EXTRACT_SUBREG
2194 (v2i64 (COPY_TO_REGCLASS BE_VDWORD_PERMUTE, VSRC)),
2197 /* BE variable float
2198 - Shift the vector to line up the desired element to BE Word 0
2199 - Convert 32-bit float to a 64-bit single precision float
2201 dag BE_VFLOAT_PERM_VEC = (v16i8 (LVSL ZERO8, (RLDICR $Idx, 2, 61)));
2202 dag BE_VFLOAT_PERMUTE = (VPERM $S, $S, BE_VFLOAT_PERM_VEC);
2203 dag BE_VARIABLE_FLOAT = (XSCVSPDPN BE_VFLOAT_PERMUTE);
2205 // BE variable float 32-bit version
2206 dag BE_32B_VFLOAT_PERM_VEC = (v16i8 (LVSL (i32 ZERO), (RLWINM $Idx, 2, 0, 29)));
2207 dag BE_32B_VFLOAT_PERMUTE = (VPERM $S, $S, BE_32B_VFLOAT_PERM_VEC);
2208 dag BE_32B_VARIABLE_FLOAT = (XSCVSPDPN BE_32B_VFLOAT_PERMUTE);
2210 /* BE variable double
2211 Same as the BE doubleword except there is no move.
2213 dag BE_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)),
2214 (v16i8 (COPY_TO_REGCLASS $S, VRRC)),
2215 BE_VDWORD_PERM_VEC));
2216 dag BE_VARIABLE_DOUBLE = (COPY_TO_REGCLASS BE_VDOUBLE_PERMUTE, VSRC);
2218 // BE variable double 32-bit version
2219 dag BE_32B_VDWORD_PERM_VEC = (v16i8 (LVSL (i32 ZERO),
2220 (RLWINM (ANDI_rec $Idx, 1), 3, 0, 28)));
2221 dag BE_32B_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)),
2222 (v16i8 (COPY_TO_REGCLASS $S, VRRC)),
2223 BE_32B_VDWORD_PERM_VEC));
2224 dag BE_32B_VARIABLE_DOUBLE = (COPY_TO_REGCLASS BE_32B_VDOUBLE_PERMUTE, VSRC);
2228 dag F32_TO_BE_WORD1 = (v4f32 (XSCVDPSPN $B));
2229 dag I32_TO_BE_WORD1 = (SUBREG_TO_REG (i64 1), (MTVSRWZ $B), sub_64);
2232 // Integer extend helper dags 32 -> 64
2234 dag A = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32);
2235 dag B = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $B, sub_32);
2236 dag C = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $C, sub_32);
2237 dag D = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $D, sub_32);
2241 dag A0 = (f32 (any_fpround (f64 (extractelt v2f64:$A, 0))));
2242 dag A1 = (f32 (any_fpround (f64 (extractelt v2f64:$A, 1))));
2243 dag B0 = (f32 (any_fpround (f64 (extractelt v2f64:$B, 0))));
2244 dag B1 = (f32 (any_fpround (f64 (extractelt v2f64:$B, 1))));
2248 dag A0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 0))))));
2249 dag A1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 1))))));
2250 dag B0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 0))))));
2251 dag B1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 1))))));
2252 dag A0U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$A, 0))))));
2253 dag A1U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$A, 1))))));
2254 dag B0U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$B, 0))))));
2255 dag B1U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$B, 1))))));
2259 dag LE_A0 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 0)), i8));
2260 dag LE_A1 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 4)), i8));
2261 dag LE_A2 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 8)), i8));
2262 dag LE_A3 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 12)), i8));
2263 dag BE_A0 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 3)), i8));
2264 dag BE_A1 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 7)), i8));
2265 dag BE_A2 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 11)), i8));
2266 dag BE_A3 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 15)), i8));
2270 dag LE_A0 = (i64 (sext_inreg
2271 (i64 (anyext (i32 (vector_extract v16i8:$A, 0)))), i8));
2272 dag LE_A1 = (i64 (sext_inreg
2273 (i64 (anyext (i32 (vector_extract v16i8:$A, 8)))), i8));
2274 dag BE_A0 = (i64 (sext_inreg
2275 (i64 (anyext (i32 (vector_extract v16i8:$A, 7)))), i8));
2276 dag BE_A1 = (i64 (sext_inreg
2277 (i64 (anyext (i32 (vector_extract v16i8:$A, 15)))), i8));
2281 dag LE_A0 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 0)), i16));
2282 dag LE_A1 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 2)), i16));
2283 dag LE_A2 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 4)), i16));
2284 dag LE_A3 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 6)), i16));
2285 dag BE_A0 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 1)), i16));
2286 dag BE_A1 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 3)), i16));
2287 dag BE_A2 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 5)), i16));
2288 dag BE_A3 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 7)), i16));
2292 dag LE_A0 = (i64 (sext_inreg
2293 (i64 (anyext (i32 (vector_extract v8i16:$A, 0)))), i16));
2294 dag LE_A1 = (i64 (sext_inreg
2295 (i64 (anyext (i32 (vector_extract v8i16:$A, 4)))), i16));
2296 dag BE_A0 = (i64 (sext_inreg
2297 (i64 (anyext (i32 (vector_extract v8i16:$A, 3)))), i16));
2298 dag BE_A1 = (i64 (sext_inreg
2299 (i64 (anyext (i32 (vector_extract v8i16:$A, 7)))), i16));
2303 dag LE_A0 = (i64 (sext (i32 (vector_extract v4i32:$A, 0))));
2304 dag LE_A1 = (i64 (sext (i32 (vector_extract v4i32:$A, 2))));
2305 dag BE_A0 = (i64 (sext (i32 (vector_extract v4i32:$A, 1))));
2306 dag BE_A1 = (i64 (sext (i32 (vector_extract v4i32:$A, 3))));
2310 dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (extloadf32 ForceXForm:$A)))));
2313 dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (extloadf32 ForceXForm:$A)))));
2316 dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 ForceXForm:$A)))));
2318 def FltToLongLoadP9 {
2319 dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 DSForm:$A)))));
2321 def FltToULongLoad {
2322 dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 ForceXForm:$A)))));
2324 def FltToULongLoadP9 {
2325 dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 DSForm:$A)))));
2328 dag A = (i64 (PPCmfvsr (f64 (PPCfctidz (fpextend f32:$A)))));
2331 dag A = (i64 (PPCmfvsr (f64 (PPCfctiduz (fpextend f32:$A)))));
2334 dag A = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$A))));
2335 dag B = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$B))));
2336 dag C = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$C))));
2337 dag D = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$D))));
2340 dag A = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$A))));
2341 dag B = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$B))));
2342 dag C = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$C))));
2343 dag D = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$D))));
2346 dag A = (i64 (PPCmfvsr (f64 (PPCfctidz f64:$A))));
2349 dag A = (i64 (PPCmfvsr (f64 (PPCfctiduz f64:$A))));
2352 dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load ForceXForm:$A)))));
2354 def DblToIntLoadP9 {
2355 dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load DSForm:$A)))));
2358 dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load ForceXForm:$A)))));
2360 def DblToUIntLoadP9 {
2361 dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load DSForm:$A)))));
2364 dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (load ForceXForm:$A)))));
2366 def DblToULongLoad {
2367 dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (load ForceXForm:$A)))));
2370 // FP load dags (for f32 -> v4f32)
2372 dag A = (f32 (load ForceXForm:$A));
2373 dag B = (f32 (load ForceXForm:$B));
2374 dag C = (f32 (load ForceXForm:$C));
2375 dag D = (f32 (load ForceXForm:$D));
2378 // FP merge dags (for f32 -> v4f32)
2380 dag LD32A = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64);
2381 dag LD32B = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$B), sub_64);
2382 dag LD32C = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$C), sub_64);
2383 dag LD32D = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$D), sub_64);
2384 dag AC = (XVCVDPSP (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64),
2385 (SUBREG_TO_REG (i64 1), $C, sub_64), 0));
2386 dag BD = (XVCVDPSP (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64),
2387 (SUBREG_TO_REG (i64 1), $D, sub_64), 0));
2388 dag ABhToFlt = (XVCVDPSP (XXPERMDI $A, $B, 0));
2389 dag ABlToFlt = (XVCVDPSP (XXPERMDI $A, $B, 3));
2390 dag BAhToFlt = (XVCVDPSP (XXPERMDI $B, $A, 0));
2391 dag BAlToFlt = (XVCVDPSP (XXPERMDI $B, $A, 3));
2394 // Word-element merge dags - conversions from f64 to i32 merged into vectors.
2396 // For big endian, we merge low and hi doublewords (A, B).
2397 dag A0B0 = (v2f64 (XXPERMDI v2f64:$A, v2f64:$B, 0));
2398 dag A1B1 = (v2f64 (XXPERMDI v2f64:$A, v2f64:$B, 3));
2399 dag CVA1B1S = (v4i32 (XVCVDPSXWS A1B1));
2400 dag CVA0B0S = (v4i32 (XVCVDPSXWS A0B0));
2401 dag CVA1B1U = (v4i32 (XVCVDPUXWS A1B1));
2402 dag CVA0B0U = (v4i32 (XVCVDPUXWS A0B0));
2404 // For little endian, we merge low and hi doublewords (B, A).
2405 dag B1A1 = (v2f64 (XXPERMDI v2f64:$B, v2f64:$A, 0));
2406 dag B0A0 = (v2f64 (XXPERMDI v2f64:$B, v2f64:$A, 3));
2407 dag CVB1A1S = (v4i32 (XVCVDPSXWS B1A1));
2408 dag CVB0A0S = (v4i32 (XVCVDPSXWS B0A0));
2409 dag CVB1A1U = (v4i32 (XVCVDPUXWS B1A1));
2410 dag CVB0A0U = (v4i32 (XVCVDPUXWS B0A0));
2412 // For big endian, we merge hi doublewords of (A, C) and (B, D), convert
2414 dag AC = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$A, sub_64),
2415 (SUBREG_TO_REG (i64 1), f64:$C, sub_64), 0));
2416 dag BD = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$B, sub_64),
2417 (SUBREG_TO_REG (i64 1), f64:$D, sub_64), 0));
2418 dag CVACS = (v4i32 (XVCVDPSXWS AC));
2419 dag CVBDS = (v4i32 (XVCVDPSXWS BD));
2420 dag CVACU = (v4i32 (XVCVDPUXWS AC));
2421 dag CVBDU = (v4i32 (XVCVDPUXWS BD));
2423 // For little endian, we merge hi doublewords of (D, B) and (C, A), convert
2425 dag DB = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$D, sub_64),
2426 (SUBREG_TO_REG (i64 1), f64:$B, sub_64), 0));
2427 dag CA = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$C, sub_64),
2428 (SUBREG_TO_REG (i64 1), f64:$A, sub_64), 0));
2429 dag CVDBS = (v4i32 (XVCVDPSXWS DB));
2430 dag CVCAS = (v4i32 (XVCVDPSXWS CA));
2431 dag CVDBU = (v4i32 (XVCVDPUXWS DB));
2432 dag CVCAU = (v4i32 (XVCVDPUXWS CA));
2436 dag SGTW = (v2i64 (v2i64 (VCMPGTSW v2i64:$vA, v2i64:$vB)));
2437 dag UGTW = (v2i64 (v2i64 (VCMPGTUW v2i64:$vA, v2i64:$vB)));
2438 dag EQW = (v2i64 (v2i64 (VCMPEQUW v2i64:$vA, v2i64:$vB)));
2439 dag UGTWSHAND = (v2i64 (XXLAND (v2i64 (XXSLDWI UGTW, UGTW, 1)), EQW));
2440 dag EQWSHAND = (v2i64 (XXLAND (v2i64 (XXSLDWI EQW, EQW, 1)), EQW));
2441 dag SGTWOR = (v2i64 (XXLOR SGTW, UGTWSHAND));
2442 dag UGTWOR = (v2i64 (XXLOR UGTW, UGTWSHAND));
2443 dag MRGSGT = (v2i64 (XXPERMDI (v2i64 (XXSPLTW SGTWOR, 0)),
2444 (v2i64 (XXSPLTW SGTWOR, 2)), 0));
2445 dag MRGUGT = (v2i64 (XXPERMDI (v2i64 (XXSPLTW UGTWOR, 0)),
2446 (v2i64 (XXSPLTW UGTWOR, 2)), 0));
2447 dag MRGEQ = (v2i64 (XXPERMDI (v2i64 (XXSPLTW EQWSHAND, 0)),
2448 (v2i64 (XXSPLTW EQWSHAND, 2)), 0));
2451 //---------------------------- Anonymous Patterns ----------------------------//
2452 // Predicate combinations are kept in roughly chronological order in terms of
2453 // instruction availability in the architecture. For example, VSX came in with
2454 // ISA 2.06 (Power7). There have since been additions in ISA 2.07 (Power8) and
2455 // ISA 3.0 (Power9). However, the granularity of features on later subtargets
2456 // is finer for various reasons. For example, we have Power8Vector,
2457 // Power8Altivec, DirectMove that all came in with ISA 2.07. The situation is
2458 // similar with ISA 3.0 with Power9Vector, Power9Altivec, IsISA3_0. Then there
2459 // are orthogonal predicates such as endianness for which the order was
2460 // arbitrarily chosen to be Big, Little.
2462 // Predicate combinations available:
2463 // [HasVSX, IsLittleEndian, HasP8Altivec] Altivec patterns using VSX instr.
2464 // [HasVSX, IsBigEndian, HasP8Altivec] Altivec patterns using VSX instr.
2466 // [HasVSX, IsBigEndian]
2467 // [HasVSX, IsLittleEndian]
2468 // [HasVSX, NoP9Vector]
2469 // [HasVSX, NoP9Vector, IsLittleEndian]
2470 // [HasVSX, NoP9Vector, IsBigEndian]
2471 // [HasVSX, HasOnlySwappingMemOps]
2472 // [HasVSX, HasOnlySwappingMemOps, IsBigEndian]
2473 // [HasVSX, HasP8Vector]
2474 // [HasVSX, HasP8Vector, IsBigEndian]
2475 // [HasVSX, HasP8Vector, IsBigEndian, IsPPC64]
2476 // [HasVSX, HasP8Vector, IsLittleEndian]
2477 // [HasVSX, HasP8Vector, NoP9Vector, IsBigEndian, IsPPC64]
2478 // [HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian]
2479 // [HasVSX, HasP8Altivec]
2480 // [HasVSX, HasDirectMove]
2481 // [HasVSX, HasDirectMove, IsBigEndian]
2482 // [HasVSX, HasDirectMove, IsLittleEndian]
2483 // [HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian, IsPPC64]
2484 // [HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64]
2485 // [HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian]
2486 // [HasVSX, HasDirectMove, NoP9Vector, IsLittleEndian]
2487 // [HasVSX, HasP9Vector]
2488 // [HasVSX, HasP9Vector, NoP10Vector]
2489 // [HasVSX, HasP9Vector, IsBigEndian]
2490 // [HasVSX, HasP9Vector, IsBigEndian, IsPPC64]
2491 // [HasVSX, HasP9Vector, IsLittleEndian]
2492 // [HasVSX, HasP9Altivec]
2493 // [HasVSX, HasP9Altivec, IsBigEndian, IsPPC64]
2494 // [HasVSX, HasP9Altivec, IsLittleEndian]
2495 // [HasVSX, IsISA3_0, HasDirectMove, IsBigEndian, IsPPC64]
2496 // [HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian]
2498 // These Altivec patterns are here because we need a VSX instruction to match
2499 // the intrinsic (but only for little endian system).
2500 let Predicates = [HasVSX, IsLittleEndian, HasP8Altivec] in
2501 def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor v16i8:$a,
2502 v16i8:$b, v16i8:$c)),
2503 (v16i8 (VPERMXOR $a, $b, (XXLNOR (COPY_TO_REGCLASS $c, VSRC),
2504 (COPY_TO_REGCLASS $c, VSRC))))>;
2505 let Predicates = [HasVSX, IsBigEndian, HasP8Altivec] in
2506 def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor v16i8:$a,
2507 v16i8:$b, v16i8:$c)),
2508 (v16i8 (VPERMXOR $a, $b, $c))>;
2509 let Predicates = [HasVSX, HasP8Altivec] in
2510 def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor_be v16i8:$a,
2511 v16i8:$b, v16i8:$c)),
2512 (v16i8 (VPERMXOR $a, $b, $c))>;
2514 let AddedComplexity = 400 in {
2515 // Valid for any VSX subtarget, regardless of endianness.
2516 let Predicates = [HasVSX] in {
2517 def : Pat<(v4i32 (vnot v4i32:$A)),
2518 (v4i32 (XXLNOR $A, $A))>;
2519 def : Pat<(v4i32 (or (and (vnot v4i32:$C), v4i32:$A),
2520 (and v4i32:$B, v4i32:$C))),
2521 (v4i32 (XXSEL $A, $B, $C))>;
2523 // Additional fnmsub pattern for PPC specific ISD opcode
2524 def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C),
2525 (XSNMSUBADP $C, $A, $B)>;
2526 def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)),
2527 (XSMSUBADP $C, $A, $B)>;
2528 def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)),
2529 (XSNMADDADP $C, $A, $B)>;
2531 def : Pat<(PPCfnmsub v2f64:$A, v2f64:$B, v2f64:$C),
2532 (XVNMSUBADP $C, $A, $B)>;
2533 def : Pat<(fneg (PPCfnmsub v2f64:$A, v2f64:$B, v2f64:$C)),
2534 (XVMSUBADP $C, $A, $B)>;
2535 def : Pat<(PPCfnmsub v2f64:$A, v2f64:$B, (fneg v2f64:$C)),
2536 (XVNMADDADP $C, $A, $B)>;
2538 def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C),
2539 (XVNMSUBASP $C, $A, $B)>;
2540 def : Pat<(fneg (PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C)),
2541 (XVMSUBASP $C, $A, $B)>;
2542 def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, (fneg v4f32:$C)),
2543 (XVNMADDASP $C, $A, $B)>;
2545 def : Pat<(PPCfsqrt f64:$frA), (XSSQRTDP $frA)>;
2546 def : Pat<(PPCfsqrt v2f64:$frA), (XVSQRTDP $frA)>;
2547 def : Pat<(PPCfsqrt v4f32:$frA), (XVSQRTSP $frA)>;
2549 def : Pat<(v2f64 (bitconvert v4f32:$A)),
2550 (COPY_TO_REGCLASS $A, VSRC)>;
2551 def : Pat<(v2f64 (bitconvert v4i32:$A)),
2552 (COPY_TO_REGCLASS $A, VSRC)>;
2553 def : Pat<(v2f64 (bitconvert v8i16:$A)),
2554 (COPY_TO_REGCLASS $A, VSRC)>;
2555 def : Pat<(v2f64 (bitconvert v16i8:$A)),
2556 (COPY_TO_REGCLASS $A, VSRC)>;
2558 def : Pat<(v4f32 (bitconvert v2f64:$A)),
2559 (COPY_TO_REGCLASS $A, VRRC)>;
2560 def : Pat<(v4i32 (bitconvert v2f64:$A)),
2561 (COPY_TO_REGCLASS $A, VRRC)>;
2562 def : Pat<(v8i16 (bitconvert v2f64:$A)),
2563 (COPY_TO_REGCLASS $A, VRRC)>;
2564 def : Pat<(v16i8 (bitconvert v2f64:$A)),
2565 (COPY_TO_REGCLASS $A, VRRC)>;
2567 def : Pat<(v2i64 (bitconvert v4f32:$A)),
2568 (COPY_TO_REGCLASS $A, VSRC)>;
2569 def : Pat<(v2i64 (bitconvert v4i32:$A)),
2570 (COPY_TO_REGCLASS $A, VSRC)>;
2571 def : Pat<(v2i64 (bitconvert v8i16:$A)),
2572 (COPY_TO_REGCLASS $A, VSRC)>;
2573 def : Pat<(v2i64 (bitconvert v16i8:$A)),
2574 (COPY_TO_REGCLASS $A, VSRC)>;
2576 def : Pat<(v4f32 (bitconvert v2i64:$A)),
2577 (COPY_TO_REGCLASS $A, VRRC)>;
2578 def : Pat<(v4i32 (bitconvert v2i64:$A)),
2579 (COPY_TO_REGCLASS $A, VRRC)>;
2580 def : Pat<(v8i16 (bitconvert v2i64:$A)),
2581 (COPY_TO_REGCLASS $A, VRRC)>;
2582 def : Pat<(v16i8 (bitconvert v2i64:$A)),
2583 (COPY_TO_REGCLASS $A, VRRC)>;
2585 def : Pat<(v2f64 (bitconvert v2i64:$A)),
2586 (COPY_TO_REGCLASS $A, VRRC)>;
2587 def : Pat<(v2i64 (bitconvert v2f64:$A)),
2588 (COPY_TO_REGCLASS $A, VRRC)>;
2590 def : Pat<(v2f64 (bitconvert v1i128:$A)),
2591 (COPY_TO_REGCLASS $A, VRRC)>;
2592 def : Pat<(v1i128 (bitconvert v2f64:$A)),
2593 (COPY_TO_REGCLASS $A, VRRC)>;
2595 def : Pat<(v2i64 (bitconvert f128:$A)),
2596 (COPY_TO_REGCLASS $A, VRRC)>;
2597 def : Pat<(v4i32 (bitconvert f128:$A)),
2598 (COPY_TO_REGCLASS $A, VRRC)>;
2599 def : Pat<(v8i16 (bitconvert f128:$A)),
2600 (COPY_TO_REGCLASS $A, VRRC)>;
2601 def : Pat<(v16i8 (bitconvert f128:$A)),
2602 (COPY_TO_REGCLASS $A, VRRC)>;
2604 def : Pat<(v2f64 (PPCsvec2fp v4i32:$C, 0)),
2605 (v2f64 (XVCVSXWDP (v2i64 (XXMRGHW $C, $C))))>;
2606 def : Pat<(v2f64 (PPCsvec2fp v4i32:$C, 1)),
2607 (v2f64 (XVCVSXWDP (v2i64 (XXMRGLW $C, $C))))>;
2609 def : Pat<(v2f64 (PPCuvec2fp v4i32:$C, 0)),
2610 (v2f64 (XVCVUXWDP (v2i64 (XXMRGHW $C, $C))))>;
2611 def : Pat<(v2f64 (PPCuvec2fp v4i32:$C, 1)),
2612 (v2f64 (XVCVUXWDP (v2i64 (XXMRGLW $C, $C))))>;
2614 def : Pat<(v2f64 (PPCfpexth v4f32:$C, 0)), (XVCVSPDP (XXMRGHW $C, $C))>;
2615 def : Pat<(v2f64 (PPCfpexth v4f32:$C, 1)), (XVCVSPDP (XXMRGLW $C, $C))>;
2618 def : Pat<(v2f64 (PPCxxswapd v2f64:$src)), (XXPERMDI $src, $src, 2)>;
2619 def : Pat<(v2i64 (PPCxxswapd v2i64:$src)), (XXPERMDI $src, $src, 2)>;
2620 def : Pat<(v4f32 (PPCxxswapd v4f32:$src)), (XXPERMDI $src, $src, 2)>;
2621 def : Pat<(v4i32 (PPCxxswapd v4i32:$src)), (XXPERMDI $src, $src, 2)>;
2622 def : Pat<(v2f64 (PPCswapNoChain v2f64:$src)), (XXPERMDI $src, $src, 2)>;
2624 // PPCvecshl XT, XA, XA, 2 can be selected to both XXSLDWI XT,XA,XA,2 and
2625 // XXSWAPD XT,XA (i.e. XXPERMDI XT,XA,XA,2), the later one is more profitable.
2626 def : Pat<(v4i32 (PPCvecshl v4i32:$src, v4i32:$src, 2)),
2627 (XXPERMDI $src, $src, 2)>;
2630 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLT)),
2631 (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
2632 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULT)),
2633 (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
2634 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLE)),
2635 (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>;
2636 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULE)),
2637 (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>;
2638 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETEQ)),
2639 (SELECT_VSRC (CREQV $lhs, $rhs), $tval, $fval)>;
2640 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGE)),
2641 (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>;
2642 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGE)),
2643 (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>;
2644 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGT)),
2645 (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
2646 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGT)),
2647 (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
2648 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETNE)),
2649 (SELECT_VSRC (CRXOR $lhs, $rhs), $tval, $fval)>;
2651 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
2652 (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>;
2653 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
2654 (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>;
2655 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
2656 (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>;
2657 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
2658 (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>;
2659 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
2660 (SELECT_VSFRC (CREQV $lhs, $rhs), $tval, $fval)>;
2661 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
2662 (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>;
2663 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
2664 (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>;
2665 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
2666 (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>;
2667 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
2668 (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>;
2669 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
2670 (SELECT_VSFRC (CRXOR $lhs, $rhs), $tval, $fval)>;
2673 def : Pat<(int_ppc_vsx_xvdivsp v4f32:$A, v4f32:$B),
2675 def : Pat<(int_ppc_vsx_xvdivdp v2f64:$A, v2f64:$B),
2678 // Vector test for software divide and sqrt.
2679 def : Pat<(i32 (int_ppc_vsx_xvtdivdp v2f64:$A, v2f64:$B)),
2680 (COPY_TO_REGCLASS (XVTDIVDP $A, $B), GPRC)>;
2681 def : Pat<(i32 (int_ppc_vsx_xvtdivsp v4f32:$A, v4f32:$B)),
2682 (COPY_TO_REGCLASS (XVTDIVSP $A, $B), GPRC)>;
2683 def : Pat<(i32 (int_ppc_vsx_xvtsqrtdp v2f64:$A)),
2684 (COPY_TO_REGCLASS (XVTSQRTDP $A), GPRC)>;
2685 def : Pat<(i32 (int_ppc_vsx_xvtsqrtsp v4f32:$A)),
2686 (COPY_TO_REGCLASS (XVTSQRTSP $A), GPRC)>;
2688 // Reciprocal estimate
2689 def : Pat<(int_ppc_vsx_xvresp v4f32:$A),
2691 def : Pat<(int_ppc_vsx_xvredp v2f64:$A),
2694 // Recip. square root estimate
2695 def : Pat<(int_ppc_vsx_xvrsqrtesp v4f32:$A),
2697 def : Pat<(int_ppc_vsx_xvrsqrtedp v2f64:$A),
2701 def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)),
2703 (XXSEL (COPY_TO_REGCLASS $vC, VSRC),
2704 (COPY_TO_REGCLASS $vB, VSRC),
2705 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;
2706 def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)),
2708 (XXSEL (COPY_TO_REGCLASS $vC, VSRC),
2709 (COPY_TO_REGCLASS $vB, VSRC),
2710 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;
2711 def : Pat<(vselect v4i32:$vA, v4i32:$vB, v4i32:$vC),
2712 (XXSEL $vC, $vB, $vA)>;
2713 def : Pat<(vselect v2i64:$vA, v2i64:$vB, v2i64:$vC),
2714 (XXSEL $vC, $vB, $vA)>;
2715 def : Pat<(vselect v4i32:$vA, v4f32:$vB, v4f32:$vC),
2716 (XXSEL $vC, $vB, $vA)>;
2717 def : Pat<(vselect v2i64:$vA, v2f64:$vB, v2f64:$vC),
2718 (XXSEL $vC, $vB, $vA)>;
2719 def : Pat<(v1i128 (vselect v1i128:$vA, v1i128:$vB, v1i128:$vC)),
2721 (XXSEL (COPY_TO_REGCLASS $vC, VSRC),
2722 (COPY_TO_REGCLASS $vB, VSRC),
2723 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;
2725 def : Pat<(v4f32 (any_fmaxnum v4f32:$src1, v4f32:$src2)),
2726 (v4f32 (XVMAXSP $src1, $src2))>;
2727 def : Pat<(v4f32 (any_fminnum v4f32:$src1, v4f32:$src2)),
2728 (v4f32 (XVMINSP $src1, $src2))>;
2729 def : Pat<(v2f64 (any_fmaxnum v2f64:$src1, v2f64:$src2)),
2730 (v2f64 (XVMAXDP $src1, $src2))>;
2731 def : Pat<(v2f64 (any_fminnum v2f64:$src1, v2f64:$src2)),
2732 (v2f64 (XVMINDP $src1, $src2))>;
2735 def : Pat<(f32 (fabs f32:$S)),
2736 (f32 (COPY_TO_REGCLASS (XSABSDP
2737 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
2740 def : Pat<(f32 (fneg (fabs f32:$S))),
2741 (f32 (COPY_TO_REGCLASS (XSNABSDP
2742 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
2745 def : Pat<(f32 (fminnum_ieee f32:$A, f32:$B)),
2746 (f32 FpMinMax.F32Min)>;
2747 def : Pat<(f32 (fminnum_ieee (fcanonicalize f32:$A), f32:$B)),
2748 (f32 FpMinMax.F32Min)>;
2749 def : Pat<(f32 (fminnum_ieee f32:$A, (fcanonicalize f32:$B))),
2750 (f32 FpMinMax.F32Min)>;
2751 def : Pat<(f32 (fminnum_ieee (fcanonicalize f32:$A), (fcanonicalize f32:$B))),
2752 (f32 FpMinMax.F32Min)>;
2754 def : Pat<(f32 (fmaxnum_ieee f32:$A, f32:$B)),
2755 (f32 FpMinMax.F32Max)>;
2756 def : Pat<(f32 (fmaxnum_ieee (fcanonicalize f32:$A), f32:$B)),
2757 (f32 FpMinMax.F32Max)>;
2758 def : Pat<(f32 (fmaxnum_ieee f32:$A, (fcanonicalize f32:$B))),
2759 (f32 FpMinMax.F32Max)>;
2760 def : Pat<(f32 (fmaxnum_ieee (fcanonicalize f32:$A), (fcanonicalize f32:$B))),
2761 (f32 FpMinMax.F32Max)>;
2764 def : Pat<(f64 (fminnum_ieee f64:$A, f64:$B)),
2765 (f64 (XSMINDP $A, $B))>;
2766 def : Pat<(f64 (fminnum_ieee (fcanonicalize f64:$A), f64:$B)),
2767 (f64 (XSMINDP $A, $B))>;
2768 def : Pat<(f64 (fminnum_ieee f64:$A, (fcanonicalize f64:$B))),
2769 (f64 (XSMINDP $A, $B))>;
2770 def : Pat<(f64 (fminnum_ieee (fcanonicalize f64:$A), (fcanonicalize f64:$B))),
2771 (f64 (XSMINDP $A, $B))>;
2773 def : Pat<(f64 (fmaxnum_ieee f64:$A, f64:$B)),
2774 (f64 (XSMAXDP $A, $B))>;
2775 def : Pat<(f64 (fmaxnum_ieee (fcanonicalize f64:$A), f64:$B)),
2776 (f64 (XSMAXDP $A, $B))>;
2777 def : Pat<(f64 (fmaxnum_ieee f64:$A, (fcanonicalize f64:$B))),
2778 (f64 (XSMAXDP $A, $B))>;
2779 def : Pat<(f64 (fmaxnum_ieee (fcanonicalize f64:$A), (fcanonicalize f64:$B))),
2780 (f64 (XSMAXDP $A, $B))>;
2782 def : Pat<(int_ppc_vsx_stxvd2x_be v2f64:$rS, ForceXForm:$dst),
2783 (STXVD2X $rS, ForceXForm:$dst)>;
2784 def : Pat<(int_ppc_vsx_stxvw4x_be v4i32:$rS, ForceXForm:$dst),
2785 (STXVW4X $rS, ForceXForm:$dst)>;
2786 def : Pat<(v4i32 (int_ppc_vsx_lxvw4x_be ForceXForm:$src)), (LXVW4X ForceXForm:$src)>;
2787 def : Pat<(v2f64 (int_ppc_vsx_lxvd2x_be ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;
2789 // Rounding for single precision.
2790 def : Pat<(f32 (any_fround f32:$S)),
2791 (f32 (COPY_TO_REGCLASS (XSRDPI
2792 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
2793 def : Pat<(f32 (any_ffloor f32:$S)),
2794 (f32 (COPY_TO_REGCLASS (XSRDPIM
2795 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
2796 def : Pat<(f32 (any_fceil f32:$S)),
2797 (f32 (COPY_TO_REGCLASS (XSRDPIP
2798 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
2799 def : Pat<(f32 (any_ftrunc f32:$S)),
2800 (f32 (COPY_TO_REGCLASS (XSRDPIZ
2801 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
2802 def : Pat<(f32 (any_frint f32:$S)),
2803 (f32 (COPY_TO_REGCLASS (XSRDPIC
2804 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
2805 def : Pat<(v4f32 (any_frint v4f32:$S)), (v4f32 (XVRSPIC $S))>;
2807 // Rounding for double precision.
2808 def : Pat<(f64 (any_frint f64:$S)), (f64 (XSRDPIC $S))>;
2809 def : Pat<(v2f64 (any_frint v2f64:$S)), (v2f64 (XVRDPIC $S))>;
2811 // Rounding without exceptions (nearbyint). Due to strange tblgen behaviour,
2812 // these need to be defined after the any_frint versions so ISEL will correctly
2813 // add the chain to the strict versions.
2814 def : Pat<(f32 (fnearbyint f32:$S)),
2815 (f32 (COPY_TO_REGCLASS (XSRDPIC
2816 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
2817 def : Pat<(f64 (fnearbyint f64:$S)),
2818 (f64 (XSRDPIC $S))>;
2819 def : Pat<(v2f64 (fnearbyint v2f64:$S)),
2820 (v2f64 (XVRDPIC $S))>;
2821 def : Pat<(v4f32 (fnearbyint v4f32:$S)),
2822 (v4f32 (XVRSPIC $S))>;
2824 // Materialize a zero-vector of long long
2825 def : Pat<(v2i64 immAllZerosV),
2828 // Build vectors of floating point converted to i32.
2829 def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.A,
2830 DblToInt.A, DblToInt.A)),
2831 (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS $A), sub_64), 1))>;
2832 def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.A,
2833 DblToUInt.A, DblToUInt.A)),
2834 (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS $A), sub_64), 1))>;
2835 def : Pat<(v2i64 (build_vector DblToLong.A, DblToLong.A)),
2836 (v2i64 (XXPERMDI (SUBREG_TO_REG (i64 1), (XSCVDPSXDS $A), sub_64),
2837 (SUBREG_TO_REG (i64 1), (XSCVDPSXDS $A), sub_64), 0))>;
2838 def : Pat<(v2i64 (build_vector DblToULong.A, DblToULong.A)),
2839 (v2i64 (XXPERMDI (SUBREG_TO_REG (i64 1), (XSCVDPUXDS $A), sub_64),
2840 (SUBREG_TO_REG (i64 1), (XSCVDPUXDS $A), sub_64), 0))>;
2841 def : Pat<(v4i32 (PPCSToV DblToInt.A)),
2842 (v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS f64:$A), sub_64))>;
2843 def : Pat<(v4i32 (PPCSToV DblToUInt.A)),
2844 (v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPUXWS f64:$A), sub_64))>;
2845 defm : ScalToVecWPermute<
2846 v4i32, FltToIntLoad.A,
2847 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1),
2848 (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>;
2849 defm : ScalToVecWPermute<
2850 v4i32, FltToUIntLoad.A,
2851 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1),
2852 (SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>;
2853 def : Pat<(v4f32 (build_vector (f32 (fpround f64:$A)), (f32 (fpround f64:$A)),
2854 (f32 (fpround f64:$A)), (f32 (fpround f64:$A)))),
2855 (v4f32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$A), sub_64), 0))>;
2857 def : Pat<(v4f32 (build_vector f32:$A, f32:$A, f32:$A, f32:$A)),
2858 (v4f32 (XXSPLTW (v4f32 (XSCVDPSPN $A)), 0))>;
2861 def : Pat<(v2f64 (PPCldsplat ForceXForm:$A)),
2862 (v2f64 (LXVDSX ForceXForm:$A))>;
2863 def : Pat<(v4f32 (PPCldsplat ForceXForm:$A)),
2864 (v4f32 (XXSPLTW (SUBREG_TO_REG (i64 1), (LFIWZX ForceXForm:$A), sub_64), 1))>;
2865 def : Pat<(v2i64 (PPCldsplat ForceXForm:$A)),
2866 (v2i64 (LXVDSX ForceXForm:$A))>;
2867 def : Pat<(v4i32 (PPCldsplat ForceXForm:$A)),
2868 (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (LFIWZX ForceXForm:$A), sub_64), 1))>;
2869 def : Pat<(v2i64 (PPCzextldsplat ForceXForm:$A)),
2870 (v2i64 (XXPERMDIs (LFIWZX ForceXForm:$A), 0))>;
2871 def : Pat<(v2i64 (PPCsextldsplat ForceXForm:$A)),
2872 (v2i64 (XXPERMDIs (LFIWAX ForceXForm:$A), 0))>;
2874 // Build vectors of floating point converted to i64.
2875 def : Pat<(v2i64 (build_vector FltToLong.A, FltToLong.A)),
2877 (COPY_TO_REGCLASS (XSCVDPSXDSs $A), VSFRC), 0))>;
2878 def : Pat<(v2i64 (build_vector FltToULong.A, FltToULong.A)),
2880 (COPY_TO_REGCLASS (XSCVDPUXDSs $A), VSFRC), 0))>;
2881 defm : ScalToVecWPermute<
2882 v2i64, DblToLongLoad.A,
2883 (XVCVDPSXDS (LXVDSX ForceXForm:$A)), (XVCVDPSXDS (LXVDSX ForceXForm:$A))>;
2884 defm : ScalToVecWPermute<
2885 v2i64, DblToULongLoad.A,
2886 (XVCVDPUXDS (LXVDSX ForceXForm:$A)), (XVCVDPUXDS (LXVDSX ForceXForm:$A))>;
2888 // Doubleword vector predicate comparisons without Power8.
2889 let AddedComplexity = 0 in {
2890 def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 967)),
2891 (VCMPGTUB_rec DblwdCmp.MRGSGT, (v2i64 (XXLXORz)))>;
2892 def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 711)),
2893 (VCMPGTUB_rec DblwdCmp.MRGUGT, (v2i64 (XXLXORz)))>;
2894 def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 199)),
2895 (VCMPGTUB_rec DblwdCmp.MRGEQ, (v2i64 (XXLXORz)))>;
2896 } // AddedComplexity = 0
2898 // XL Compat builtins.
2899 def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (XSMSUBMDP $A, $B, $C)>;
2900 def : Pat<(int_ppc_fnmsub f64:$A, f64:$B, f64:$C), (XSNMSUBMDP $A, $B, $C)>;
2901 def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (XSNMADDMDP $A, $B, $C)>;
2902 def : Pat<(int_ppc_fre f64:$A), (XSREDP $A)>;
2903 def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
2906 // Any big endian VSX subtarget.
2907 let Predicates = [HasVSX, IsBigEndian] in {
2908 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
2909 (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;
2911 def : Pat<(f64 (extractelt v2f64:$S, 0)),
2912 (f64 (EXTRACT_SUBREG $S, sub_64))>;
2913 def : Pat<(f64 (extractelt v2f64:$S, 1)),
2914 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
2915 def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
2916 (f64 (XSCVSXDDP (COPY_TO_REGCLASS $S, VSFRC)))>;
2917 def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
2918 (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
2919 def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
2920 (f64 (XSCVUXDDP (COPY_TO_REGCLASS $S, VSFRC)))>;
2921 def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
2922 (f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
2924 def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)),
2925 (f64 VectorExtractions.BE_VARIABLE_DOUBLE)>;
2927 def : Pat<(v2f64 (build_vector f64:$A, f64:$B)),
2929 (SUBREG_TO_REG (i64 1), $A, sub_64),
2930 (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>;
2931 // Using VMRGEW to assemble the final vector would be a lower latency
2932 // solution. However, we choose to go with the slightly higher latency
2933 // XXPERMDI for 2 reasons:
2934 // 1. This is likely to occur in unrolled loops where regpressure is high,
2935 // so we want to use the latter as it has access to all 64 VSX registers.
2936 // 2. Using Altivec instructions in this sequence would likely cause the
2937 // allocation of Altivec registers even for the loads which in turn would
2938 // force the use of LXSIWZX for the loads, adding a cycle of latency to
2939 // each of the loads which would otherwise be able to use LFIWZX.
2940 def : Pat<(v4f32 (build_vector LoadFP.A, LoadFP.B, LoadFP.C, LoadFP.D)),
2941 (v4f32 (XXPERMDI (XXMRGHW MrgFP.LD32A, MrgFP.LD32B),
2942 (XXMRGHW MrgFP.LD32C, MrgFP.LD32D), 3))>;
2943 def : Pat<(v4f32 (build_vector f32:$A, f32:$B, f32:$C, f32:$D)),
2944 (VMRGEW MrgFP.AC, MrgFP.BD)>;
2945 def : Pat<(v4f32 (build_vector DblToFlt.A0, DblToFlt.A1,
2946 DblToFlt.B0, DblToFlt.B1)),
2947 (v4f32 (VMRGEW MrgFP.ABhToFlt, MrgFP.ABlToFlt))>;
2949 // Convert 4 doubles to a vector of ints.
2950 def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.B,
2951 DblToInt.C, DblToInt.D)),
2952 (v4i32 (VMRGEW MrgWords.CVACS, MrgWords.CVBDS))>;
2953 def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.B,
2954 DblToUInt.C, DblToUInt.D)),
2955 (v4i32 (VMRGEW MrgWords.CVACU, MrgWords.CVBDU))>;
2956 def : Pat<(v4i32 (build_vector ExtDbl.A0S, ExtDbl.A1S,
2957 ExtDbl.B0S, ExtDbl.B1S)),
2958 (v4i32 (VMRGEW MrgWords.CVA0B0S, MrgWords.CVA1B1S))>;
2959 def : Pat<(v4i32 (build_vector ExtDbl.A0U, ExtDbl.A1U,
2960 ExtDbl.B0U, ExtDbl.B1U)),
2961 (v4i32 (VMRGEW MrgWords.CVA0B0U, MrgWords.CVA1B1U))>;
2962 def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),
2963 (f64 (fpextend (extractelt v4f32:$A, 1))))),
2964 (v2f64 (XVCVSPDP (XXMRGHW $A, $A)))>;
2965 def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),
2966 (f64 (fpextend (extractelt v4f32:$A, 0))))),
2967 (v2f64 (XXPERMDI (XVCVSPDP (XXMRGHW $A, $A)),
2968 (XVCVSPDP (XXMRGHW $A, $A)), 2))>;
2969 def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),
2970 (f64 (fpextend (extractelt v4f32:$A, 2))))),
2971 (v2f64 (XVCVSPDP $A))>;
2972 def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),
2973 (f64 (fpextend (extractelt v4f32:$A, 3))))),
2974 (v2f64 (XVCVSPDP (XXSLDWI $A, $A, 3)))>;
2975 def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 2))),
2976 (f64 (fpextend (extractelt v4f32:$A, 3))))),
2977 (v2f64 (XVCVSPDP (XXMRGLW $A, $A)))>;
2978 def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))),
2979 (f64 (fpextend (extractelt v4f32:$A, 2))))),
2980 (v2f64 (XXPERMDI (XVCVSPDP (XXMRGLW $A, $A)),
2981 (XVCVSPDP (XXMRGLW $A, $A)), 2))>;
2982 def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),
2983 (f64 (fpextend (extractelt v4f32:$B, 0))))),
2984 (v2f64 (XVCVSPDP (XXPERMDI $A, $B, 0)))>;
2985 def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))),
2986 (f64 (fpextend (extractelt v4f32:$B, 3))))),
2987 (v2f64 (XVCVSPDP (XXSLDWI (XXPERMDI $A, $B, 3),
2988 (XXPERMDI $A, $B, 3), 1)))>;
2989 def : Pat<(v2i64 (fp_to_sint
2990 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),
2991 (f64 (fpextend (extractelt v4f32:$A, 2)))))),
2992 (v2i64 (XVCVSPSXDS $A))>;
2993 def : Pat<(v2i64 (fp_to_uint
2994 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),
2995 (f64 (fpextend (extractelt v4f32:$A, 2)))))),
2996 (v2i64 (XVCVSPUXDS $A))>;
2997 def : Pat<(v2i64 (fp_to_sint
2998 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),
2999 (f64 (fpextend (extractelt v4f32:$A, 3)))))),
3000 (v2i64 (XVCVSPSXDS (XXSLDWI $A, $A, 1)))>;
3001 def : Pat<(v2i64 (fp_to_uint
3002 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),
3003 (f64 (fpextend (extractelt v4f32:$A, 3)))))),
3004 (v2i64 (XVCVSPUXDS (XXSLDWI $A, $A, 1)))>;
3005 def : Pat<WToDPExtractConv.BV02S,
3006 (v2f64 (XVCVSXWDP $A))>;
3007 def : Pat<WToDPExtractConv.BV13S,
3008 (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 1)))>;
3009 def : Pat<WToDPExtractConv.BV02U,
3010 (v2f64 (XVCVUXWDP $A))>;
3011 def : Pat<WToDPExtractConv.BV13U,
3012 (v2f64 (XVCVUXWDP (XXSLDWI $A, $A, 1)))>;
3013 def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 0)),
3014 (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), $A, 1))>;
3015 def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 1)),
3016 (v2f64 (XXPERMDI $A, (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>;
3017 } // HasVSX, IsBigEndian
3019 // Any little endian VSX subtarget.
3020 let Predicates = [HasVSX, IsLittleEndian] in {
3021 defm : ScalToVecWPermute<v2f64, (f64 f64:$A),
3022 (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64),
3023 (SUBREG_TO_REG (i64 1), $A, sub_64), 0),
3024 (SUBREG_TO_REG (i64 1), $A, sub_64)>;
3026 def : Pat<(f64 (extractelt (v2f64 (bitconvert (v16i8
3027 (PPCvperm v16i8:$A, v16i8:$B, v16i8:$C)))), 0)),
3028 (f64 (EXTRACT_SUBREG (VPERM $B, $A, $C), sub_64))>;
3029 def : Pat<(f64 (extractelt v2f64:$S, 0)),
3030 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
3031 def : Pat<(f64 (extractelt v2f64:$S, 1)),
3032 (f64 (EXTRACT_SUBREG $S, sub_64))>;
3034 def : Pat<(v2f64 (PPCld_vec_be ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;
3035 def : Pat<(PPCst_vec_be v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>;
3036 def : Pat<(v4f32 (PPCld_vec_be ForceXForm:$src)), (LXVW4X ForceXForm:$src)>;
3037 def : Pat<(PPCst_vec_be v4f32:$rS, ForceXForm:$dst), (STXVW4X $rS, ForceXForm:$dst)>;
3038 def : Pat<(v2i64 (PPCld_vec_be ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;
3039 def : Pat<(PPCst_vec_be v2i64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>;
3040 def : Pat<(v4i32 (PPCld_vec_be ForceXForm:$src)), (LXVW4X ForceXForm:$src)>;
3041 def : Pat<(PPCst_vec_be v4i32:$rS, ForceXForm:$dst), (STXVW4X $rS, ForceXForm:$dst)>;
3042 def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
3043 (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
3044 def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
3045 (f64 (XSCVSXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>;
3046 def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
3047 (f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
3048 def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
3049 (f64 (XSCVUXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>;
3051 def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)),
3052 (f64 VectorExtractions.LE_VARIABLE_DOUBLE)>;
3054 // Little endian, available on all targets with VSX
3055 def : Pat<(v2f64 (build_vector f64:$A, f64:$B)),
3057 (SUBREG_TO_REG (i64 1), $B, sub_64),
3058 (SUBREG_TO_REG (i64 1), $A, sub_64), 0))>;
3059 // Using VMRGEW to assemble the final vector would be a lower latency
3060 // solution. However, we choose to go with the slightly higher latency
3061 // XXPERMDI for 2 reasons:
3062 // 1. This is likely to occur in unrolled loops where regpressure is high,
3063 // so we want to use the latter as it has access to all 64 VSX registers.
3064 // 2. Using Altivec instructions in this sequence would likely cause the
3065 // allocation of Altivec registers even for the loads which in turn would
3066 // force the use of LXSIWZX for the loads, adding a cycle of latency to
3067 // each of the loads which would otherwise be able to use LFIWZX.
3068 def : Pat<(v4f32 (build_vector LoadFP.A, LoadFP.B, LoadFP.C, LoadFP.D)),
3069 (v4f32 (XXPERMDI (XXMRGHW MrgFP.LD32D, MrgFP.LD32C),
3070 (XXMRGHW MrgFP.LD32B, MrgFP.LD32A), 3))>;
3071 def : Pat<(v4f32 (build_vector f32:$D, f32:$C, f32:$B, f32:$A)),
3072 (VMRGEW MrgFP.AC, MrgFP.BD)>;
3073 def : Pat<(v4f32 (build_vector DblToFlt.A0, DblToFlt.A1,
3074 DblToFlt.B0, DblToFlt.B1)),
3075 (v4f32 (VMRGEW MrgFP.BAhToFlt, MrgFP.BAlToFlt))>;
3077 // Convert 4 doubles to a vector of ints.
3078 def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.B,
3079 DblToInt.C, DblToInt.D)),
3080 (v4i32 (VMRGEW MrgWords.CVDBS, MrgWords.CVCAS))>;
3081 def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.B,
3082 DblToUInt.C, DblToUInt.D)),
3083 (v4i32 (VMRGEW MrgWords.CVDBU, MrgWords.CVCAU))>;
3084 def : Pat<(v4i32 (build_vector ExtDbl.A0S, ExtDbl.A1S,
3085 ExtDbl.B0S, ExtDbl.B1S)),
3086 (v4i32 (VMRGEW MrgWords.CVB1A1S, MrgWords.CVB0A0S))>;
3087 def : Pat<(v4i32 (build_vector ExtDbl.A0U, ExtDbl.A1U,
3088 ExtDbl.B0U, ExtDbl.B1U)),
3089 (v4i32 (VMRGEW MrgWords.CVB1A1U, MrgWords.CVB0A0U))>;
3090 def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),
3091 (f64 (fpextend (extractelt v4f32:$A, 1))))),
3092 (v2f64 (XVCVSPDP (XXMRGLW $A, $A)))>;
3093 def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),
3094 (f64 (fpextend (extractelt v4f32:$A, 0))))),
3095 (v2f64 (XXPERMDI (XVCVSPDP (XXMRGLW $A, $A)),
3096 (XVCVSPDP (XXMRGLW $A, $A)), 2))>;
3097 def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),
3098 (f64 (fpextend (extractelt v4f32:$A, 2))))),
3099 (v2f64 (XVCVSPDP (XXSLDWI $A, $A, 1)))>;
3100 def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),
3101 (f64 (fpextend (extractelt v4f32:$A, 3))))),
3102 (v2f64 (XVCVSPDP $A))>;
3103 def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 2))),
3104 (f64 (fpextend (extractelt v4f32:$A, 3))))),
3105 (v2f64 (XVCVSPDP (XXMRGHW $A, $A)))>;
3106 def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))),
3107 (f64 (fpextend (extractelt v4f32:$A, 2))))),
3108 (v2f64 (XXPERMDI (XVCVSPDP (XXMRGHW $A, $A)),
3109 (XVCVSPDP (XXMRGHW $A, $A)), 2))>;
3110 def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),
3111 (f64 (fpextend (extractelt v4f32:$B, 0))))),
3112 (v2f64 (XVCVSPDP (XXSLDWI (XXPERMDI $B, $A, 3),
3113 (XXPERMDI $B, $A, 3), 1)))>;
3114 def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))),
3115 (f64 (fpextend (extractelt v4f32:$B, 3))))),
3116 (v2f64 (XVCVSPDP (XXPERMDI $B, $A, 0)))>;
3117 def : Pat<(v2i64 (fp_to_sint
3118 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),
3119 (f64 (fpextend (extractelt v4f32:$A, 3)))))),
3120 (v2i64 (XVCVSPSXDS $A))>;
3121 def : Pat<(v2i64 (fp_to_uint
3122 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),
3123 (f64 (fpextend (extractelt v4f32:$A, 3)))))),
3124 (v2i64 (XVCVSPUXDS $A))>;
3125 def : Pat<(v2i64 (fp_to_sint
3126 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),
3127 (f64 (fpextend (extractelt v4f32:$A, 2)))))),
3128 (v2i64 (XVCVSPSXDS (XXSLDWI $A, $A, 1)))>;
3129 def : Pat<(v2i64 (fp_to_uint
3130 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),
3131 (f64 (fpextend (extractelt v4f32:$A, 2)))))),
3132 (v2i64 (XVCVSPUXDS (XXSLDWI $A, $A, 1)))>;
3133 def : Pat<WToDPExtractConv.BV02S,
3134 (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 1)))>;
3135 def : Pat<WToDPExtractConv.BV13S,
3136 (v2f64 (XVCVSXWDP $A))>;
3137 def : Pat<WToDPExtractConv.BV02U,
3138 (v2f64 (XVCVUXWDP (XXSLDWI $A, $A, 1)))>;
3139 def : Pat<WToDPExtractConv.BV13U,
3140 (v2f64 (XVCVUXWDP $A))>;
3141 def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 0)),
3142 (v2f64 (XXPERMDI $A, (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>;
3143 def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 1)),
3144 (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), $A, 1))>;
3145 } // HasVSX, IsLittleEndian
3147 // Any pre-Power9 VSX subtarget.
3148 let Predicates = [HasVSX, NoP9Vector] in {
3149 def : Pat<(PPCstore_scal_int_from_vsr
3150 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), ForceXForm:$dst, 8),
3151 (STXSDX (XSCVDPSXDS f64:$src), ForceXForm:$dst)>;
3152 def : Pat<(PPCstore_scal_int_from_vsr
3153 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), ForceXForm:$dst, 8),
3154 (STXSDX (XSCVDPUXDS f64:$src), ForceXForm:$dst)>;
3156 // Load-and-splat with fp-to-int conversion (using X-Form VSX/FP loads).
3157 defm : ScalToVecWPermute<
3158 v4i32, DblToIntLoad.A,
3159 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1),
3160 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64)>;
3161 defm : ScalToVecWPermute<
3162 v4i32, DblToUIntLoad.A,
3163 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1),
3164 (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64)>;
3165 defm : ScalToVecWPermute<
3166 v2i64, FltToLongLoad.A,
3167 (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), 0),
3168 (SUBREG_TO_REG (i64 1), (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A),
3170 defm : ScalToVecWPermute<
3171 v2i64, FltToULongLoad.A,
3172 (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), 0),
3173 (SUBREG_TO_REG (i64 1), (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A),
3175 } // HasVSX, NoP9Vector
3177 // Any little endian pre-Power9 VSX subtarget.
3178 let Predicates = [HasVSX, NoP9Vector, IsLittleEndian] in {
3179 // Load-and-splat using only X-Form VSX loads.
3180 defm : ScalToVecWPermute<
3181 v2i64, (i64 (load ForceXForm:$src)),
3182 (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2),
3183 (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>;
3184 defm : ScalToVecWPermute<
3185 v2f64, (f64 (load ForceXForm:$src)),
3186 (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2),
3187 (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>;
3190 def : Pat<(v8i16 (PPCldsplatAlign16 ForceXForm:$A)),
3191 (v8i16 (VSPLTH 7, (LVX ForceXForm:$A)))>;
3192 def : Pat<(v16i8 (PPCldsplatAlign16 ForceXForm:$A)),
3193 (v16i8 (VSPLTB 15, (LVX ForceXForm:$A)))>;
3194 } // HasVSX, NoP9Vector, IsLittleEndian
3196 let Predicates = [HasVSX, NoP9Vector, IsBigEndian] in {
3197 def : Pat<(v2f64 (int_ppc_vsx_lxvd2x ForceXForm:$src)),
3198 (LXVD2X ForceXForm:$src)>;
3199 def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, ForceXForm:$dst),
3200 (STXVD2X $rS, ForceXForm:$dst)>;
3203 def : Pat<(v8i16 (PPCldsplatAlign16 ForceXForm:$A)),
3204 (v8i16 (VSPLTH 0, (LVX ForceXForm:$A)))>;
3205 def : Pat<(v16i8 (PPCldsplatAlign16 ForceXForm:$A)),
3206 (v16i8 (VSPLTB 0, (LVX ForceXForm:$A)))>;
3207 } // HasVSX, NoP9Vector, IsBigEndian
3209 // Any VSX subtarget that only has loads and stores that load in big endian
3210 // order regardless of endianness. This is really pre-Power9 subtargets.
3211 let Predicates = [HasVSX, HasOnlySwappingMemOps] in {
3212 def : Pat<(v2f64 (PPClxvd2x ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;
3215 def : Pat<(PPCstxvd2x v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>;
3216 } // HasVSX, HasOnlySwappingMemOps
3218 // Big endian VSX subtarget that only has loads and stores that always
3219 // load in big endian order. Really big endian pre-Power9 subtargets.
3220 let Predicates = [HasVSX, HasOnlySwappingMemOps, IsBigEndian] in {
3221 def : Pat<(v2f64 (load ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;
3222 def : Pat<(v2i64 (load ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;
3223 def : Pat<(v4i32 (load ForceXForm:$src)), (LXVW4X ForceXForm:$src)>;
3224 def : Pat<(v4i32 (int_ppc_vsx_lxvw4x ForceXForm:$src)), (LXVW4X ForceXForm:$src)>;
3225 def : Pat<(store v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>;
3226 def : Pat<(store v2i64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>;
3227 def : Pat<(store v4i32:$XT, ForceXForm:$dst), (STXVW4X $XT, ForceXForm:$dst)>;
3228 def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, ForceXForm:$dst),
3229 (STXVW4X $rS, ForceXForm:$dst)>;
3230 def : Pat<(v2i64 (scalar_to_vector (i64 (load ForceXForm:$src)))),
3231 (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>;
3232 } // HasVSX, HasOnlySwappingMemOps, IsBigEndian
3234 // Any Power8 VSX subtarget.
3235 let Predicates = [HasVSX, HasP8Vector] in {
3236 def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B),
3238 def : Pat<(f64 (extloadf32 XForm:$src)),
3239 (COPY_TO_REGCLASS (XFLOADf32 XForm:$src), VSFRC)>;
3240 def : Pat<(f32 (fpround (f64 (extloadf32 ForceXForm:$src)))),
3241 (f32 (XFLOADf32 ForceXForm:$src))>;
3242 def : Pat<(f64 (any_fpextend f32:$src)),
3243 (COPY_TO_REGCLASS $src, VSFRC)>;
3245 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3246 (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3247 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
3248 (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3249 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3250 (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>;
3251 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
3252 (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>;
3253 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3254 (SELECT_VSSRC (CREQV $lhs, $rhs), $tval, $fval)>;
3255 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3256 (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>;
3257 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
3258 (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>;
3259 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3260 (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3261 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
3262 (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3263 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3264 (SELECT_VSSRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3266 // Additional fnmsub pattern for PPC specific ISD opcode
3267 def : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C),
3268 (XSNMSUBASP $C, $A, $B)>;
3269 def : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)),
3270 (XSMSUBASP $C, $A, $B)>;
3271 def : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)),
3272 (XSNMADDASP $C, $A, $B)>;
3275 // Although XSNEGDP is available in P7, we want to select it starting from P8,
3276 // so that FNMSUBS can be selected for fneg-fmsub pattern on P7. (VSX version,
3277 // XSNMSUBASP, is available since P8)
3278 def : Pat<(f32 (fneg f32:$S)),
3279 (f32 (COPY_TO_REGCLASS (XSNEGDP
3280 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
3282 // Instructions for converting float to i32 feeding a store.
3283 def : Pat<(PPCstore_scal_int_from_vsr
3284 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), ForceXForm:$dst, 4),
3285 (STIWX (XSCVDPSXWS f64:$src), ForceXForm:$dst)>;
3286 def : Pat<(PPCstore_scal_int_from_vsr
3287 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), ForceXForm:$dst, 4),
3288 (STIWX (XSCVDPUXWS f64:$src), ForceXForm:$dst)>;
3290 def : Pat<(v2i64 (smax v2i64:$src1, v2i64:$src2)),
3291 (v2i64 (VMAXSD (COPY_TO_REGCLASS $src1, VRRC),
3292 (COPY_TO_REGCLASS $src2, VRRC)))>;
3293 def : Pat<(v2i64 (umax v2i64:$src1, v2i64:$src2)),
3294 (v2i64 (VMAXUD (COPY_TO_REGCLASS $src1, VRRC),
3295 (COPY_TO_REGCLASS $src2, VRRC)))>;
3296 def : Pat<(v2i64 (smin v2i64:$src1, v2i64:$src2)),
3297 (v2i64 (VMINSD (COPY_TO_REGCLASS $src1, VRRC),
3298 (COPY_TO_REGCLASS $src2, VRRC)))>;
3299 def : Pat<(v2i64 (umin v2i64:$src1, v2i64:$src2)),
3300 (v2i64 (VMINUD (COPY_TO_REGCLASS $src1, VRRC),
3301 (COPY_TO_REGCLASS $src2, VRRC)))>;
3303 def : Pat<(v1i128 (bitconvert (v16i8 immAllOnesV))),
3304 (v1i128 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
3305 def : Pat<(v2i64 (bitconvert (v16i8 immAllOnesV))),
3306 (v2i64 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
3307 def : Pat<(v8i16 (bitconvert (v16i8 immAllOnesV))),
3308 (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
3309 def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))),
3310 (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
3312 // XL Compat builtins.
3313 def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (XSMSUBMSP $A, $B, $C)>;
3314 def : Pat<(int_ppc_fnmsubs f32:$A, f32:$B, f32:$C), (XSNMSUBMSP $A, $B, $C)>;
3315 def : Pat<(int_ppc_fnmadds f32:$A, f32:$B, f32:$C), (XSNMADDMSP $A, $B, $C)>;
3316 def : Pat<(int_ppc_fres f32:$A), (XSRESP $A)>;
3317 def : Pat<(i32 (int_ppc_extract_exp f64:$A)),
3318 (EXTRACT_SUBREG (XSXEXPDP (COPY_TO_REGCLASS $A, VSFRC)), sub_32)>;
3319 def : Pat<(int_ppc_extract_sig f64:$A),
3320 (XSXSIGDP (COPY_TO_REGCLASS $A, VSFRC))>;
3321 def : Pat<(f64 (int_ppc_insert_exp f64:$A, i64:$B)),
3322 (COPY_TO_REGCLASS (XSIEXPDP (COPY_TO_REGCLASS $A, G8RC), $B), F8RC)>;
3324 def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT),
3325 (STXSIWX f64:$XT, ForceXForm:$dst)>;
3326 def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;
3327 } // HasVSX, HasP8Vector
3329 // Any big endian Power8 VSX subtarget.
3330 let Predicates = [HasVSX, HasP8Vector, IsBigEndian] in {
3331 def : Pat<DWToSPExtractConv.El0SS1,
3332 (f32 (XSCVSXDSP (COPY_TO_REGCLASS $S1, VSFRC)))>;
3333 def : Pat<DWToSPExtractConv.El1SS1,
3334 (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>;
3335 def : Pat<DWToSPExtractConv.El0US1,
3336 (f32 (XSCVUXDSP (COPY_TO_REGCLASS $S1, VSFRC)))>;
3337 def : Pat<DWToSPExtractConv.El1US1,
3338 (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>;
3340 // v4f32 scalar <-> vector conversions (BE)
3341 defm : ScalToVecWPermute<v4f32, (f32 f32:$A), (XSCVDPSPN $A), (XSCVDPSPN $A)>;
3342 def : Pat<(f32 (vector_extract v4f32:$S, 0)),
3343 (f32 (XSCVSPDPN $S))>;
3344 def : Pat<(f32 (vector_extract v4f32:$S, 1)),
3345 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>;
3346 def : Pat<(f32 (vector_extract v4f32:$S, 2)),
3347 (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>;
3348 def : Pat<(f32 (vector_extract v4f32:$S, 3)),
3349 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>;
3351 def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),
3352 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 0))))>;
3353 def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),
3354 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 1))))>;
3355 def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),
3356 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 2))))>;
3357 def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
3358 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 3))))>;
3359 def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),
3360 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 0)), VSFRC))>;
3361 def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),
3362 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 1)), VSFRC))>;
3363 def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),
3364 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 2)), VSFRC))>;
3365 def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
3366 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 3)), VSFRC))>;
3368 def : Pat<(f32 (vector_extract v4f32:$S, i32:$Idx)),
3369 (f32 VectorExtractions.BE_32B_VARIABLE_FLOAT)>;
3371 def : Pat<(f64 (vector_extract v2f64:$S, i32:$Idx)),
3372 (f64 VectorExtractions.BE_32B_VARIABLE_DOUBLE)>;
3373 } // HasVSX, HasP8Vector, IsBigEndian
3375 // Big endian Power8 64Bit VSX subtarget.
3376 let Predicates = [HasVSX, HasP8Vector, IsBigEndian, IsPPC64] in {
3377 def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)),
3378 (f32 VectorExtractions.BE_VARIABLE_FLOAT)>;
3380 // LIWAX - This instruction is used for sign extending i32 -> i64.
3381 // LIWZX - This instruction will be emitted for i32, f32, and when
3382 // zero-extending i32 to i64 (zext i32 -> i64).
3383 def : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 ForceXForm:$src)))),
3384 (v2i64 (SUBREG_TO_REG (i64 1), (LIWAX ForceXForm:$src), sub_64))>;
3385 def : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 ForceXForm:$src)))),
3386 (v2i64 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64))>;
3387 defm : ScalToVecWPermute<
3388 v4i32, (i32 (load ForceXForm:$src)),
3389 (XXSLDWIs (LIWZX ForceXForm:$src), 1),
3390 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;
3391 defm : ScalToVecWPermute<
3392 v4f32, (f32 (load ForceXForm:$src)),
3393 (XXSLDWIs (LIWZX ForceXForm:$src), 1),
3394 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;
3396 def : Pat<DWToSPExtractConv.BVU,
3397 (v4f32 (VPKUDUM (XXSLDWI (XVCVUXDSP $S1), (XVCVUXDSP $S1), 3),
3398 (XXSLDWI (XVCVUXDSP $S2), (XVCVUXDSP $S2), 3)))>;
3399 def : Pat<DWToSPExtractConv.BVS,
3400 (v4f32 (VPKUDUM (XXSLDWI (XVCVSXDSP $S1), (XVCVSXDSP $S1), 3),
3401 (XXSLDWI (XVCVSXDSP $S2), (XVCVSXDSP $S2), 3)))>;
3402 def : Pat<(store (i32 (extractelt v4i32:$A, 1)), ForceXForm:$src),
3403 (STIWX (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;
3404 def : Pat<(store (f32 (extractelt v4f32:$A, 1)), ForceXForm:$src),
3405 (STIWX (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;
3407 // Elements in a register on a BE system are in order <0, 1, 2, 3>.
3408 // The store instructions store the second word from the left.
3409 // So to align element zero, we need to modulo-left-shift by 3 words.
3410 // Similar logic applies for elements 2 and 3.
3411 foreach Idx = [ [0,3], [2,1], [3,2] ] in {
3412 def : Pat<(store (i32 (extractelt v4i32:$A, !head(Idx))), ForceXForm:$src),
3413 (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))),
3414 sub_64), ForceXForm:$src)>;
3415 def : Pat<(store (f32 (extractelt v4f32:$A, !head(Idx))), ForceXForm:$src),
3416 (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))),
3417 sub_64), ForceXForm:$src)>;
3419 } // HasVSX, HasP8Vector, IsBigEndian, IsPPC64
3421 // Little endian Power8 VSX subtarget.
3422 let Predicates = [HasVSX, HasP8Vector, IsLittleEndian] in {
3423 def : Pat<DWToSPExtractConv.El0SS1,
3424 (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>;
3425 def : Pat<DWToSPExtractConv.El1SS1,
3426 (f32 (XSCVSXDSP (COPY_TO_REGCLASS
3427 (f64 (COPY_TO_REGCLASS $S1, VSRC)), VSFRC)))>;
3428 def : Pat<DWToSPExtractConv.El0US1,
3429 (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>;
3430 def : Pat<DWToSPExtractConv.El1US1,
3431 (f32 (XSCVUXDSP (COPY_TO_REGCLASS
3432 (f64 (COPY_TO_REGCLASS $S1, VSRC)), VSFRC)))>;
3434 // v4f32 scalar <-> vector conversions (LE)
3435 defm : ScalToVecWPermute<v4f32, (f32 f32:$A),
3436 (XXSLDWI (XSCVDPSPN $A), (XSCVDPSPN $A), 1),
3438 def : Pat<(f32 (vector_extract v4f32:$S, 0)),
3439 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>;
3440 def : Pat<(f32 (vector_extract v4f32:$S, 1)),
3441 (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>;
3442 def : Pat<(f32 (vector_extract v4f32:$S, 2)),
3443 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>;
3444 def : Pat<(f32 (vector_extract v4f32:$S, 3)),
3445 (f32 (XSCVSPDPN $S))>;
3446 def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)),
3447 (f32 VectorExtractions.LE_VARIABLE_FLOAT)>;
3449 def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),
3450 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 3))))>;
3451 def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),
3452 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 2))))>;
3453 def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),
3454 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 1))))>;
3455 def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
3456 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 0))))>;
3457 def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),
3458 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 3)), VSFRC))>;
3459 def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),
3460 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 2)), VSFRC))>;
3461 def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),
3462 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 1)), VSFRC))>;
3463 def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
3464 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 0)), VSFRC))>;
3466 // LIWAX - This instruction is used for sign extending i32 -> i64.
3467 // LIWZX - This instruction will be emitted for i32, f32, and when
3468 // zero-extending i32 to i64 (zext i32 -> i64).
3469 defm : ScalToVecWPermute<
3470 v2i64, (i64 (sextloadi32 ForceXForm:$src)),
3471 (XXPERMDIs (LIWAX ForceXForm:$src), 2),
3472 (SUBREG_TO_REG (i64 1), (LIWAX ForceXForm:$src), sub_64)>;
3474 defm : ScalToVecWPermute<
3475 v2i64, (i64 (zextloadi32 ForceXForm:$src)),
3476 (XXPERMDIs (LIWZX ForceXForm:$src), 2),
3477 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;
3479 defm : ScalToVecWPermute<
3480 v4i32, (i32 (load ForceXForm:$src)),
3481 (XXPERMDIs (LIWZX ForceXForm:$src), 2),
3482 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;
3484 defm : ScalToVecWPermute<
3485 v4f32, (f32 (load ForceXForm:$src)),
3486 (XXPERMDIs (LIWZX ForceXForm:$src), 2),
3487 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;
3489 def : Pat<DWToSPExtractConv.BVU,
3490 (v4f32 (VPKUDUM (XXSLDWI (XVCVUXDSP $S2), (XVCVUXDSP $S2), 3),
3491 (XXSLDWI (XVCVUXDSP $S1), (XVCVUXDSP $S1), 3)))>;
3492 def : Pat<DWToSPExtractConv.BVS,
3493 (v4f32 (VPKUDUM (XXSLDWI (XVCVSXDSP $S2), (XVCVSXDSP $S2), 3),
3494 (XXSLDWI (XVCVSXDSP $S1), (XVCVSXDSP $S1), 3)))>;
3495 def : Pat<(store (i32 (extractelt v4i32:$A, 2)), ForceXForm:$src),
3496 (STIWX (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;
3497 def : Pat<(store (f32 (extractelt v4f32:$A, 2)), ForceXForm:$src),
3498 (STIWX (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;
3500 // Elements in a register on a LE system are in order <3, 2, 1, 0>.
3501 // The store instructions store the second word from the left.
3502 // So to align element 3, we need to modulo-left-shift by 3 words.
3503 // Similar logic applies for elements 0 and 1.
3504 foreach Idx = [ [0,2], [1,1], [3,3] ] in {
3505 def : Pat<(store (i32 (extractelt v4i32:$A, !head(Idx))), ForceXForm:$src),
3506 (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))),
3507 sub_64), ForceXForm:$src)>;
3508 def : Pat<(store (f32 (extractelt v4f32:$A, !head(Idx))), ForceXForm:$src),
3509 (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))),
3510 sub_64), ForceXForm:$src)>;
3512 } // HasVSX, HasP8Vector, IsLittleEndian
3514 // Big endian pre-Power9 VSX subtarget.
3515 let Predicates = [HasVSX, HasP8Vector, NoP9Vector, IsBigEndian, IsPPC64] in {
3516 def : Pat<(store (i64 (extractelt v2i64:$A, 0)), ForceXForm:$src),
3517 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;
3518 def : Pat<(store (f64 (extractelt v2f64:$A, 0)), ForceXForm:$src),
3519 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;
3520 def : Pat<(store (i64 (extractelt v2i64:$A, 1)), ForceXForm:$src),
3521 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64),
3523 def : Pat<(store (f64 (extractelt v2f64:$A, 1)), ForceXForm:$src),
3524 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64),
3526 } // HasVSX, HasP8Vector, NoP9Vector, IsBigEndian, IsPPC64
3528 // Little endian pre-Power9 VSX subtarget.
3529 let Predicates = [HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian] in {
3530 def : Pat<(store (i64 (extractelt v2i64:$A, 0)), ForceXForm:$src),
3531 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64),
3533 def : Pat<(store (f64 (extractelt v2f64:$A, 0)), ForceXForm:$src),
3534 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64),
3536 def : Pat<(store (i64 (extractelt v2i64:$A, 1)), ForceXForm:$src),
3537 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;
3538 def : Pat<(store (f64 (extractelt v2f64:$A, 1)), ForceXForm:$src),
3539 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>;
3540 } // HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian
3542 // Any VSX target with direct moves.
3543 let Predicates = [HasVSX, HasDirectMove] in {
3544 // bitconvert f32 -> i32
3545 // (convert to 32-bit fp single, shift right 1 word, move to GPR)
3546 def : Pat<(i32 (bitconvert f32:$A)), Bitcast.FltToInt>;
3548 // bitconvert i32 -> f32
3549 // (move to FPR, shift left 1 word, convert to 64-bit fp single)
3550 def : Pat<(f32 (bitconvert i32:$A)),
3552 (XXSLDWI MovesToVSR.LE_WORD_1, MovesToVSR.LE_WORD_1, 1)))>;
3554 // bitconvert f64 -> i64
3555 // (move to GPR, nothing else needed)
3556 def : Pat<(i64 (bitconvert f64:$A)), Bitcast.DblToLong>;
3558 // bitconvert i64 -> f64
3559 // (move to FPR, nothing else needed)
3560 def : Pat<(f64 (bitconvert i64:$S)),
3563 // Rounding to integer.
3564 def : Pat<(i64 (lrint f64:$S)),
3565 (i64 (MFVSRD (FCTID $S)))>;
3566 def : Pat<(i64 (lrint f32:$S)),
3567 (i64 (MFVSRD (FCTID (COPY_TO_REGCLASS $S, F8RC))))>;
3568 def : Pat<(i64 (llrint f64:$S)),
3569 (i64 (MFVSRD (FCTID $S)))>;
3570 def : Pat<(i64 (llrint f32:$S)),
3571 (i64 (MFVSRD (FCTID (COPY_TO_REGCLASS $S, F8RC))))>;
3572 def : Pat<(i64 (lround f64:$S)),
3573 (i64 (MFVSRD (FCTID (XSRDPI $S))))>;
3574 def : Pat<(i64 (lround f32:$S)),
3575 (i64 (MFVSRD (FCTID (XSRDPI (COPY_TO_REGCLASS $S, VSFRC)))))>;
3576 def : Pat<(i64 (llround f64:$S)),
3577 (i64 (MFVSRD (FCTID (XSRDPI $S))))>;
3578 def : Pat<(i64 (llround f32:$S)),
3579 (i64 (MFVSRD (FCTID (XSRDPI (COPY_TO_REGCLASS $S, VSFRC)))))>;
3581 // Alternate patterns for PPCmtvsrz where the output is v8i16 or v16i8 instead
3583 def : Pat<(v8i16 (PPCmtvsrz i32:$A)),
3584 (v8i16 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64))>;
3585 def : Pat<(v16i8 (PPCmtvsrz i32:$A)),
3586 (v16i8 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64))>;
3588 // Endianness-neutral constant splat on P8 and newer targets. The reason
3589 // for this pattern is that on targets with direct moves, we don't expand
3590 // BUILD_VECTOR nodes for v4i32.
3591 def : Pat<(v4i32 (build_vector immSExt5NonZero:$A, immSExt5NonZero:$A,
3592 immSExt5NonZero:$A, immSExt5NonZero:$A)),
3593 (v4i32 (VSPLTISW imm:$A))>;
3596 def : Pat<(v8i16 (PPCldsplat ForceXForm:$A)),
3597 (v8i16 (VSPLTHs 3, (MTVSRWZ (LHZX ForceXForm:$A))))>;
3598 def : Pat<(v16i8 (PPCldsplat ForceXForm:$A)),
3599 (v16i8 (VSPLTBs 7, (MTVSRWZ (LBZX ForceXForm:$A))))>;
3600 } // HasVSX, HasDirectMove
3602 // Big endian VSX subtarget with direct moves.
3603 let Predicates = [HasVSX, HasDirectMove, IsBigEndian] in {
3604 // v16i8 scalar <-> vector conversions (BE)
3605 defm : ScalToVecWPermute<
3606 v16i8, (i32 i32:$A),
3607 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_BYTE_0, sub_64),
3608 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>;
3609 defm : ScalToVecWPermute<
3610 v8i16, (i32 i32:$A),
3611 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_HALF_0, sub_64),
3612 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>;
3613 defm : ScalToVecWPermute<
3614 v4i32, (i32 i32:$A),
3615 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_WORD_0, sub_64),
3616 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>;
3617 def : Pat<(v2i64 (scalar_to_vector i64:$A)),
3618 (v2i64 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_DWORD_0, sub_64))>;
3620 // v2i64 scalar <-> vector conversions (BE)
3621 def : Pat<(i64 (vector_extract v2i64:$S, 0)),
3622 (i64 VectorExtractions.LE_DWORD_1)>;
3623 def : Pat<(i64 (vector_extract v2i64:$S, 1)),
3624 (i64 VectorExtractions.LE_DWORD_0)>;
3625 def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)),
3626 (i64 VectorExtractions.BE_VARIABLE_DWORD)>;
3627 } // HasVSX, HasDirectMove, IsBigEndian
3629 // Little endian VSX subtarget with direct moves.
3630 let Predicates = [HasVSX, HasDirectMove, IsLittleEndian] in {
3631 // v16i8 scalar <-> vector conversions (LE)
3632 defm : ScalToVecWPermute<v16i8, (i32 i32:$A),
3633 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_0, VSRC),
3634 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_1, VSRC)>;
3635 defm : ScalToVecWPermute<v8i16, (i32 i32:$A),
3636 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_0, VSRC),
3637 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_1, VSRC)>;
3638 defm : ScalToVecWPermute<v4i32, (i32 i32:$A), MovesToVSR.LE_WORD_0,
3639 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>;
3640 defm : ScalToVecWPermute<v2i64, (i64 i64:$A), MovesToVSR.LE_DWORD_0,
3641 MovesToVSR.LE_DWORD_1>;
3643 // v2i64 scalar <-> vector conversions (LE)
3644 def : Pat<(i64 (vector_extract v2i64:$S, 0)),
3645 (i64 VectorExtractions.LE_DWORD_0)>;
3646 def : Pat<(i64 (vector_extract v2i64:$S, 1)),
3647 (i64 VectorExtractions.LE_DWORD_1)>;
3648 def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)),
3649 (i64 VectorExtractions.LE_VARIABLE_DWORD)>;
3650 } // HasVSX, HasDirectMove, IsLittleEndian
3652 // Big endian pre-P9 VSX subtarget with direct moves.
3653 let Predicates = [HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian] in {
3654 def : Pat<(i32 (vector_extract v16i8:$S, 0)),
3655 (i32 VectorExtractions.LE_BYTE_15)>;
3656 def : Pat<(i32 (vector_extract v16i8:$S, 1)),
3657 (i32 VectorExtractions.LE_BYTE_14)>;
3658 def : Pat<(i32 (vector_extract v16i8:$S, 2)),
3659 (i32 VectorExtractions.LE_BYTE_13)>;
3660 def : Pat<(i32 (vector_extract v16i8:$S, 3)),
3661 (i32 VectorExtractions.LE_BYTE_12)>;
3662 def : Pat<(i32 (vector_extract v16i8:$S, 4)),
3663 (i32 VectorExtractions.LE_BYTE_11)>;
3664 def : Pat<(i32 (vector_extract v16i8:$S, 5)),
3665 (i32 VectorExtractions.LE_BYTE_10)>;
3666 def : Pat<(i32 (vector_extract v16i8:$S, 6)),
3667 (i32 VectorExtractions.LE_BYTE_9)>;
3668 def : Pat<(i32 (vector_extract v16i8:$S, 7)),
3669 (i32 VectorExtractions.LE_BYTE_8)>;
3670 def : Pat<(i32 (vector_extract v16i8:$S, 8)),
3671 (i32 VectorExtractions.LE_BYTE_7)>;
3672 def : Pat<(i32 (vector_extract v16i8:$S, 9)),
3673 (i32 VectorExtractions.LE_BYTE_6)>;
3674 def : Pat<(i32 (vector_extract v16i8:$S, 10)),
3675 (i32 VectorExtractions.LE_BYTE_5)>;
3676 def : Pat<(i32 (vector_extract v16i8:$S, 11)),
3677 (i32 VectorExtractions.LE_BYTE_4)>;
3678 def : Pat<(i32 (vector_extract v16i8:$S, 12)),
3679 (i32 VectorExtractions.LE_BYTE_3)>;
3680 def : Pat<(i32 (vector_extract v16i8:$S, 13)),
3681 (i32 VectorExtractions.LE_BYTE_2)>;
3682 def : Pat<(i32 (vector_extract v16i8:$S, 14)),
3683 (i32 VectorExtractions.LE_BYTE_1)>;
3684 def : Pat<(i32 (vector_extract v16i8:$S, 15)),
3685 (i32 VectorExtractions.LE_BYTE_0)>;
3686 def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)),
3687 (i32 VectorExtractions.BE_VARIABLE_BYTE)>;
3689 // v8i16 scalar <-> vector conversions (BE)
3690 def : Pat<(i32 (vector_extract v8i16:$S, 0)),
3691 (i32 VectorExtractions.LE_HALF_7)>;
3692 def : Pat<(i32 (vector_extract v8i16:$S, 1)),
3693 (i32 VectorExtractions.LE_HALF_6)>;
3694 def : Pat<(i32 (vector_extract v8i16:$S, 2)),
3695 (i32 VectorExtractions.LE_HALF_5)>;
3696 def : Pat<(i32 (vector_extract v8i16:$S, 3)),
3697 (i32 VectorExtractions.LE_HALF_4)>;
3698 def : Pat<(i32 (vector_extract v8i16:$S, 4)),
3699 (i32 VectorExtractions.LE_HALF_3)>;
3700 def : Pat<(i32 (vector_extract v8i16:$S, 5)),
3701 (i32 VectorExtractions.LE_HALF_2)>;
3702 def : Pat<(i32 (vector_extract v8i16:$S, 6)),
3703 (i32 VectorExtractions.LE_HALF_1)>;
3704 def : Pat<(i32 (vector_extract v8i16:$S, 7)),
3705 (i32 VectorExtractions.LE_HALF_0)>;
3706 def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)),
3707 (i32 VectorExtractions.BE_VARIABLE_HALF)>;
3709 // v4i32 scalar <-> vector conversions (BE)
3710 def : Pat<(i32 (vector_extract v4i32:$S, 0)),
3711 (i32 VectorExtractions.LE_WORD_3)>;
3712 def : Pat<(i32 (vector_extract v4i32:$S, 1)),
3713 (i32 VectorExtractions.LE_WORD_2)>;
3714 def : Pat<(i32 (vector_extract v4i32:$S, 2)),
3715 (i32 VectorExtractions.LE_WORD_1)>;
3716 def : Pat<(i32 (vector_extract v4i32:$S, 3)),
3717 (i32 VectorExtractions.LE_WORD_0)>;
3718 def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)),
3719 (i32 VectorExtractions.BE_VARIABLE_WORD)>;
3720 } // HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian
3722 // Little endian pre-P9 VSX subtarget with direct moves.
3723 let Predicates = [HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian] in {
3724 def : Pat<(i32 (vector_extract v16i8:$S, 0)),
3725 (i32 VectorExtractions.LE_BYTE_0)>;
3726 def : Pat<(i32 (vector_extract v16i8:$S, 1)),
3727 (i32 VectorExtractions.LE_BYTE_1)>;
3728 def : Pat<(i32 (vector_extract v16i8:$S, 2)),
3729 (i32 VectorExtractions.LE_BYTE_2)>;
3730 def : Pat<(i32 (vector_extract v16i8:$S, 3)),
3731 (i32 VectorExtractions.LE_BYTE_3)>;
3732 def : Pat<(i32 (vector_extract v16i8:$S, 4)),
3733 (i32 VectorExtractions.LE_BYTE_4)>;
3734 def : Pat<(i32 (vector_extract v16i8:$S, 5)),
3735 (i32 VectorExtractions.LE_BYTE_5)>;
3736 def : Pat<(i32 (vector_extract v16i8:$S, 6)),
3737 (i32 VectorExtractions.LE_BYTE_6)>;
3738 def : Pat<(i32 (vector_extract v16i8:$S, 7)),
3739 (i32 VectorExtractions.LE_BYTE_7)>;
3740 def : Pat<(i32 (vector_extract v16i8:$S, 8)),
3741 (i32 VectorExtractions.LE_BYTE_8)>;
3742 def : Pat<(i32 (vector_extract v16i8:$S, 9)),
3743 (i32 VectorExtractions.LE_BYTE_9)>;
3744 def : Pat<(i32 (vector_extract v16i8:$S, 10)),
3745 (i32 VectorExtractions.LE_BYTE_10)>;
3746 def : Pat<(i32 (vector_extract v16i8:$S, 11)),
3747 (i32 VectorExtractions.LE_BYTE_11)>;
3748 def : Pat<(i32 (vector_extract v16i8:$S, 12)),
3749 (i32 VectorExtractions.LE_BYTE_12)>;
3750 def : Pat<(i32 (vector_extract v16i8:$S, 13)),
3751 (i32 VectorExtractions.LE_BYTE_13)>;
3752 def : Pat<(i32 (vector_extract v16i8:$S, 14)),
3753 (i32 VectorExtractions.LE_BYTE_14)>;
3754 def : Pat<(i32 (vector_extract v16i8:$S, 15)),
3755 (i32 VectorExtractions.LE_BYTE_15)>;
3756 def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)),
3757 (i32 VectorExtractions.LE_VARIABLE_BYTE)>;
3759 // v8i16 scalar <-> vector conversions (LE)
3760 def : Pat<(i32 (vector_extract v8i16:$S, 0)),
3761 (i32 VectorExtractions.LE_HALF_0)>;
3762 def : Pat<(i32 (vector_extract v8i16:$S, 1)),
3763 (i32 VectorExtractions.LE_HALF_1)>;
3764 def : Pat<(i32 (vector_extract v8i16:$S, 2)),
3765 (i32 VectorExtractions.LE_HALF_2)>;
3766 def : Pat<(i32 (vector_extract v8i16:$S, 3)),
3767 (i32 VectorExtractions.LE_HALF_3)>;
3768 def : Pat<(i32 (vector_extract v8i16:$S, 4)),
3769 (i32 VectorExtractions.LE_HALF_4)>;
3770 def : Pat<(i32 (vector_extract v8i16:$S, 5)),
3771 (i32 VectorExtractions.LE_HALF_5)>;
3772 def : Pat<(i32 (vector_extract v8i16:$S, 6)),
3773 (i32 VectorExtractions.LE_HALF_6)>;
3774 def : Pat<(i32 (vector_extract v8i16:$S, 7)),
3775 (i32 VectorExtractions.LE_HALF_7)>;
3776 def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)),
3777 (i32 VectorExtractions.LE_VARIABLE_HALF)>;
3779 // v4i32 scalar <-> vector conversions (LE)
3780 def : Pat<(i32 (vector_extract v4i32:$S, 0)),
3781 (i32 VectorExtractions.LE_WORD_0)>;
3782 def : Pat<(i32 (vector_extract v4i32:$S, 1)),
3783 (i32 VectorExtractions.LE_WORD_1)>;
3784 def : Pat<(i32 (vector_extract v4i32:$S, 2)),
3785 (i32 VectorExtractions.LE_WORD_2)>;
3786 def : Pat<(i32 (vector_extract v4i32:$S, 3)),
3787 (i32 VectorExtractions.LE_WORD_3)>;
3788 def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)),
3789 (i32 VectorExtractions.LE_VARIABLE_WORD)>;
3790 } // HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian
3792 // Big endian pre-Power9 64Bit VSX subtarget that has direct moves.
3793 let Predicates = [HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64] in {
3794 // Big endian integer vectors using direct moves.
3795 def : Pat<(v2i64 (build_vector i64:$A, i64:$B)),
3797 (SUBREG_TO_REG (i64 1), (MTVSRD $A), sub_64),
3798 (SUBREG_TO_REG (i64 1), (MTVSRD $B), sub_64), 0))>;
3799 def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
3801 (SUBREG_TO_REG (i64 1),
3802 (MTVSRD (RLDIMI AnyExts.B, AnyExts.A, 32, 0)), sub_64),
3803 (SUBREG_TO_REG (i64 1),
3804 (MTVSRD (RLDIMI AnyExts.D, AnyExts.C, 32, 0)), sub_64), 0)>;
3805 def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
3806 (XXSPLTW (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64), 1)>;
3807 } // HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64
3809 // Little endian pre-Power9 VSX subtarget that has direct moves.
3810 let Predicates = [HasVSX, HasDirectMove, NoP9Vector, IsLittleEndian] in {
3811 // Little endian integer vectors using direct moves.
3812 def : Pat<(v2i64 (build_vector i64:$A, i64:$B)),
3814 (SUBREG_TO_REG (i64 1), (MTVSRD $B), sub_64),
3815 (SUBREG_TO_REG (i64 1), (MTVSRD $A), sub_64), 0))>;
3816 def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
3818 (SUBREG_TO_REG (i64 1),
3819 (MTVSRD (RLDIMI AnyExts.C, AnyExts.D, 32, 0)), sub_64),
3820 (SUBREG_TO_REG (i64 1),
3821 (MTVSRD (RLDIMI AnyExts.A, AnyExts.B, 32, 0)), sub_64), 0)>;
3822 def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
3823 (XXSPLTW (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64), 1)>;
3826 // Any Power9 VSX subtarget.
3827 let Predicates = [HasVSX, HasP9Vector] in {
3828 // Additional fnmsub pattern for PPC specific ISD opcode
3829 def : Pat<(PPCfnmsub f128:$A, f128:$B, f128:$C),
3830 (XSNMSUBQP $C, $A, $B)>;
3831 def : Pat<(fneg (PPCfnmsub f128:$A, f128:$B, f128:$C)),
3832 (XSMSUBQP $C, $A, $B)>;
3833 def : Pat<(PPCfnmsub f128:$A, f128:$B, (fneg f128:$C)),
3834 (XSNMADDQP $C, $A, $B)>;
3836 def : Pat<(f128 (any_sint_to_fp i64:$src)),
3837 (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
3838 def : Pat<(f128 (any_sint_to_fp (i64 (PPCmfvsr f64:$src)))),
3839 (f128 (XSCVSDQP $src))>;
3840 def : Pat<(f128 (any_sint_to_fp (i32 (PPCmfvsr f64:$src)))),
3841 (f128 (XSCVSDQP (VEXTSW2Ds $src)))>;
3842 def : Pat<(f128 (any_uint_to_fp i64:$src)),
3843 (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
3844 def : Pat<(f128 (any_uint_to_fp (i64 (PPCmfvsr f64:$src)))),
3845 (f128 (XSCVUDQP $src))>;
3847 // Convert (Un)Signed Word -> QP.
3848 def : Pat<(f128 (any_sint_to_fp i32:$src)),
3849 (f128 (XSCVSDQP (MTVSRWA $src)))>;
3850 def : Pat<(f128 (any_sint_to_fp (i32 (load ForceXForm:$src)))),
3851 (f128 (XSCVSDQP (LIWAX ForceXForm:$src)))>;
3852 def : Pat<(f128 (any_uint_to_fp i32:$src)),
3853 (f128 (XSCVUDQP (MTVSRWZ $src)))>;
3854 def : Pat<(f128 (any_uint_to_fp (i32 (load ForceXForm:$src)))),
3855 (f128 (XSCVUDQP (LIWZX ForceXForm:$src)))>;
3857 // Pattern for matching Vector HP -> Vector SP intrinsic. Defined as a
3858 // separate pattern so that it can convert the input register class from
3859 // VRRC(v8i16) to VSRC.
3860 def : Pat<(v4f32 (int_ppc_vsx_xvcvhpsp v8i16:$A)),
3861 (v4f32 (XVCVHPSP (COPY_TO_REGCLASS $A, VSRC)))>;
3863 // Use current rounding mode
3864 def : Pat<(f128 (any_fnearbyint f128:$vB)), (f128 (XSRQPI 0, $vB, 3))>;
3865 // Round to nearest, ties away from zero
3866 def : Pat<(f128 (any_fround f128:$vB)), (f128 (XSRQPI 0, $vB, 0))>;
3867 // Round towards Zero
3868 def : Pat<(f128 (any_ftrunc f128:$vB)), (f128 (XSRQPI 1, $vB, 1))>;
3869 // Round towards +Inf
3870 def : Pat<(f128 (any_fceil f128:$vB)), (f128 (XSRQPI 1, $vB, 2))>;
3871 // Round towards -Inf
3872 def : Pat<(f128 (any_ffloor f128:$vB)), (f128 (XSRQPI 1, $vB, 3))>;
3873 // Use current rounding mode, [with Inexact]
3874 def : Pat<(f128 (any_frint f128:$vB)), (f128 (XSRQPIX 0, $vB, 3))>;
3876 def : Pat<(f128 (int_ppc_scalar_insert_exp_qp f128:$vA, i64:$vB)),
3877 (f128 (XSIEXPQP $vA, (MTVSRD $vB)))>;
3879 def : Pat<(i64 (int_ppc_scalar_extract_expq f128:$vA)),
3880 (i64 (MFVSRD (EXTRACT_SUBREG
3881 (v2i64 (XSXEXPQP $vA)), sub_64)))>;
3883 // Extra patterns expanding to vector Extract Word/Insert Word
3884 def : Pat<(v4i32 (int_ppc_vsx_xxinsertw v4i32:$A, v2i64:$B, imm:$IMM)),
3885 (v4i32 (XXINSERTW $A, $B, imm:$IMM))>;
3886 def : Pat<(v2i64 (int_ppc_vsx_xxextractuw v2i64:$A, imm:$IMM)),
3887 (v2i64 (COPY_TO_REGCLASS (XXEXTRACTUW $A, imm:$IMM), VSRC))>;
3890 def : Pat<(v8i16 (bswap v8i16 :$A)),
3891 (v8i16 (COPY_TO_REGCLASS (XXBRH (COPY_TO_REGCLASS $A, VSRC)), VRRC))>;
3892 def : Pat<(v1i128 (bswap v1i128 :$A)),
3893 (v1i128 (COPY_TO_REGCLASS (XXBRQ (COPY_TO_REGCLASS $A, VSRC)), VRRC))>;
3895 // D-Form Load/Store
3896 foreach Ty = [v4i32, v4f32, v2i64, v2f64] in {
3897 def : Pat<(Ty (load DQForm:$src)), (LXV memrix16:$src)>;
3898 def : Pat<(Ty (load XForm:$src)), (LXVX XForm:$src)>;
3899 def : Pat<(store Ty:$rS, DQForm:$dst), (STXV $rS, memrix16:$dst)>;
3900 def : Pat<(store Ty:$rS, XForm:$dst), (STXVX $rS, XForm:$dst)>;
3903 def : Pat<(f128 (load DQForm:$src)),
3904 (COPY_TO_REGCLASS (LXV memrix16:$src), VRRC)>;
3905 def : Pat<(f128 (load XForm:$src)),
3906 (COPY_TO_REGCLASS (LXVX XForm:$src), VRRC)>;
3907 def : Pat<(v4i32 (int_ppc_vsx_lxvw4x DQForm:$src)), (LXV memrix16:$src)>;
3908 def : Pat<(v2f64 (int_ppc_vsx_lxvd2x DQForm:$src)), (LXV memrix16:$src)>;
3909 def : Pat<(v4i32 (int_ppc_vsx_lxvw4x XForm:$src)), (LXVX XForm:$src)>;
3910 def : Pat<(v2f64 (int_ppc_vsx_lxvd2x XForm:$src)), (LXVX XForm:$src)>;
3912 def : Pat<(store f128:$rS, DQForm:$dst),
3913 (STXV (COPY_TO_REGCLASS $rS, VSRC), memrix16:$dst)>;
3914 def : Pat<(store f128:$rS, XForm:$dst),
3915 (STXVX (COPY_TO_REGCLASS $rS, VSRC), XForm:$dst)>;
3916 def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, DQForm:$dst),
3917 (STXV $rS, memrix16:$dst)>;
3918 def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, DQForm:$dst),
3919 (STXV $rS, memrix16:$dst)>;
3920 def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, XForm:$dst),
3921 (STXVX $rS, XForm:$dst)>;
3922 def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, XForm:$dst),
3923 (STXVX $rS, XForm:$dst)>;
3925 // Build vectors from i8 loads
3926 defm : ScalToVecWPermute<v8i16, ScalarLoads.ZELi8,
3927 (VSPLTHs 3, (LXSIBZX ForceXForm:$src)),
3928 (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;
3929 defm : ScalToVecWPermute<v4i32, ScalarLoads.ZELi8,
3930 (XXSPLTWs (LXSIBZX ForceXForm:$src), 1),
3931 (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;
3932 defm : ScalToVecWPermute<v2i64, ScalarLoads.ZELi8i64,
3933 (XXPERMDIs (LXSIBZX ForceXForm:$src), 0),
3934 (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;
3935 defm : ScalToVecWPermute<
3936 v4i32, ScalarLoads.SELi8,
3937 (XXSPLTWs (VEXTSB2Ws (LXSIBZX ForceXForm:$src)), 1),
3938 (SUBREG_TO_REG (i64 1), (VEXTSB2Ws (LXSIBZX ForceXForm:$src)), sub_64)>;
3939 defm : ScalToVecWPermute<
3940 v2i64, ScalarLoads.SELi8i64,
3941 (XXPERMDIs (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), 0),
3942 (SUBREG_TO_REG (i64 1), (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), sub_64)>;
3944 // Build vectors from i16 loads
3945 defm : ScalToVecWPermute<
3946 v4i32, ScalarLoads.ZELi16,
3947 (XXSPLTWs (LXSIHZX ForceXForm:$src), 1),
3948 (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>;
3949 defm : ScalToVecWPermute<
3950 v2i64, ScalarLoads.ZELi16i64,
3951 (XXPERMDIs (LXSIHZX ForceXForm:$src), 0),
3952 (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>;
3953 defm : ScalToVecWPermute<
3954 v4i32, ScalarLoads.SELi16,
3955 (XXSPLTWs (VEXTSH2Ws (LXSIHZX ForceXForm:$src)), 1),
3956 (SUBREG_TO_REG (i64 1), (VEXTSH2Ws (LXSIHZX ForceXForm:$src)), sub_64)>;
3957 defm : ScalToVecWPermute<
3958 v2i64, ScalarLoads.SELi16i64,
3959 (XXPERMDIs (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), 0),
3960 (SUBREG_TO_REG (i64 1), (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64)>;
3962 // Load/convert and convert/store patterns for f16.
3963 def : Pat<(f64 (extloadf16 ForceXForm:$src)),
3964 (f64 (XSCVHPDP (LXSIHZX ForceXForm:$src)))>;
3965 def : Pat<(truncstoref16 f64:$src, ForceXForm:$dst),
3966 (STXSIHX (XSCVDPHP $src), ForceXForm:$dst)>;
3967 def : Pat<(f32 (extloadf16 ForceXForm:$src)),
3968 (f32 (COPY_TO_REGCLASS (XSCVHPDP (LXSIHZX ForceXForm:$src)), VSSRC))>;
3969 def : Pat<(truncstoref16 f32:$src, ForceXForm:$dst),
3970 (STXSIHX (XSCVDPHP (COPY_TO_REGCLASS $src, VSFRC)), ForceXForm:$dst)>;
3971 def : Pat<(f64 (f16_to_fp i32:$A)),
3972 (f64 (XSCVHPDP (MTVSRWZ $A)))>;
3973 def : Pat<(f32 (f16_to_fp i32:$A)),
3974 (f32 (COPY_TO_REGCLASS (XSCVHPDP (MTVSRWZ $A)), VSSRC))>;
3975 def : Pat<(i32 (fp_to_f16 f32:$A)),
3976 (i32 (MFVSRWZ (XSCVDPHP (COPY_TO_REGCLASS $A, VSFRC))))>;
3977 def : Pat<(i32 (fp_to_f16 f64:$A)), (i32 (MFVSRWZ (XSCVDPHP $A)))>;
3979 // Vector sign extensions
3980 def : Pat<(f64 (PPCVexts f64:$A, 1)),
3981 (f64 (COPY_TO_REGCLASS (VEXTSB2Ds $A), VSFRC))>;
3982 def : Pat<(f64 (PPCVexts f64:$A, 2)),
3983 (f64 (COPY_TO_REGCLASS (VEXTSH2Ds $A), VSFRC))>;
3985 def : Pat<(f64 (extloadf32 DSForm:$src)),
3986 (COPY_TO_REGCLASS (DFLOADf32 DSForm:$src), VSFRC)>;
3987 def : Pat<(f32 (fpround (f64 (extloadf32 DSForm:$src)))),
3988 (f32 (DFLOADf32 DSForm:$src))>;
3990 def : Pat<(v4f32 (PPCldvsxlh XForm:$src)),
3991 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>;
3992 def : Pat<(v4f32 (PPCldvsxlh DSForm:$src)),
3993 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>;
3995 // Convert (Un)Signed DWord in memory -> QP
3996 def : Pat<(f128 (sint_to_fp (i64 (load XForm:$src)))),
3997 (f128 (XSCVSDQP (LXSDX XForm:$src)))>;
3998 def : Pat<(f128 (sint_to_fp (i64 (load DSForm:$src)))),
3999 (f128 (XSCVSDQP (LXSD DSForm:$src)))>;
4000 def : Pat<(f128 (uint_to_fp (i64 (load XForm:$src)))),
4001 (f128 (XSCVUDQP (LXSDX XForm:$src)))>;
4002 def : Pat<(f128 (uint_to_fp (i64 (load DSForm:$src)))),
4003 (f128 (XSCVUDQP (LXSD DSForm:$src)))>;
4005 // Convert Unsigned HWord in memory -> QP
4006 def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi16)),
4007 (f128 (XSCVUDQP (LXSIHZX XForm:$src)))>;
4009 // Convert Unsigned Byte in memory -> QP
4010 def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi8)),
4011 (f128 (XSCVUDQP (LXSIBZX ForceXForm:$src)))>;
4013 // Truncate & Convert QP -> (Un)Signed (D)Word.
4014 def : Pat<(i64 (any_fp_to_sint f128:$src)), (i64 (MFVRD (XSCVQPSDZ $src)))>;
4015 def : Pat<(i64 (any_fp_to_uint f128:$src)), (i64 (MFVRD (XSCVQPUDZ $src)))>;
4016 def : Pat<(i32 (any_fp_to_sint f128:$src)),
4017 (i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC)))>;
4018 def : Pat<(i32 (any_fp_to_uint f128:$src)),
4019 (i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC)))>;
4021 // Instructions for store(fptosi).
4022 // The 8-byte version is repeated here due to availability of D-Form STXSD.
4023 def : Pat<(PPCstore_scal_int_from_vsr
4024 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), XForm:$dst, 8),
4025 (STXSDX (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC),
4027 def : Pat<(PPCstore_scal_int_from_vsr
4028 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), DSForm:$dst, 8),
4029 (STXSD (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC),
4031 def : Pat<(PPCstore_scal_int_from_vsr
4032 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), ForceXForm:$dst, 4),
4033 (STXSIWX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), ForceXForm:$dst)>;
4034 def : Pat<(PPCstore_scal_int_from_vsr
4035 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), ForceXForm:$dst, 2),
4036 (STXSIHX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), ForceXForm:$dst)>;
4037 def : Pat<(PPCstore_scal_int_from_vsr
4038 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), ForceXForm:$dst, 1),
4039 (STXSIBX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), ForceXForm:$dst)>;
4040 def : Pat<(PPCstore_scal_int_from_vsr
4041 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), XForm:$dst, 8),
4042 (STXSDX (XSCVDPSXDS f64:$src), XForm:$dst)>;
4043 def : Pat<(PPCstore_scal_int_from_vsr
4044 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), DSForm:$dst, 8),
4045 (STXSD (XSCVDPSXDS f64:$src), DSForm:$dst)>;
4046 def : Pat<(PPCstore_scal_int_from_vsr
4047 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), ForceXForm:$dst, 2),
4048 (STXSIHX (XSCVDPSXWS f64:$src), ForceXForm:$dst)>;
4049 def : Pat<(PPCstore_scal_int_from_vsr
4050 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), ForceXForm:$dst, 1),
4051 (STXSIBX (XSCVDPSXWS f64:$src), ForceXForm:$dst)>;
4053 // Instructions for store(fptoui).
4054 def : Pat<(PPCstore_scal_int_from_vsr
4055 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), XForm:$dst, 8),
4056 (STXSDX (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC),
4058 def : Pat<(PPCstore_scal_int_from_vsr
4059 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), DSForm:$dst, 8),
4060 (STXSD (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC),
4062 def : Pat<(PPCstore_scal_int_from_vsr
4063 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), ForceXForm:$dst, 4),
4064 (STXSIWX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), ForceXForm:$dst)>;
4065 def : Pat<(PPCstore_scal_int_from_vsr
4066 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), ForceXForm:$dst, 2),
4067 (STXSIHX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), ForceXForm:$dst)>;
4068 def : Pat<(PPCstore_scal_int_from_vsr
4069 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), ForceXForm:$dst, 1),
4070 (STXSIBX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), ForceXForm:$dst)>;
4071 def : Pat<(PPCstore_scal_int_from_vsr
4072 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), XForm:$dst, 8),
4073 (STXSDX (XSCVDPUXDS f64:$src), XForm:$dst)>;
4074 def : Pat<(PPCstore_scal_int_from_vsr
4075 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), DSForm:$dst, 8),
4076 (STXSD (XSCVDPUXDS f64:$src), DSForm:$dst)>;
4077 def : Pat<(PPCstore_scal_int_from_vsr
4078 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), ForceXForm:$dst, 2),
4079 (STXSIHX (XSCVDPUXWS f64:$src), ForceXForm:$dst)>;
4080 def : Pat<(PPCstore_scal_int_from_vsr
4081 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), ForceXForm:$dst, 1),
4082 (STXSIBX (XSCVDPUXWS f64:$src), ForceXForm:$dst)>;
4084 // Round & Convert QP -> DP/SP
4085 def : Pat<(f64 (any_fpround f128:$src)), (f64 (XSCVQPDP $src))>;
4086 def : Pat<(f32 (any_fpround f128:$src)), (f32 (XSRSP (XSCVQPDPO $src)))>;
4089 def : Pat<(f128 (any_fpextend f32:$src)),
4090 (f128 (XSCVDPQP (COPY_TO_REGCLASS $src, VFRC)))>;
4092 def : Pat<(f32 (PPCxsmaxc f32:$XA, f32:$XB)),
4093 (f32 (COPY_TO_REGCLASS (XSMAXCDP (COPY_TO_REGCLASS $XA, VSSRC),
4094 (COPY_TO_REGCLASS $XB, VSSRC)),
4096 def : Pat<(f32 (PPCxsminc f32:$XA, f32:$XB)),
4097 (f32 (COPY_TO_REGCLASS (XSMINCDP (COPY_TO_REGCLASS $XA, VSSRC),
4098 (COPY_TO_REGCLASS $XB, VSSRC)),
4101 // Endianness-neutral patterns for const splats with ISA 3.0 instructions.
4102 defm : ScalToVecWPermute<v4i32, (i32 i32:$A), (MTVSRWS $A),
4103 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>;
4104 def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
4105 (v4i32 (MTVSRWS $A))>;
4106 def : Pat<(v16i8 (build_vector immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
4107 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
4108 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
4109 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
4110 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
4111 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
4112 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
4113 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A)),
4114 (v16i8 (COPY_TO_REGCLASS (XXSPLTIB imm:$A), VSRC))>;
4115 defm : ScalToVecWPermute<
4116 v4i32, FltToIntLoad.A,
4117 (XVCVSPSXWS (LXVWSX ForceXForm:$A)),
4118 (XVCVSPSXWS (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64))>;
4119 defm : ScalToVecWPermute<
4120 v4i32, FltToUIntLoad.A,
4121 (XVCVSPUXWS (LXVWSX ForceXForm:$A)),
4122 (XVCVSPUXWS (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64))>;
4123 defm : ScalToVecWPermute<
4124 v4i32, DblToIntLoadP9.A,
4125 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64), 1),
4126 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64)>;
4127 defm : ScalToVecWPermute<
4128 v4i32, DblToUIntLoadP9.A,
4129 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64), 1),
4130 (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64)>;
4131 defm : ScalToVecWPermute<
4132 v2i64, FltToLongLoadP9.A,
4133 (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), 0),
4136 (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64)>;
4137 defm : ScalToVecWPermute<
4138 v2i64, FltToULongLoadP9.A,
4139 (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), 0),
4142 (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64)>;
4143 def : Pat<(v4f32 (PPCldsplat ForceXForm:$A)),
4144 (v4f32 (LXVWSX ForceXForm:$A))>;
4145 def : Pat<(v4i32 (PPCldsplat ForceXForm:$A)),
4146 (v4i32 (LXVWSX ForceXForm:$A))>;
4147 def : Pat<(v8i16 (PPCldsplat ForceXForm:$A)),
4148 (v8i16 (VSPLTHs 3, (LXSIHZX ForceXForm:$A)))>;
4149 def : Pat<(v16i8 (PPCldsplat ForceXForm:$A)),
4150 (v16i8 (VSPLTBs 7, (LXSIBZX ForceXForm:$A)))>;
4151 } // HasVSX, HasP9Vector
4153 // Any Power9 VSX subtarget with equivalent length but better Power10 VSX
4155 // Two identical blocks are required due to the slightly different predicates:
4156 // One without P10 instructions, the other is BigEndian only with P10 instructions.
4157 let Predicates = [HasVSX, HasP9Vector, NoP10Vector] in {
4158 // Little endian Power10 subtargets produce a shorter pattern but require a
4159 // COPY_TO_REGCLASS. The COPY_TO_REGCLASS makes it appear to need two instructions
4160 // to perform the operation, when only one instruction is produced in practice.
4161 // The NoP10Vector predicate excludes these patterns from Power10 VSX subtargets.
4162 defm : ScalToVecWPermute<
4163 v16i8, ScalarLoads.Li8,
4164 (VSPLTBs 7, (LXSIBZX ForceXForm:$src)),
4165 (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;
4166 // Build vectors from i16 loads
4167 defm : ScalToVecWPermute<
4168 v8i16, ScalarLoads.Li16,
4169 (VSPLTHs 3, (LXSIHZX ForceXForm:$src)),
4170 (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>;
4171 } // HasVSX, HasP9Vector, NoP10Vector
4173 // Any big endian Power9 VSX subtarget
4174 let Predicates = [HasVSX, HasP9Vector, IsBigEndian] in {
4175 // Power10 VSX subtargets produce a shorter pattern for little endian targets
4176 // but this is still the best pattern for Power9 and Power10 VSX big endian
4177 // Build vectors from i8 loads
4178 defm : ScalToVecWPermute<
4179 v16i8, ScalarLoads.Li8,
4180 (VSPLTBs 7, (LXSIBZX ForceXForm:$src)),
4181 (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;
4182 // Build vectors from i16 loads
4183 defm : ScalToVecWPermute<
4184 v8i16, ScalarLoads.Li16,
4185 (VSPLTHs 3, (LXSIHZX ForceXForm:$src)),
4186 (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>;
4188 def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
4189 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>;
4190 def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
4191 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>;
4192 def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),
4193 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>;
4194 def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
4195 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 12)))>;
4196 def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
4197 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 0)))>;
4198 def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
4199 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 4)))>;
4200 def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),
4201 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 8)))>;
4202 def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
4203 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 12)))>;
4204 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)),
4205 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>;
4206 def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 0)),
4207 (v4i32 (XXINSERTW v4i32:$A,
4208 (SUBREG_TO_REG (i64 1),
4209 (XSCVDPSXWS f64:$B), sub_64),
4211 def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 0)),
4212 (v4i32 (XXINSERTW v4i32:$A,
4213 (SUBREG_TO_REG (i64 1),
4214 (XSCVDPUXWS f64:$B), sub_64),
4216 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)),
4217 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>;
4218 def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 1)),
4219 (v4i32 (XXINSERTW v4i32:$A,
4220 (SUBREG_TO_REG (i64 1),
4221 (XSCVDPSXWS f64:$B), sub_64),
4223 def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 1)),
4224 (v4i32 (XXINSERTW v4i32:$A,
4225 (SUBREG_TO_REG (i64 1),
4226 (XSCVDPUXWS f64:$B), sub_64),
4228 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)),
4229 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>;
4230 def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 2)),
4231 (v4i32 (XXINSERTW v4i32:$A,
4232 (SUBREG_TO_REG (i64 1),
4233 (XSCVDPSXWS f64:$B), sub_64),
4235 def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 2)),
4236 (v4i32 (XXINSERTW v4i32:$A,
4237 (SUBREG_TO_REG (i64 1),
4238 (XSCVDPUXWS f64:$B), sub_64),
4240 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)),
4241 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>;
4242 def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 3)),
4243 (v4i32 (XXINSERTW v4i32:$A,
4244 (SUBREG_TO_REG (i64 1),
4245 (XSCVDPSXWS f64:$B), sub_64),
4247 def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 3)),
4248 (v4i32 (XXINSERTW v4i32:$A,
4249 (SUBREG_TO_REG (i64 1),
4250 (XSCVDPUXWS f64:$B), sub_64),
4252 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)),
4253 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>;
4254 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)),
4255 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>;
4256 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)),
4257 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>;
4258 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)),
4259 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>;
4261 def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 0)),
4262 (v4f32 (XXINSERTW v4f32:$A,
4263 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 0))>;
4264 def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 1)),
4265 (v4f32 (XXINSERTW v4f32:$A,
4266 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 4))>;
4267 def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 2)),
4268 (v4f32 (XXINSERTW v4f32:$A,
4269 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 8))>;
4270 def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 3)),
4271 (v4f32 (XXINSERTW v4f32:$A,
4272 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 12))>;
4274 // Scalar stores of i8
4275 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 0)), ForceXForm:$dst),
4276 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 9)), VSRC), ForceXForm:$dst)>;
4277 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 1)), ForceXForm:$dst),
4278 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>;
4279 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 2)), ForceXForm:$dst),
4280 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 11)), VSRC), ForceXForm:$dst)>;
4281 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 3)), ForceXForm:$dst),
4282 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), ForceXForm:$dst)>;
4283 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 4)), ForceXForm:$dst),
4284 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 13)), VSRC), ForceXForm:$dst)>;
4285 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 5)), ForceXForm:$dst),
4286 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), ForceXForm:$dst)>;
4287 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 6)), ForceXForm:$dst),
4288 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 15)), VSRC), ForceXForm:$dst)>;
4289 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 7)), ForceXForm:$dst),
4290 (STXSIBXv (COPY_TO_REGCLASS $S, VSRC), ForceXForm:$dst)>;
4291 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 8)), ForceXForm:$dst),
4292 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 1)), VSRC), ForceXForm:$dst)>;
4293 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 9)), ForceXForm:$dst),
4294 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), ForceXForm:$dst)>;
4295 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 10)), ForceXForm:$dst),
4296 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 3)), VSRC), ForceXForm:$dst)>;
4297 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 11)), ForceXForm:$dst),
4298 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), ForceXForm:$dst)>;
4299 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 12)), ForceXForm:$dst),
4300 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 5)), VSRC), ForceXForm:$dst)>;
4301 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 13)), ForceXForm:$dst),
4302 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), ForceXForm:$dst)>;
4303 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 14)), ForceXForm:$dst),
4304 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 7)), VSRC), ForceXForm:$dst)>;
4305 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 15)), ForceXForm:$dst),
4306 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), ForceXForm:$dst)>;
4308 // Scalar stores of i16
4309 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 0)), ForceXForm:$dst),
4310 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>;
4311 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 1)), ForceXForm:$dst),
4312 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), ForceXForm:$dst)>;
4313 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 2)), ForceXForm:$dst),
4314 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), ForceXForm:$dst)>;
4315 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 3)), ForceXForm:$dst),
4316 (STXSIHXv (COPY_TO_REGCLASS $S, VSRC), ForceXForm:$dst)>;
4317 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 4)), ForceXForm:$dst),
4318 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), ForceXForm:$dst)>;
4319 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 5)), ForceXForm:$dst),
4320 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), ForceXForm:$dst)>;
4321 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 6)), ForceXForm:$dst),
4322 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), ForceXForm:$dst)>;
4323 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), ForceXForm:$dst),
4324 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), ForceXForm:$dst)>;
4325 } // HasVSX, HasP9Vector, IsBigEndian
4327 // Big endian 64Bit Power9 subtarget.
4328 let Predicates = [HasVSX, HasP9Vector, IsBigEndian, IsPPC64] in {
4329 def : Pat<(v2i64 (scalar_to_vector (i64 (load DSForm:$src)))),
4330 (v2i64 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64))>;
4331 def : Pat<(v2i64 (scalar_to_vector (i64 (load XForm:$src)))),
4332 (v2i64 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64))>;
4334 def : Pat<(v2f64 (scalar_to_vector (f64 (load DSForm:$src)))),
4335 (v2f64 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64))>;
4336 def : Pat<(v2f64 (scalar_to_vector (f64 (load XForm:$src)))),
4337 (v2f64 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64))>;
4338 def : Pat<(store (i64 (extractelt v2i64:$A, 1)), XForm:$src),
4339 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
4340 sub_64), XForm:$src)>;
4341 def : Pat<(store (f64 (extractelt v2f64:$A, 1)), XForm:$src),
4342 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
4343 sub_64), XForm:$src)>;
4344 def : Pat<(store (i64 (extractelt v2i64:$A, 0)), XForm:$src),
4345 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), XForm:$src)>;
4346 def : Pat<(store (f64 (extractelt v2f64:$A, 0)), XForm:$src),
4347 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), XForm:$src)>;
4348 def : Pat<(store (i64 (extractelt v2i64:$A, 1)), DSForm:$src),
4349 (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
4350 sub_64), DSForm:$src)>;
4351 def : Pat<(store (f64 (extractelt v2f64:$A, 1)), DSForm:$src),
4352 (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
4353 sub_64), DSForm:$src)>;
4354 def : Pat<(store (i64 (extractelt v2i64:$A, 0)), DSForm:$src),
4355 (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), DSForm:$src)>;
4356 def : Pat<(store (f64 (extractelt v2f64:$A, 0)), DSForm:$src),
4357 (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), DSForm:$src)>;
4359 // (Un)Signed DWord vector extract -> QP
4360 def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))),
4361 (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
4362 def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))),
4364 (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
4365 def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))),
4366 (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
4367 def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))),
4369 (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
4371 // (Un)Signed Word vector extract -> QP
4372 def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 1)))),
4373 (f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>;
4374 foreach Idx = [0,2,3] in {
4375 def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, Idx)))),
4376 (f128 (XSCVSDQP (EXTRACT_SUBREG
4377 (VEXTSW2D (VSPLTW Idx, $src)), sub_64)))>;
4379 foreach Idx = 0-3 in {
4380 def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, Idx)))),
4381 (f128 (XSCVUDQP (XXEXTRACTUW $src, !shl(Idx, 2))))>;
4384 // (Un)Signed HWord vector extract -> QP/DP/SP
4385 foreach Idx = 0-7 in {
4386 def : Pat<(f128 (sint_to_fp
4388 (vector_extract v8i16:$src, Idx), i16)))),
4389 (f128 (XSCVSDQP (EXTRACT_SUBREG
4390 (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)),
4392 // The SDAG adds the `and` since an `i16` is being extracted as an `i32`.
4393 def : Pat<(f128 (uint_to_fp
4394 (and (i32 (vector_extract v8i16:$src, Idx)), 65535))),
4395 (f128 (XSCVUDQP (EXTRACT_SUBREG
4396 (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>;
4397 def : Pat<(f32 (PPCfcfidus
4398 (f64 (PPCmtvsrz (and (i32 (vector_extract v8i16:$src, Idx)),
4400 (f32 (XSCVUXDSP (EXTRACT_SUBREG
4401 (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>;
4402 def : Pat<(f32 (PPCfcfids
4404 (i32 (sext_inreg (vector_extract v8i16:$src, Idx),
4406 (f32 (XSCVSXDSP (EXTRACT_SUBREG
4407 (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)),
4409 def : Pat<(f64 (PPCfcfidu
4411 (and (i32 (vector_extract v8i16:$src, Idx)),
4413 (f64 (XSCVUXDDP (EXTRACT_SUBREG
4414 (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>;
4415 def : Pat<(f64 (PPCfcfid
4417 (i32 (sext_inreg (vector_extract v8i16:$src, Idx),
4419 (f64 (XSCVSXDDP (EXTRACT_SUBREG
4420 (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)),
4424 // (Un)Signed Byte vector extract -> QP
4425 foreach Idx = 0-15 in {
4426 def : Pat<(f128 (sint_to_fp
4427 (i32 (sext_inreg (vector_extract v16i8:$src, Idx),
4429 (f128 (XSCVSDQP (EXTRACT_SUBREG
4430 (VEXTSB2D (VEXTRACTUB Idx, $src)), sub_64)))>;
4431 def : Pat<(f128 (uint_to_fp
4432 (and (i32 (vector_extract v16i8:$src, Idx)), 255))),
4434 (EXTRACT_SUBREG (VEXTRACTUB Idx, $src), sub_64)))>;
4436 def : Pat<(f32 (PPCfcfidus
4438 (and (i32 (vector_extract v16i8:$src, Idx)),
4440 (f32 (XSCVUXDSP (EXTRACT_SUBREG
4441 (VEXTRACTUB !add(Idx, Idx), $src), sub_64)))>;
4442 def : Pat<(f32 (PPCfcfids
4444 (i32 (sext_inreg (vector_extract v16i8:$src, Idx),
4446 (f32 (XSCVSXDSP (EXTRACT_SUBREG
4447 (VEXTSH2D (VEXTRACTUB !add(Idx, Idx), $src)),
4449 def : Pat<(f64 (PPCfcfidu
4451 (and (i32 (vector_extract v16i8:$src, Idx)),
4453 (f64 (XSCVUXDDP (EXTRACT_SUBREG
4454 (VEXTRACTUB !add(Idx, Idx), $src), sub_64)))>;
4455 def : Pat<(f64 (PPCfcfid
4457 (i32 (sext_inreg (vector_extract v16i8:$src, Idx),
4459 (f64 (XSCVSXDDP (EXTRACT_SUBREG
4460 (VEXTSH2D (VEXTRACTUB !add(Idx, Idx), $src)),
4464 // Unsiged int in vsx register -> QP
4465 def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))),
4467 (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 4)))>;
4468 } // HasVSX, HasP9Vector, IsBigEndian, IsPPC64
4470 // Little endian Power9 subtarget.
4471 let Predicates = [HasVSX, HasP9Vector, IsLittleEndian] in {
4472 def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
4473 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 12)))>;
4474 def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
4475 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>;
4476 def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),
4477 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>;
4478 def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
4479 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>;
4480 def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
4481 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 12)))>;
4482 def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
4483 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 8)))>;
4484 def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),
4485 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 4)))>;
4486 def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
4487 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 0)))>;
4488 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)),
4489 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>;
4490 def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 0)),
4491 (v4i32 (XXINSERTW v4i32:$A,
4492 (SUBREG_TO_REG (i64 1),
4493 (XSCVDPSXWS f64:$B), sub_64),
4495 def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 0)),
4496 (v4i32 (XXINSERTW v4i32:$A,
4497 (SUBREG_TO_REG (i64 1),
4498 (XSCVDPUXWS f64:$B), sub_64),
4500 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)),
4501 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>;
4502 def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 1)),
4503 (v4i32 (XXINSERTW v4i32:$A,
4504 (SUBREG_TO_REG (i64 1),
4505 (XSCVDPSXWS f64:$B), sub_64),
4507 def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 1)),
4508 (v4i32 (XXINSERTW v4i32:$A,
4509 (SUBREG_TO_REG (i64 1),
4510 (XSCVDPUXWS f64:$B), sub_64),
4512 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)),
4513 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>;
4514 def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 2)),
4515 (v4i32 (XXINSERTW v4i32:$A,
4516 (SUBREG_TO_REG (i64 1),
4517 (XSCVDPSXWS f64:$B), sub_64),
4519 def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 2)),
4520 (v4i32 (XXINSERTW v4i32:$A,
4521 (SUBREG_TO_REG (i64 1),
4522 (XSCVDPUXWS f64:$B), sub_64),
4524 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)),
4525 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>;
4526 def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 3)),
4527 (v4i32 (XXINSERTW v4i32:$A,
4528 (SUBREG_TO_REG (i64 1),
4529 (XSCVDPSXWS f64:$B), sub_64),
4531 def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 3)),
4532 (v4i32 (XXINSERTW v4i32:$A,
4533 (SUBREG_TO_REG (i64 1),
4534 (XSCVDPUXWS f64:$B), sub_64),
4536 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)),
4537 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>;
4538 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)),
4539 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>;
4540 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)),
4541 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>;
4542 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)),
4543 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>;
4545 def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 0)),
4546 (v4f32 (XXINSERTW v4f32:$A,
4547 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 12))>;
4548 def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 1)),
4549 (v4f32 (XXINSERTW v4f32:$A,
4550 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 8))>;
4551 def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 2)),
4552 (v4f32 (XXINSERTW v4f32:$A,
4553 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 4))>;
4554 def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 3)),
4555 (v4f32 (XXINSERTW v4f32:$A,
4556 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 0))>;
4558 def : Pat<(v8i16 (PPCld_vec_be ForceXForm:$src)),
4559 (COPY_TO_REGCLASS (LXVH8X ForceXForm:$src), VRRC)>;
4560 def : Pat<(PPCst_vec_be v8i16:$rS, ForceXForm:$dst),
4561 (STXVH8X (COPY_TO_REGCLASS $rS, VSRC), ForceXForm:$dst)>;
4563 def : Pat<(v16i8 (PPCld_vec_be ForceXForm:$src)),
4564 (COPY_TO_REGCLASS (LXVB16X ForceXForm:$src), VRRC)>;
4565 def : Pat<(PPCst_vec_be v16i8:$rS, ForceXForm:$dst),
4566 (STXVB16X (COPY_TO_REGCLASS $rS, VSRC), ForceXForm:$dst)>;
4568 // Scalar stores of i8
4569 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 0)), ForceXForm:$dst),
4570 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), ForceXForm:$dst)>;
4571 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 1)), ForceXForm:$dst),
4572 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 7)), VSRC), ForceXForm:$dst)>;
4573 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 2)), ForceXForm:$dst),
4574 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), ForceXForm:$dst)>;
4575 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 3)), ForceXForm:$dst),
4576 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 5)), VSRC), ForceXForm:$dst)>;
4577 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 4)), ForceXForm:$dst),
4578 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), ForceXForm:$dst)>;
4579 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 5)), ForceXForm:$dst),
4580 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 3)), VSRC), ForceXForm:$dst)>;
4581 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 6)), ForceXForm:$dst),
4582 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), ForceXForm:$dst)>;
4583 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 7)), ForceXForm:$dst),
4584 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 1)), VSRC), ForceXForm:$dst)>;
4585 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 8)), ForceXForm:$dst),
4586 (STXSIBXv (COPY_TO_REGCLASS $S, VSRC), ForceXForm:$dst)>;
4587 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 9)), ForceXForm:$dst),
4588 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 15)), VSRC), ForceXForm:$dst)>;
4589 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 10)), ForceXForm:$dst),
4590 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), ForceXForm:$dst)>;
4591 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 11)), ForceXForm:$dst),
4592 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 13)), VSRC), ForceXForm:$dst)>;
4593 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 12)), ForceXForm:$dst),
4594 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), ForceXForm:$dst)>;
4595 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 13)), ForceXForm:$dst),
4596 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 11)), VSRC), ForceXForm:$dst)>;
4597 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 14)), ForceXForm:$dst),
4598 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>;
4599 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 15)), ForceXForm:$dst),
4600 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 9)), VSRC), ForceXForm:$dst)>;
4602 // Scalar stores of i16
4603 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 0)), ForceXForm:$dst),
4604 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), ForceXForm:$dst)>;
4605 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 1)), ForceXForm:$dst),
4606 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), ForceXForm:$dst)>;
4607 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 2)), ForceXForm:$dst),
4608 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), ForceXForm:$dst)>;
4609 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 3)), ForceXForm:$dst),
4610 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), ForceXForm:$dst)>;
4611 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 4)), ForceXForm:$dst),
4612 (STXSIHXv (COPY_TO_REGCLASS $S, VSRC), ForceXForm:$dst)>;
4613 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 5)), ForceXForm:$dst),
4614 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), ForceXForm:$dst)>;
4615 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 6)), ForceXForm:$dst),
4616 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), ForceXForm:$dst)>;
4617 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), ForceXForm:$dst),
4618 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>;
4620 defm : ScalToVecWPermute<
4621 v2i64, (i64 (load DSForm:$src)),
4622 (XXPERMDIs (DFLOADf64 DSForm:$src), 2),
4623 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>;
4624 defm : ScalToVecWPermute<
4625 v2i64, (i64 (load XForm:$src)),
4626 (XXPERMDIs (XFLOADf64 XForm:$src), 2),
4627 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>;
4628 defm : ScalToVecWPermute<
4629 v2f64, (f64 (load DSForm:$src)),
4630 (XXPERMDIs (DFLOADf64 DSForm:$src), 2),
4631 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>;
4632 defm : ScalToVecWPermute<
4633 v2f64, (f64 (load XForm:$src)),
4634 (XXPERMDIs (XFLOADf64 XForm:$src), 2),
4635 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>;
4637 def : Pat<(store (i64 (extractelt v2i64:$A, 0)), XForm:$src),
4638 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
4639 sub_64), XForm:$src)>;
4640 def : Pat<(store (f64 (extractelt v2f64:$A, 0)), XForm:$src),
4641 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
4642 sub_64), XForm:$src)>;
4643 def : Pat<(store (i64 (extractelt v2i64:$A, 1)), XForm:$src),
4644 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), XForm:$src)>;
4645 def : Pat<(store (f64 (extractelt v2f64:$A, 1)), XForm:$src),
4646 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), XForm:$src)>;
4647 def : Pat<(store (i64 (extractelt v2i64:$A, 0)), DSForm:$src),
4648 (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
4649 sub_64), DSForm:$src)>;
4650 def : Pat<(store (f64 (extractelt v2f64:$A, 0)), DSForm:$src),
4651 (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64),
4653 def : Pat<(store (i64 (extractelt v2i64:$A, 1)), DSForm:$src),
4654 (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), DSForm:$src)>;
4655 def : Pat<(store (f64 (extractelt v2f64:$A, 1)), DSForm:$src),
4656 (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), DSForm:$src)>;
4658 // (Un)Signed DWord vector extract -> QP
4659 def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))),
4661 (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
4662 def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))),
4663 (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
4664 def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))),
4666 (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
4667 def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))),
4668 (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
4670 // (Un)Signed Word vector extract -> QP
4671 foreach Idx = [[0,3],[1,2],[3,0]] in {
4672 def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))),
4673 (f128 (XSCVSDQP (EXTRACT_SUBREG
4674 (VEXTSW2D (VSPLTW !head(!tail(Idx)), $src)),
4677 def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 2)))),
4678 (f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>;
4680 foreach Idx = [[0,12],[1,8],[2,4],[3,0]] in {
4681 def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))),
4682 (f128 (XSCVUDQP (XXEXTRACTUW $src, !head(!tail(Idx)))))>;
4685 // (Un)Signed HWord vector extract -> QP/DP/SP
4686 // The Nested foreach lists identifies the vector element and corresponding
4687 // register byte location.
4688 foreach Idx = [[0,14],[1,12],[2,10],[3,8],[4,6],[5,4],[6,2],[7,0]] in {
4689 def : Pat<(f128 (sint_to_fp
4691 (vector_extract v8i16:$src, !head(Idx)), i16)))),
4693 (EXTRACT_SUBREG (VEXTSH2D
4694 (VEXTRACTUH !head(!tail(Idx)), $src)),
4696 def : Pat<(f128 (uint_to_fp
4697 (and (i32 (vector_extract v8i16:$src, !head(Idx))),
4699 (f128 (XSCVUDQP (EXTRACT_SUBREG
4700 (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>;
4701 def : Pat<(f32 (PPCfcfidus
4703 (and (i32 (vector_extract v8i16:$src, !head(Idx))),
4705 (f32 (XSCVUXDSP (EXTRACT_SUBREG
4706 (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>;
4707 def : Pat<(f32 (PPCfcfids
4709 (i32 (sext_inreg (vector_extract v8i16:$src,
4710 !head(Idx)), i16)))))),
4713 (VEXTSH2D (VEXTRACTUH !head(!tail(Idx)), $src)),
4715 def : Pat<(f64 (PPCfcfidu
4717 (and (i32 (vector_extract v8i16:$src, !head(Idx))),
4719 (f64 (XSCVUXDDP (EXTRACT_SUBREG
4720 (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>;
4721 def : Pat<(f64 (PPCfcfid
4724 (vector_extract v8i16:$src, !head(Idx)), i16)))))),
4726 (EXTRACT_SUBREG (VEXTSH2D
4727 (VEXTRACTUH !head(!tail(Idx)), $src)),
4731 // (Un)Signed Byte vector extract -> QP/DP/SP
4732 foreach Idx = [[0,15],[1,14],[2,13],[3,12],[4,11],[5,10],[6,9],[7,8],[8,7],
4733 [9,6],[10,5],[11,4],[12,3],[13,2],[14,1],[15,0]] in {
4734 def : Pat<(f128 (sint_to_fp
4736 (vector_extract v16i8:$src, !head(Idx)), i8)))),
4739 (VEXTSB2D (VEXTRACTUB !head(!tail(Idx)), $src)),
4741 def : Pat<(f128 (uint_to_fp
4742 (and (i32 (vector_extract v16i8:$src, !head(Idx))),
4746 (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>;
4748 def : Pat<(f32 (PPCfcfidus
4750 (and (i32 (vector_extract v16i8:$src, !head(Idx))),
4752 (f32 (XSCVUXDSP (EXTRACT_SUBREG
4753 (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>;
4754 def : Pat<(f32 (PPCfcfids
4757 (vector_extract v16i8:$src, !head(Idx)), i8)))))),
4759 (EXTRACT_SUBREG (VEXTSH2D
4760 (VEXTRACTUB !head(!tail(Idx)), $src)),
4762 def : Pat<(f64 (PPCfcfidu
4765 (vector_extract v16i8:$src, !head(Idx))), 255))))),
4766 (f64 (XSCVUXDDP (EXTRACT_SUBREG
4767 (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>;
4768 def : Pat<(f64 (PPCfcfidu
4771 (vector_extract v16i8:$src, !head(Idx)), i8)))))),
4773 (EXTRACT_SUBREG (VEXTSH2D
4774 (VEXTRACTUB !head(!tail(Idx)), $src)),
4777 def : Pat<(f64 (PPCfcfid
4780 (vector_extract v16i8:$src, !head(Idx)), i8)))))),
4782 (EXTRACT_SUBREG (VEXTSH2D
4783 (VEXTRACTUH !head(!tail(Idx)), $src)),
4787 // Unsiged int in vsx register -> QP
4788 def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))),
4790 (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 8)))>;
4791 } // HasVSX, HasP9Vector, IsLittleEndian
4793 // Any Power9 VSX subtarget that supports Power9 Altivec.
4794 let Predicates = [HasVSX, HasP9Altivec] in {
4795 // Put this P9Altivec related definition here since it's possible to be
4796 // selected to VSX instruction xvnegsp, avoid possible undef.
4797 def : Pat<(v4i32 (PPCvabsd v4i32:$A, v4i32:$B, (i32 0))),
4798 (v4i32 (VABSDUW $A, $B))>;
4800 def : Pat<(v8i16 (PPCvabsd v8i16:$A, v8i16:$B, (i32 0))),
4801 (v8i16 (VABSDUH $A, $B))>;
4803 def : Pat<(v16i8 (PPCvabsd v16i8:$A, v16i8:$B, (i32 0))),
4804 (v16i8 (VABSDUB $A, $B))>;
4806 // As PPCVABSD description, the last operand indicates whether do the
4808 def : Pat<(v4i32 (PPCvabsd v4i32:$A, v4i32:$B, (i32 1))),
4809 (v4i32 (VABSDUW (XVNEGSP $A), (XVNEGSP $B)))>;
4810 } // HasVSX, HasP9Altivec
4812 // Big endian Power9 64Bit VSX subtargets with P9 Altivec support.
4813 let Predicates = [HasVSX, HasP9Altivec, IsBigEndian, IsPPC64] in {
4814 def : Pat<(i64 (anyext (i32 (vector_extract v16i8:$S, i64:$Idx)))),
4815 (VEXTUBLX $Idx, $S)>;
4817 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, i64:$Idx)))),
4818 (VEXTUHLX (RLWINM8 $Idx, 1, 28, 30), $S)>;
4819 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 0)))),
4820 (VEXTUHLX (LI8 0), $S)>;
4821 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 1)))),
4822 (VEXTUHLX (LI8 2), $S)>;
4823 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 2)))),
4824 (VEXTUHLX (LI8 4), $S)>;
4825 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 3)))),
4826 (VEXTUHLX (LI8 6), $S)>;
4827 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 4)))),
4828 (VEXTUHLX (LI8 8), $S)>;
4829 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 5)))),
4830 (VEXTUHLX (LI8 10), $S)>;
4831 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 6)))),
4832 (VEXTUHLX (LI8 12), $S)>;
4833 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 7)))),
4834 (VEXTUHLX (LI8 14), $S)>;
4836 def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, i64:$Idx)))),
4837 (VEXTUWLX (RLWINM8 $Idx, 2, 28, 29), $S)>;
4838 def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 0)))),
4839 (VEXTUWLX (LI8 0), $S)>;
4841 // For extracting BE word 1, MFVSRWZ is better than VEXTUWLX
4842 def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 1)))),
4843 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
4844 (i32 VectorExtractions.LE_WORD_2), sub_32)>;
4845 def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 2)))),
4846 (VEXTUWLX (LI8 8), $S)>;
4847 def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 3)))),
4848 (VEXTUWLX (LI8 12), $S)>;
4850 def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, i64:$Idx)))),
4851 (EXTSW (VEXTUWLX (RLWINM8 $Idx, 2, 28, 29), $S))>;
4852 def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 0)))),
4853 (EXTSW (VEXTUWLX (LI8 0), $S))>;
4854 // For extracting BE word 1, MFVSRWZ is better than VEXTUWLX
4855 def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 1)))),
4856 (EXTSW (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
4857 (i32 VectorExtractions.LE_WORD_2), sub_32))>;
4858 def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 2)))),
4859 (EXTSW (VEXTUWLX (LI8 8), $S))>;
4860 def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 3)))),
4861 (EXTSW (VEXTUWLX (LI8 12), $S))>;
4863 def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)),
4864 (i32 (EXTRACT_SUBREG (VEXTUBLX $Idx, $S), sub_32))>;
4865 def : Pat<(i32 (vector_extract v16i8:$S, 0)),
4866 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 0), $S), sub_32))>;
4867 def : Pat<(i32 (vector_extract v16i8:$S, 1)),
4868 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 1), $S), sub_32))>;
4869 def : Pat<(i32 (vector_extract v16i8:$S, 2)),
4870 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 2), $S), sub_32))>;
4871 def : Pat<(i32 (vector_extract v16i8:$S, 3)),
4872 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 3), $S), sub_32))>;
4873 def : Pat<(i32 (vector_extract v16i8:$S, 4)),
4874 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 4), $S), sub_32))>;
4875 def : Pat<(i32 (vector_extract v16i8:$S, 5)),
4876 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 5), $S), sub_32))>;
4877 def : Pat<(i32 (vector_extract v16i8:$S, 6)),
4878 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 6), $S), sub_32))>;
4879 def : Pat<(i32 (vector_extract v16i8:$S, 7)),
4880 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 7), $S), sub_32))>;
4881 def : Pat<(i32 (vector_extract v16i8:$S, 8)),
4882 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 8), $S), sub_32))>;
4883 def : Pat<(i32 (vector_extract v16i8:$S, 9)),
4884 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 9), $S), sub_32))>;
4885 def : Pat<(i32 (vector_extract v16i8:$S, 10)),
4886 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 10), $S), sub_32))>;
4887 def : Pat<(i32 (vector_extract v16i8:$S, 11)),
4888 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 11), $S), sub_32))>;
4889 def : Pat<(i32 (vector_extract v16i8:$S, 12)),
4890 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 12), $S), sub_32))>;
4891 def : Pat<(i32 (vector_extract v16i8:$S, 13)),
4892 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 13), $S), sub_32))>;
4893 def : Pat<(i32 (vector_extract v16i8:$S, 14)),
4894 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 14), $S), sub_32))>;
4895 def : Pat<(i32 (vector_extract v16i8:$S, 15)),
4896 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 15), $S), sub_32))>;
4898 def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)),
4899 (i32 (EXTRACT_SUBREG (VEXTUHLX
4900 (RLWINM8 $Idx, 1, 28, 30), $S), sub_32))>;
4901 def : Pat<(i32 (vector_extract v8i16:$S, 0)),
4902 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 0), $S), sub_32))>;
4903 def : Pat<(i32 (vector_extract v8i16:$S, 1)),
4904 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 2), $S), sub_32))>;
4905 def : Pat<(i32 (vector_extract v8i16:$S, 2)),
4906 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 4), $S), sub_32))>;
4907 def : Pat<(i32 (vector_extract v8i16:$S, 3)),
4908 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 6), $S), sub_32))>;
4909 def : Pat<(i32 (vector_extract v8i16:$S, 4)),
4910 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 8), $S), sub_32))>;
4911 def : Pat<(i32 (vector_extract v8i16:$S, 5)),
4912 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 10), $S), sub_32))>;
4913 def : Pat<(i32 (vector_extract v8i16:$S, 6)),
4914 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 12), $S), sub_32))>;
4915 def : Pat<(i32 (vector_extract v8i16:$S, 6)),
4916 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 14), $S), sub_32))>;
4918 def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)),
4919 (i32 (EXTRACT_SUBREG (VEXTUWLX
4920 (RLWINM8 $Idx, 2, 28, 29), $S), sub_32))>;
4921 def : Pat<(i32 (vector_extract v4i32:$S, 0)),
4922 (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 0), $S), sub_32))>;
4923 // For extracting BE word 1, MFVSRWZ is better than VEXTUWLX
4924 def : Pat<(i32 (vector_extract v4i32:$S, 1)),
4925 (i32 VectorExtractions.LE_WORD_2)>;
4926 def : Pat<(i32 (vector_extract v4i32:$S, 2)),
4927 (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 8), $S), sub_32))>;
4928 def : Pat<(i32 (vector_extract v4i32:$S, 3)),
4929 (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 12), $S), sub_32))>;
4931 // P9 Altivec instructions that can be used to build vectors.
4932 // Adding them to PPCInstrVSX.td rather than PPCAltivecVSX.td to compete
4933 // with complexities of existing build vector patterns in this file.
4934 def : Pat<(v2i64 (build_vector WordToDWord.BE_A0, WordToDWord.BE_A1)),
4935 (v2i64 (VEXTSW2D $A))>;
4936 def : Pat<(v2i64 (build_vector HWordToDWord.BE_A0, HWordToDWord.BE_A1)),
4937 (v2i64 (VEXTSH2D $A))>;
4938 def : Pat<(v4i32 (build_vector HWordToWord.BE_A0, HWordToWord.BE_A1,
4939 HWordToWord.BE_A2, HWordToWord.BE_A3)),
4940 (v4i32 (VEXTSH2W $A))>;
4941 def : Pat<(v4i32 (build_vector ByteToWord.BE_A0, ByteToWord.BE_A1,
4942 ByteToWord.BE_A2, ByteToWord.BE_A3)),
4943 (v4i32 (VEXTSB2W $A))>;
4944 def : Pat<(v2i64 (build_vector ByteToDWord.BE_A0, ByteToDWord.BE_A1)),
4945 (v2i64 (VEXTSB2D $A))>;
4946 } // HasVSX, HasP9Altivec, IsBigEndian, IsPPC64
4948 // Little endian Power9 VSX subtargets with P9 Altivec support.
4949 let Predicates = [HasVSX, HasP9Altivec, IsLittleEndian] in {
4950 def : Pat<(i64 (anyext (i32 (vector_extract v16i8:$S, i64:$Idx)))),
4951 (VEXTUBRX $Idx, $S)>;
4953 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, i64:$Idx)))),
4954 (VEXTUHRX (RLWINM8 $Idx, 1, 28, 30), $S)>;
4955 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 0)))),
4956 (VEXTUHRX (LI8 0), $S)>;
4957 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 1)))),
4958 (VEXTUHRX (LI8 2), $S)>;
4959 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 2)))),
4960 (VEXTUHRX (LI8 4), $S)>;
4961 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 3)))),
4962 (VEXTUHRX (LI8 6), $S)>;
4963 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 4)))),
4964 (VEXTUHRX (LI8 8), $S)>;
4965 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 5)))),
4966 (VEXTUHRX (LI8 10), $S)>;
4967 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 6)))),
4968 (VEXTUHRX (LI8 12), $S)>;
4969 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 7)))),
4970 (VEXTUHRX (LI8 14), $S)>;
4972 def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, i64:$Idx)))),
4973 (VEXTUWRX (RLWINM8 $Idx, 2, 28, 29), $S)>;
4974 def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 0)))),
4975 (VEXTUWRX (LI8 0), $S)>;
4976 def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 1)))),
4977 (VEXTUWRX (LI8 4), $S)>;
4978 // For extracting LE word 2, MFVSRWZ is better than VEXTUWRX
4979 def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 2)))),
4980 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
4981 (i32 VectorExtractions.LE_WORD_2), sub_32)>;
4982 def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 3)))),
4983 (VEXTUWRX (LI8 12), $S)>;
4985 def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, i64:$Idx)))),
4986 (EXTSW (VEXTUWRX (RLWINM8 $Idx, 2, 28, 29), $S))>;
4987 def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 0)))),
4988 (EXTSW (VEXTUWRX (LI8 0), $S))>;
4989 def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 1)))),
4990 (EXTSW (VEXTUWRX (LI8 4), $S))>;
4991 // For extracting LE word 2, MFVSRWZ is better than VEXTUWRX
4992 def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 2)))),
4993 (EXTSW (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
4994 (i32 VectorExtractions.LE_WORD_2), sub_32))>;
4995 def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 3)))),
4996 (EXTSW (VEXTUWRX (LI8 12), $S))>;
4998 def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)),
4999 (i32 (EXTRACT_SUBREG (VEXTUBRX $Idx, $S), sub_32))>;
5000 def : Pat<(i32 (vector_extract v16i8:$S, 0)),
5001 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 0), $S), sub_32))>;
5002 def : Pat<(i32 (vector_extract v16i8:$S, 1)),
5003 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 1), $S), sub_32))>;
5004 def : Pat<(i32 (vector_extract v16i8:$S, 2)),
5005 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 2), $S), sub_32))>;
5006 def : Pat<(i32 (vector_extract v16i8:$S, 3)),
5007 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 3), $S), sub_32))>;
5008 def : Pat<(i32 (vector_extract v16i8:$S, 4)),
5009 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 4), $S), sub_32))>;
5010 def : Pat<(i32 (vector_extract v16i8:$S, 5)),
5011 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 5), $S), sub_32))>;
5012 def : Pat<(i32 (vector_extract v16i8:$S, 6)),
5013 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 6), $S), sub_32))>;
5014 def : Pat<(i32 (vector_extract v16i8:$S, 7)),
5015 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 7), $S), sub_32))>;
5016 def : Pat<(i32 (vector_extract v16i8:$S, 8)),
5017 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 8), $S), sub_32))>;
5018 def : Pat<(i32 (vector_extract v16i8:$S, 9)),
5019 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 9), $S), sub_32))>;
5020 def : Pat<(i32 (vector_extract v16i8:$S, 10)),
5021 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 10), $S), sub_32))>;
5022 def : Pat<(i32 (vector_extract v16i8:$S, 11)),
5023 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 11), $S), sub_32))>;
5024 def : Pat<(i32 (vector_extract v16i8:$S, 12)),
5025 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 12), $S), sub_32))>;
5026 def : Pat<(i32 (vector_extract v16i8:$S, 13)),
5027 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 13), $S), sub_32))>;
5028 def : Pat<(i32 (vector_extract v16i8:$S, 14)),
5029 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 14), $S), sub_32))>;
5030 def : Pat<(i32 (vector_extract v16i8:$S, 15)),
5031 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 15), $S), sub_32))>;
5033 def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)),
5034 (i32 (EXTRACT_SUBREG (VEXTUHRX
5035 (RLWINM8 $Idx, 1, 28, 30), $S), sub_32))>;
5036 def : Pat<(i32 (vector_extract v8i16:$S, 0)),
5037 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 0), $S), sub_32))>;
5038 def : Pat<(i32 (vector_extract v8i16:$S, 1)),
5039 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 2), $S), sub_32))>;
5040 def : Pat<(i32 (vector_extract v8i16:$S, 2)),
5041 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 4), $S), sub_32))>;
5042 def : Pat<(i32 (vector_extract v8i16:$S, 3)),
5043 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 6), $S), sub_32))>;
5044 def : Pat<(i32 (vector_extract v8i16:$S, 4)),
5045 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 8), $S), sub_32))>;
5046 def : Pat<(i32 (vector_extract v8i16:$S, 5)),
5047 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 10), $S), sub_32))>;
5048 def : Pat<(i32 (vector_extract v8i16:$S, 6)),
5049 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 12), $S), sub_32))>;
5050 def : Pat<(i32 (vector_extract v8i16:$S, 6)),
5051 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 14), $S), sub_32))>;
5053 def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)),
5054 (i32 (EXTRACT_SUBREG (VEXTUWRX
5055 (RLWINM8 $Idx, 2, 28, 29), $S), sub_32))>;
5056 def : Pat<(i32 (vector_extract v4i32:$S, 0)),
5057 (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 0), $S), sub_32))>;
5058 def : Pat<(i32 (vector_extract v4i32:$S, 1)),
5059 (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 4), $S), sub_32))>;
5060 // For extracting LE word 2, MFVSRWZ is better than VEXTUWRX
5061 def : Pat<(i32 (vector_extract v4i32:$S, 2)),
5062 (i32 VectorExtractions.LE_WORD_2)>;
5063 def : Pat<(i32 (vector_extract v4i32:$S, 3)),
5064 (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 12), $S), sub_32))>;
5066 // P9 Altivec instructions that can be used to build vectors.
5067 // Adding them to PPCInstrVSX.td rather than PPCAltivecVSX.td to compete
5068 // with complexities of existing build vector patterns in this file.
5069 def : Pat<(v2i64 (build_vector WordToDWord.LE_A0, WordToDWord.LE_A1)),
5070 (v2i64 (VEXTSW2D $A))>;
5071 def : Pat<(v2i64 (build_vector HWordToDWord.LE_A0, HWordToDWord.LE_A1)),
5072 (v2i64 (VEXTSH2D $A))>;
5073 def : Pat<(v4i32 (build_vector HWordToWord.LE_A0, HWordToWord.LE_A1,
5074 HWordToWord.LE_A2, HWordToWord.LE_A3)),
5075 (v4i32 (VEXTSH2W $A))>;
5076 def : Pat<(v4i32 (build_vector ByteToWord.LE_A0, ByteToWord.LE_A1,
5077 ByteToWord.LE_A2, ByteToWord.LE_A3)),
5078 (v4i32 (VEXTSB2W $A))>;
5079 def : Pat<(v2i64 (build_vector ByteToDWord.LE_A0, ByteToDWord.LE_A1)),
5080 (v2i64 (VEXTSB2D $A))>;
5081 } // HasVSX, HasP9Altivec, IsLittleEndian
5083 // Big endian 64Bit VSX subtarget that supports additional direct moves from
5085 let Predicates = [HasVSX, IsISA3_0, HasDirectMove, IsBigEndian, IsPPC64] in {
5086 def : Pat<(i64 (extractelt v2i64:$A, 1)),
5087 (i64 (MFVSRLD $A))>;
5088 // Better way to build integer vectors if we have MTVSRDD. Big endian.
5089 def : Pat<(v2i64 (build_vector i64:$rB, i64:$rA)),
5090 (v2i64 (MTVSRDD $rB, $rA))>;
5091 def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
5093 (RLDIMI AnyExts.B, AnyExts.A, 32, 0),
5094 (RLDIMI AnyExts.D, AnyExts.C, 32, 0))>;
5096 def : Pat<(f128 (PPCbuild_fp128 i64:$rB, i64:$rA)),
5097 (f128 (COPY_TO_REGCLASS (MTVSRDD $rB, $rA), VRRC))>;
5098 } // HasVSX, IsISA3_0, HasDirectMove, IsBigEndian, IsPPC64
5100 // Little endian VSX subtarget that supports direct moves from ISA3.0.
5101 let Predicates = [HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian] in {
5102 def : Pat<(i64 (extractelt v2i64:$A, 0)),
5103 (i64 (MFVSRLD $A))>;
5104 // Better way to build integer vectors if we have MTVSRDD. Little endian.
5105 def : Pat<(v2i64 (build_vector i64:$rA, i64:$rB)),
5106 (v2i64 (MTVSRDD $rB, $rA))>;
5107 def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
5109 (RLDIMI AnyExts.C, AnyExts.D, 32, 0),
5110 (RLDIMI AnyExts.A, AnyExts.B, 32, 0))>;
5112 def : Pat<(f128 (PPCbuild_fp128 i64:$rA, i64:$rB)),
5113 (f128 (COPY_TO_REGCLASS (MTVSRDD $rB, $rA), VRRC))>;
5114 } // HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian
5115 } // AddedComplexity = 400
5117 //---------------------------- Instruction aliases ---------------------------//
5118 def : InstAlias<"xvmovdp $XT, $XB",
5119 (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
5120 def : InstAlias<"xvmovsp $XT, $XB",
5121 (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
5123 // Certain versions of the AIX assembler may missassemble these mnemonics.
5124 let Predicates = [ModernAs] in {
5125 def : InstAlias<"xxspltd $XT, $XB, 0",
5126 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0)>;
5127 def : InstAlias<"xxspltd $XT, $XB, 1",
5128 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3)>;
5129 def : InstAlias<"xxspltd $XT, $XB, 0",
5130 (XXPERMDIs vsrc:$XT, vsfrc:$XB, 0)>;
5131 def : InstAlias<"xxspltd $XT, $XB, 1",
5132 (XXPERMDIs vsrc:$XT, vsfrc:$XB, 3)>;
5135 def : InstAlias<"xxmrghd $XT, $XA, $XB",
5136 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0)>;
5137 def : InstAlias<"xxmrgld $XT, $XA, $XB",
5138 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3)>;
5139 def : InstAlias<"xxswapd $XT, $XB",
5140 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>;
5141 def : InstAlias<"xxswapd $XT, $XB",
5142 (XXPERMDIs vsrc:$XT, vsfrc:$XB, 2)>;
5143 def : InstAlias<"mfvrd $rA, $XT",
5144 (MFVRD g8rc:$rA, vrrc:$XT), 0>;
5145 def : InstAlias<"mffprd $rA, $src",
5146 (MFVSRD g8rc:$rA, f8rc:$src)>;
5147 def : InstAlias<"mtvrd $XT, $rA",
5148 (MTVRD vrrc:$XT, g8rc:$rA), 0>;
5149 def : InstAlias<"mtfprd $dst, $rA",
5150 (MTVSRD f8rc:$dst, g8rc:$rA)>;
5151 def : InstAlias<"mfvrwz $rA, $XT",
5152 (MFVRWZ gprc:$rA, vrrc:$XT), 0>;
5153 def : InstAlias<"mffprwz $rA, $src",
5154 (MFVSRWZ gprc:$rA, f8rc:$src)>;
5155 def : InstAlias<"mtvrwa $XT, $rA",
5156 (MTVRWA vrrc:$XT, gprc:$rA), 0>;
5157 def : InstAlias<"mtfprwa $dst, $rA",
5158 (MTVSRWA f8rc:$dst, gprc:$rA)>;
5159 def : InstAlias<"mtvrwz $XT, $rA",
5160 (MTVRWZ vrrc:$XT, gprc:$rA), 0>;
5161 def : InstAlias<"mtfprwz $dst, $rA",
5162 (MTVSRWZ f8rc:$dst, gprc:$rA)>;