1 //===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the PowerPC implementation of the TargetRegisterInfo
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
17 #include "MCTargetDesc/PPCMCTargetDesc.h"
18 #include "llvm/ADT/DenseMap.h"
20 #define GET_REGINFO_HEADER
21 #include "PPCGenRegisterInfo.inc"
24 class PPCTargetMachine;
26 inline static unsigned getCRFromCRBit(unsigned SrcReg) {
28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
37 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
38 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
40 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
41 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
43 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
44 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
46 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
47 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
49 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
50 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
53 assert(Reg != 0 && "Invalid CR bit register");
57 class PPCRegisterInfo : public PPCGenRegisterInfo {
58 DenseMap<unsigned, unsigned> ImmToIdxMap;
59 const PPCTargetMachine &TM;
62 PPCRegisterInfo(const PPCTargetMachine &TM);
64 /// getMappedIdxOpcForImmOpc - Return the mapped index form load/store opcode
65 /// for a given imm form load/store opcode \p ImmFormOpcode.
66 /// FIXME: move this to PPCInstrInfo class.
67 unsigned getMappedIdxOpcForImmOpc(unsigned ImmOpcode) const {
68 if (!ImmToIdxMap.count(ImmOpcode))
69 return PPC::INSTRUCTION_LIST_END;
70 return ImmToIdxMap.find(ImmOpcode)->second;
73 /// getPointerRegClass - Return the register class to use to hold pointers.
74 /// This is used for addressing modes.
75 const TargetRegisterClass *
76 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
78 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
79 MachineFunction &MF) const override;
81 const TargetRegisterClass *
82 getLargestLegalSuperClass(const TargetRegisterClass *RC,
83 const MachineFunction &MF) const override;
85 /// Code Generation virtual methods...
86 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
87 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
88 CallingConv::ID CC) const override;
89 const uint32_t *getNoPreservedMask() const override;
91 void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
93 BitVector getReservedRegs(const MachineFunction &MF) const override;
94 bool isCallerPreservedPhysReg(MCRegister PhysReg,
95 const MachineFunction &MF) const override;
97 /// We require the register scavenger.
98 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
102 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
104 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
108 void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
109 void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const;
110 void prepareDynamicAlloca(MachineBasicBlock::iterator II,
111 Register &NegSizeReg, bool &KillNegSizeReg,
112 Register &FramePointer) const;
113 void lowerPrepareProbedAlloca(MachineBasicBlock::iterator II) const;
114 void lowerCRSpilling(MachineBasicBlock::iterator II,
115 unsigned FrameIndex) const;
116 void lowerCRRestore(MachineBasicBlock::iterator II,
117 unsigned FrameIndex) const;
118 void lowerCRBitSpilling(MachineBasicBlock::iterator II,
119 unsigned FrameIndex) const;
120 void lowerCRBitRestore(MachineBasicBlock::iterator II,
121 unsigned FrameIndex) const;
122 void lowerVRSAVESpilling(MachineBasicBlock::iterator II,
123 unsigned FrameIndex) const;
124 void lowerVRSAVERestore(MachineBasicBlock::iterator II,
125 unsigned FrameIndex) const;
127 bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg,
128 int &FrameIdx) const override;
129 void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
130 unsigned FIOperandNum,
131 RegScavenger *RS = nullptr) const override;
133 // Support for virtual base registers.
134 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
135 void materializeFrameBaseRegister(MachineBasicBlock *MBB, Register BaseReg,
137 int64_t Offset) const override;
138 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
139 int64_t Offset) const override;
140 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
141 int64_t Offset) const override;
143 // Debug information queries.
144 Register getFrameRegister(const MachineFunction &MF) const override;
146 // Base pointer (stack realignment) support.
147 Register getBaseRegister(const MachineFunction &MF) const;
148 bool hasBasePointer(const MachineFunction &MF) const;
150 /// stripRegisterPrefix - This method strips the character prefix from a
151 /// register name so that only the number is left. Used by for linux asm.
152 static const char *stripRegisterPrefix(const char *RegName) {
153 switch (RegName[0]) {
158 if (RegName[1] == 's')
161 case 'c': if (RegName[1] == 'r') return RegName + 2;
168 } // end namespace llvm