1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements the PPC specific subclass of TargetSubtargetInfo.
11 //===----------------------------------------------------------------------===//
13 #include "PPCSubtarget.h"
15 #include "PPCRegisterInfo.h"
16 #include "PPCTargetMachine.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineScheduler.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/IR/GlobalValue.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetMachine.h"
29 #define DEBUG_TYPE "ppc-subtarget"
31 #define GET_SUBTARGETINFO_TARGET_DESC
32 #define GET_SUBTARGETINFO_CTOR
33 #include "PPCGenSubtargetInfo.inc"
35 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
36 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
38 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned",
39 cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"),
43 EnableMachinePipeliner("ppc-enable-pipeliner",
44 cl::desc("Enable Machine Pipeliner for PPC"),
45 cl::init(false), cl::Hidden);
47 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
49 initializeEnvironment();
50 initSubtargetFeatures(CPU, FS);
54 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
55 const std::string &FS, const PPCTargetMachine &TM)
56 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
57 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
58 TargetTriple.getArch() == Triple::ppc64le),
59 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
60 InstrInfo(*this), TLInfo(TM, *this) {}
62 void PPCSubtarget::initializeEnvironment() {
64 DarwinDirective = PPC::DIR_NONE;
66 Has64BitSupport = false;
75 NeedsTwoConstNR = false;
103 DeprecatedDST = false;
104 HasLazyResolverStubs = false;
106 HasInvariantFunctionDescriptors = false;
107 HasPartwordAtomics = false;
108 HasDirectMove = false;
109 IsQPXStackUnaligned = false;
113 UseLongCalls = false;
115 VectorsUseTwoUnits = false;
116 UsePPCPreRASchedStrategy = false;
117 UsePPCPostRASchedStrategy = false;
119 HasPOPCNTD = POPCNTD_Unavailable;
122 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
123 // Determine default and user specified characteristics
124 std::string CPUName = CPU;
125 if (CPUName.empty() || CPU == "generic") {
126 // If cross-compiling with -march=ppc64le without -mcpu
127 if (TargetTriple.getArch() == Triple::ppc64le)
133 // Initialize scheduling itinerary for the specified CPU.
134 InstrItins = getInstrItineraryForCPU(CPUName);
136 // Parse features string.
137 ParseSubtargetFeatures(CPUName, FS);
139 // If the user requested use of 64-bit regs, but the cpu selected doesn't
140 // support it, ignore.
141 if (IsPPC64 && has64BitSupport())
144 // Set up darwin-specific properties.
146 HasLazyResolverStubs = true;
148 if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) ||
149 TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() ||
150 TargetTriple.isMusl())
153 if (HasSPE && IsPPC64)
154 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
155 if (HasSPE && (HasAltivec || HasQPX || HasVSX || HasFPU))
157 "SPE and traditional floating point cannot both be enabled.\n", false);
159 // If not SPE, set standard FPU
163 // QPX requires a 32-byte aligned stack. Note that we need to do this if
164 // we're compiling for a BG/Q system regardless of whether or not QPX
165 // is enabled because external functions will assume this alignment.
166 IsQPXStackUnaligned = QPXStackUnaligned;
167 StackAlignment = getPlatformStackAlignment();
169 // Determine endianness.
170 // FIXME: Part of the TargetMachine.
171 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
174 /// Return true if accesses to the specified global have to go through a dyld
175 /// lazy resolution stub. This means that an extra load is required to get the
176 /// address of the global.
177 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
178 if (!HasLazyResolverStubs)
180 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
182 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
183 // the section that is being relocated. This means we have to use o load even
184 // for GVs that are known to be local to the dso.
185 if (GV->isDeclarationForLinker() || GV->hasCommonLinkage())
190 bool PPCSubtarget::enableMachineScheduler() const { return true; }
192 bool PPCSubtarget::enableMachinePipeliner() const {
193 return (DarwinDirective == PPC::DIR_PWR9) && EnableMachinePipeliner;
196 bool PPCSubtarget::useDFAforSMS() const { return false; }
198 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
199 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
201 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
202 return TargetSubtargetInfo::ANTIDEP_ALL;
205 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
206 CriticalPathRCs.clear();
207 CriticalPathRCs.push_back(isPPC64() ?
208 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
211 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
212 unsigned NumRegionInstrs) const {
213 // The GenericScheduler that we use defaults to scheduling bottom up only.
214 // We want to schedule from both the top and the bottom and so we set
215 // OnlyBottomUp to false.
216 // We want to do bi-directional scheduling since it provides a more balanced
217 // schedule leading to better performance.
218 Policy.OnlyBottomUp = false;
219 // Spilling is generally expensive on all PPC cores, so always enable
220 // register-pressure tracking.
221 Policy.ShouldTrackPressure = true;
224 bool PPCSubtarget::useAA() const {
228 bool PPCSubtarget::enableSubRegLiveness() const {
229 return UseSubRegLiveness;
233 PPCSubtarget::classifyGlobalReference(const GlobalValue *GV) const {
234 // Note that currently we don't generate non-pic references.
235 // If a caller wants that, this will have to be updated.
237 // Large code model always uses the TOC even for local symbols.
238 if (TM.getCodeModel() == CodeModel::Large)
239 return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG;
241 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
242 return PPCII::MO_PIC_FLAG;
243 return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG;
246 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
247 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }