1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
16 #include "PPCFrameLowering.h"
17 #include "PPCISelLowering.h"
18 #include "PPCInstrInfo.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
26 #define GET_SUBTARGETINFO_HEADER
27 #include "PPCGenSubtargetInfo.inc"
29 // GCC #defines PPC on Linux but we use it as our namespace name
36 // -m directive values.
68 class PPCSubtarget : public PPCGenSubtargetInfo {
77 /// TargetTriple - What processor and OS we're targeting.
80 /// stackAlignment - The minimum alignment known to hold of the stack frame on
81 /// entry to the function and which must be maintained by every function.
84 /// Selected instruction itineraries (one entry per itinerary class.)
85 InstrItineraryData InstrItins;
87 /// Which cpu directive was used.
88 unsigned CPUDirective;
90 /// Used by the ISel to turn in optimizations for POWER4-derived architectures
102 bool NeedsTwoConstNR;
109 bool HasPrefixInstrs;
110 bool HasPCRelativeMemops;
113 bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
130 bool AllowsUnalignedFPAccess;
134 bool HasInvariantFunctionDescriptors;
135 bool HasPartwordAtomics;
140 bool HasAddiLoadFusion;
141 bool HasAddisLoadFusion;
146 bool VectorsUseTwoUnits;
147 bool UsePPCPreRASchedStrategy;
148 bool UsePPCPostRASchedStrategy;
149 bool PredictableSelectIsExpensive;
151 POPCNTDKind HasPOPCNTD;
153 /// When targeting QPX running a stock PPC64 Linux kernel where the stack
154 /// alignment has not been changed, we need to keep the 16-byte alignment
156 bool IsQPXStackUnaligned;
158 const PPCTargetMachine &TM;
159 PPCFrameLowering FrameLowering;
160 PPCInstrInfo InstrInfo;
161 PPCTargetLowering TLInfo;
162 SelectionDAGTargetInfo TSInfo;
165 /// This constructor initializes the data members to match that
166 /// of the specified triple.
168 PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
169 const PPCTargetMachine &TM);
171 /// ParseSubtargetFeatures - Parses features string setting specified
172 /// subtarget options. Definition of function is auto generated by tblgen.
173 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
175 /// getStackAlignment - Returns the minimum alignment known to hold of the
176 /// stack frame on entry to the function and which must be maintained by every
177 /// function for this subtarget.
178 Align getStackAlignment() const { return StackAlignment; }
180 /// getDarwinDirective - Returns the -m directive specified for the cpu.
181 unsigned getDarwinDirective() const { return CPUDirective; }
183 /// getCPUDirective - Returns the -m directive specified for the cpu.
185 unsigned getCPUDirective() const { return CPUDirective; }
187 /// getInstrItins - Return the instruction itineraries based on subtarget
189 const InstrItineraryData *getInstrItineraryData() const override {
193 const PPCFrameLowering *getFrameLowering() const override {
194 return &FrameLowering;
196 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
197 const PPCTargetLowering *getTargetLowering() const override {
200 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
203 const PPCRegisterInfo *getRegisterInfo() const override {
204 return &getInstrInfo()->getRegisterInfo();
206 const PPCTargetMachine &getTargetMachine() const { return TM; }
208 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
209 /// so that we can use initializer lists for subtarget initialization.
210 PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
213 void initializeEnvironment();
214 void initSubtargetFeatures(StringRef CPU, StringRef FS);
217 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
219 bool isPPC64() const;
221 /// has64BitSupport - Return true if the selected CPU supports 64-bit
222 /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
223 bool has64BitSupport() const { return Has64BitSupport; }
224 // useSoftFloat - Return true if soft-float option is turned on.
225 bool useSoftFloat() const {
226 if (isAIXABI() && !HasHardFloat)
227 report_fatal_error("soft-float is not yet supported on AIX.");
228 return !HasHardFloat;
231 /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
232 /// registers in 32-bit mode when possible. This can only true if
233 /// has64BitSupport() returns true.
234 bool use64BitRegs() const { return Use64BitRegs; }
236 /// useCRBits - Return true if we should store and manipulate i1 values in
237 /// the individual condition register bits.
238 bool useCRBits() const { return UseCRBits; }
240 // isLittleEndian - True if generating little-endian code
241 bool isLittleEndian() const { return IsLittleEndian; }
243 // Specific obvious features.
244 bool hasFCPSGN() const { return HasFCPSGN; }
245 bool hasFSQRT() const { return HasFSQRT; }
246 bool hasFRE() const { return HasFRE; }
247 bool hasFRES() const { return HasFRES; }
248 bool hasFRSQRTE() const { return HasFRSQRTE; }
249 bool hasFRSQRTES() const { return HasFRSQRTES; }
250 bool hasRecipPrec() const { return HasRecipPrec; }
251 bool hasSTFIWX() const { return HasSTFIWX; }
252 bool hasLFIWAX() const { return HasLFIWAX; }
253 bool hasFPRND() const { return HasFPRND; }
254 bool hasFPCVT() const { return HasFPCVT; }
255 bool hasAltivec() const { return HasAltivec; }
256 bool hasSPE() const { return HasSPE; }
257 bool hasFPU() const { return HasFPU; }
258 bool hasQPX() const { return HasQPX; }
259 bool hasVSX() const { return HasVSX; }
260 bool needsTwoConstNR() const { return NeedsTwoConstNR; }
261 bool hasP8Vector() const { return HasP8Vector; }
262 bool hasP8Altivec() const { return HasP8Altivec; }
263 bool hasP8Crypto() const { return HasP8Crypto; }
264 bool hasP9Vector() const { return HasP9Vector; }
265 bool hasP9Altivec() const { return HasP9Altivec; }
266 bool hasP10Vector() const { return HasP10Vector; }
267 bool hasPrefixInstrs() const { return HasPrefixInstrs; }
268 bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
269 bool hasMFOCRF() const { return HasMFOCRF; }
270 bool hasISEL() const { return HasISEL; }
271 bool hasBPERMD() const { return HasBPERMD; }
272 bool hasExtDiv() const { return HasExtDiv; }
273 bool hasCMPB() const { return HasCMPB; }
274 bool hasLDBRX() const { return HasLDBRX; }
275 bool isBookE() const { return IsBookE; }
276 bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
277 bool isPPC4xx() const { return IsPPC4xx; }
278 bool isPPC6xx() const { return IsPPC6xx; }
279 bool isSecurePlt() const {return SecurePlt; }
280 bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; }
281 bool isE500() const { return IsE500; }
282 bool isFeatureMFTB() const { return FeatureMFTB; }
283 bool allowsUnalignedFPAccess() const { return AllowsUnalignedFPAccess; }
284 bool isDeprecatedDST() const { return DeprecatedDST; }
285 bool hasICBT() const { return HasICBT; }
286 bool hasInvariantFunctionDescriptors() const {
287 return HasInvariantFunctionDescriptors;
289 bool usePPCPreRASchedStrategy() const { return UsePPCPreRASchedStrategy; }
290 bool usePPCPostRASchedStrategy() const { return UsePPCPostRASchedStrategy; }
291 bool hasPartwordAtomics() const { return HasPartwordAtomics; }
292 bool hasDirectMove() const { return HasDirectMove; }
294 bool isQPXStackUnaligned() const { return IsQPXStackUnaligned; }
295 Align getPlatformStackAlignment() const {
296 if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned())
302 unsigned getRedZoneSize() const {
304 // 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
307 // AIX PPC32: 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
308 // PPC32 SVR4ABI has no redzone.
309 return isAIXABI() ? 220 : 0;
312 bool hasHTM() const { return HasHTM; }
313 bool hasFloat128() const { return HasFloat128; }
314 bool isISA3_0() const { return IsISA3_0; }
315 bool isISA3_1() const { return IsISA3_1; }
316 bool useLongCalls() const { return UseLongCalls; }
317 bool hasFusion() const { return HasFusion; }
318 bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
319 bool hasAddisLoadFusion() const { return HasAddisLoadFusion; }
320 bool needsSwapsForVSXMemOps() const {
321 return hasVSX() && isLittleEndian() && !hasP9Vector();
324 POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
326 const Triple &getTargetTriple() const { return TargetTriple; }
328 /// isBGQ - True if this is a BG/Q platform.
329 bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
331 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
332 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
333 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
335 bool isAIXABI() const { return TargetTriple.isOSAIX(); }
336 bool isSVR4ABI() const { return !isAIXABI(); }
337 bool isELFv2ABI() const;
339 bool is64BitELFABI() const { return isSVR4ABI() && isPPC64(); }
340 bool is32BitELFABI() const { return isSVR4ABI() && !isPPC64(); }
341 bool isUsingPCRelativeCalls() const;
343 /// Originally, this function return hasISEL(). Now we always enable it,
344 /// but may expand the ISEL instruction later.
345 bool enableEarlyIfConversion() const override { return true; }
347 /// Scheduling customization.
348 bool enableMachineScheduler() const override;
349 /// Pipeliner customization.
350 bool enableMachinePipeliner() const override;
351 /// Machine Pipeliner customization
352 bool useDFAforSMS() const override;
353 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
354 bool enablePostRAScheduler() const override;
355 AntiDepBreakMode getAntiDepBreakMode() const override;
356 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
358 void overrideSchedPolicy(MachineSchedPolicy &Policy,
359 unsigned NumRegionInstrs) const override;
360 bool useAA() const override;
362 bool enableSubRegLiveness() const override;
364 /// True if the GV will be accessed via an indirect symbol.
365 bool isGVIndirectSymbol(const GlobalValue *GV) const;
367 /// True if the ABI is descriptor based.
368 bool usesFunctionDescriptors() const {
369 // Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
370 // v1 ABI uses descriptors.
371 return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
374 unsigned descriptorTOCAnchorOffset() const {
375 assert(usesFunctionDescriptors() &&
376 "Should only be called when the target uses descriptors.");
377 return IsPPC64 ? 8 : 4;
380 unsigned descriptorEnvironmentPointerOffset() const {
381 assert(usesFunctionDescriptors() &&
382 "Should only be called when the target uses descriptors.");
383 return IsPPC64 ? 16 : 8;
386 MCRegister getEnvironmentPointerRegister() const {
387 assert(usesFunctionDescriptors() &&
388 "Should only be called when the target uses descriptors.");
389 return IsPPC64 ? PPC::X11 : PPC::R11;
392 MCRegister getTOCPointerRegister() const {
393 assert((is64BitELFABI() || isAIXABI()) &&
394 "Should only be called when the target is a TOC based ABI.");
395 return IsPPC64 ? PPC::X2 : PPC::R2;
398 MCRegister getStackPointerRegister() const {
399 return IsPPC64 ? PPC::X1 : PPC::R1;
402 bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
404 bool isPredictableSelectIsExpensive() const {
405 return PredictableSelectIsExpensive;
408 } // End llvm namespace