1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Top-level implementation for the PowerPC target.
11 //===----------------------------------------------------------------------===//
13 #include "PPCTargetMachine.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "PPCMachineScheduler.h"
17 #include "PPCSubtarget.h"
18 #include "PPCTargetObjectFile.h"
19 #include "PPCTargetTransformInfo.h"
20 #include "TargetInfo/PowerPCTargetInfo.h"
21 #include "llvm/ADT/Optional.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/Triple.h"
25 #include "llvm/Analysis/TargetTransformInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/TargetPassConfig.h"
28 #include "llvm/CodeGen/MachineScheduler.h"
29 #include "llvm/IR/Attributes.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/Pass.h"
33 #include "llvm/Support/CodeGen.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/TargetRegistry.h"
36 #include "llvm/Target/TargetLoweringObjectFile.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Transforms/Scalar.h"
47 EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
48 cl::desc("enable coalescing of duplicate branches for PPC"));
50 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
51 cl::desc("Disable CTR loops for PPC"));
54 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
55 cl::desc("Disable PPC loop preinc prep"));
58 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
59 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
62 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
63 cl::desc("Disable VSX Swap Removal for PPC"));
66 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
67 cl::desc("Disable QPX load splat simplification"));
70 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
71 cl::desc("Disable machine peepholes for PPC"));
74 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
75 cl::desc("Enable optimizations on complex GEPs"),
79 EnablePrefetch("enable-ppc-prefetching",
80 cl::desc("disable software prefetching on PPC"),
81 cl::init(false), cl::Hidden);
84 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
85 cl::desc("Add extra TOC register dependencies"),
86 cl::init(true), cl::Hidden);
89 EnableMachineCombinerPass("ppc-machine-combiner",
90 cl::desc("Enable the machine combiner pass"),
91 cl::init(true), cl::Hidden);
94 ReduceCRLogical("ppc-reduce-cr-logicals",
95 cl::desc("Expand eligible cr-logical binary ops to branches"),
96 cl::init(false), cl::Hidden);
97 extern "C" void LLVMInitializePowerPCTarget() {
98 // Register the targets
99 RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
100 RegisterTargetMachine<PPCTargetMachine> B(getThePPC64Target());
101 RegisterTargetMachine<PPCTargetMachine> C(getThePPC64LETarget());
103 PassRegistry &PR = *PassRegistry::getPassRegistry();
105 initializePPCCTRLoopsVerifyPass(PR);
107 initializePPCLoopPreIncPrepPass(PR);
108 initializePPCTOCRegDepsPass(PR);
109 initializePPCEarlyReturnPass(PR);
110 initializePPCVSXCopyPass(PR);
111 initializePPCVSXFMAMutatePass(PR);
112 initializePPCVSXSwapRemovalPass(PR);
113 initializePPCReduceCRLogicalsPass(PR);
114 initializePPCBSelPass(PR);
115 initializePPCBranchCoalescingPass(PR);
116 initializePPCQPXLoadSplatPass(PR);
117 initializePPCBoolRetToIntPass(PR);
118 initializePPCExpandISELPass(PR);
119 initializePPCPreEmitPeepholePass(PR);
120 initializePPCTLSDynamicCallPass(PR);
121 initializePPCMIPeepholePass(PR);
124 /// Return the datalayout string of a subtarget.
125 static std::string getDataLayoutString(const Triple &T) {
126 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
129 // Most PPC* platforms are big endian, PPC64LE is little endian.
130 if (T.getArch() == Triple::ppc64le)
135 Ret += DataLayout::getManglingComponent(T);
137 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
139 if (!is64Bit || T.getOS() == Triple::Lv2)
142 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
143 // documentation are wrong; these are correct (i.e. "what gcc does").
144 if (is64Bit || !T.isOSDarwin())
149 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
158 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
160 std::string FullFS = FS;
162 // Make sure 64-bit features are available when CPUname is generic
163 if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
165 FullFS = "+64bit," + FullFS;
170 if (OL >= CodeGenOpt::Default) {
172 FullFS = "+crbits," + FullFS;
177 if (OL != CodeGenOpt::None) {
179 FullFS = "+invariant-function-descriptors," + FullFS;
181 FullFS = "+invariant-function-descriptors";
187 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
188 // If it isn't a Mach-O file then it's going to be a linux ELF
191 return llvm::make_unique<TargetLoweringObjectFileMachO>();
193 return llvm::make_unique<PPC64LinuxTargetObjectFile>();
196 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
197 const TargetOptions &Options) {
199 report_fatal_error("Darwin is no longer supported for PowerPC");
201 if (Options.MCOptions.getABIName().startswith("elfv1"))
202 return PPCTargetMachine::PPC_ABI_ELFv1;
203 else if (Options.MCOptions.getABIName().startswith("elfv2"))
204 return PPCTargetMachine::PPC_ABI_ELFv2;
206 assert(Options.MCOptions.getABIName().empty() &&
207 "Unknown target-abi option!");
210 return PPCTargetMachine::PPC_ABI_UNKNOWN;
212 if (TT.isOSFreeBSD()) {
213 switch (TT.getArch()) {
214 case Triple::ppc64le:
216 if (TT.getOSMajorVersion() >= 13)
217 return PPCTargetMachine::PPC_ABI_ELFv2;
219 return PPCTargetMachine::PPC_ABI_ELFv1;
222 return PPCTargetMachine::PPC_ABI_UNKNOWN;
226 switch (TT.getArch()) {
227 case Triple::ppc64le:
228 return PPCTargetMachine::PPC_ABI_ELFv2;
230 if (TT.getEnvironment() == llvm::Triple::ELFv2)
231 return PPCTargetMachine::PPC_ABI_ELFv2;
232 return PPCTargetMachine::PPC_ABI_ELFv1;
234 return PPCTargetMachine::PPC_ABI_UNKNOWN;
238 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
239 Optional<Reloc::Model> RM) {
243 // Darwin defaults to dynamic-no-pic.
245 return Reloc::DynamicNoPIC;
247 // Big Endian PPC is PIC by default.
248 if (TT.getArch() == Triple::ppc64)
251 // Rest are static by default.
252 return Reloc::Static;
255 static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT,
256 Optional<CodeModel::Model> CM,
259 if (*CM == CodeModel::Tiny)
260 report_fatal_error("Target does not support the tiny CodeModel", false);
261 if (*CM == CodeModel::Kernel)
262 report_fatal_error("Target does not support the kernel CodeModel", false);
265 if (!TT.isOSDarwin() && !JIT &&
266 (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
267 return CodeModel::Medium;
268 return CodeModel::Small;
272 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
273 const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
274 ScheduleDAGMILive *DAG =
275 new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
276 llvm::make_unique<PPCPreRASchedStrategy>(C) :
277 llvm::make_unique<GenericScheduler>(C));
278 // add DAG Mutations here.
279 DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
283 static ScheduleDAGInstrs *createPPCPostMachineScheduler(
284 MachineSchedContext *C) {
285 const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
287 new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
288 llvm::make_unique<PPCPostRASchedStrategy>(C) :
289 llvm::make_unique<PostGenericScheduler>(C), true);
290 // add DAG Mutations here.
294 // The FeatureString here is a little subtle. We are modifying the feature
295 // string with what are (currently) non-function specific overrides as it goes
296 // into the LLVMTargetMachine constructor and then using the stored value in the
297 // Subtarget constructor below it.
298 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
299 StringRef CPU, StringRef FS,
300 const TargetOptions &Options,
301 Optional<Reloc::Model> RM,
302 Optional<CodeModel::Model> CM,
303 CodeGenOpt::Level OL, bool JIT)
304 : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
305 computeFSAdditions(FS, OL, TT), Options,
306 getEffectiveRelocModel(TT, RM),
307 getEffectivePPCCodeModel(TT, CM, JIT), OL),
308 TLOF(createTLOF(getTargetTriple())),
309 TargetABI(computeTargetABI(TT, Options)) {
313 PPCTargetMachine::~PPCTargetMachine() = default;
316 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
317 Attribute CPUAttr = F.getFnAttribute("target-cpu");
318 Attribute FSAttr = F.getFnAttribute("target-features");
320 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
321 ? CPUAttr.getValueAsString().str()
323 std::string FS = !FSAttr.hasAttribute(Attribute::None)
324 ? FSAttr.getValueAsString().str()
327 // FIXME: This is related to the code below to reset the target options,
328 // we need to know whether or not the soft float flag is set on the
329 // function before we can generate a subtarget. We also need to use
330 // it as a key for the subtarget since that can be the only difference
331 // between two functions.
333 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
334 // If the soft float attribute is set on the function turn on the soft float
335 // subtarget feature.
337 FS += FS.empty() ? "-hard-float" : ",-hard-float";
339 auto &I = SubtargetMap[CPU + FS];
341 // This needs to be done before we create a new subtarget since any
342 // creation will depend on the TM and the code generation flags on the
343 // function that reside in TargetOptions.
344 resetTargetOptions(F);
345 I = llvm::make_unique<PPCSubtarget>(
347 // FIXME: It would be good to have the subtarget additions here
348 // not necessary. Anything that turns them on/off (overrides) ends
349 // up being put at the end of the feature string, but the defaults
350 // shouldn't require adding them. Fixing this means pulling Feature64Bit
351 // out of most of the target cpus in the .td file and making it set only
352 // as part of initialization via the TargetTriple.
353 computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
358 //===----------------------------------------------------------------------===//
359 // Pass Pipeline Configuration
360 //===----------------------------------------------------------------------===//
364 /// PPC Code Generator Pass Configuration Options.
365 class PPCPassConfig : public TargetPassConfig {
367 PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
368 : TargetPassConfig(TM, PM) {
369 // At any optimization level above -O0 we use the Machine Scheduler and not
370 // the default Post RA List Scheduler.
371 if (TM.getOptLevel() != CodeGenOpt::None)
372 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
375 PPCTargetMachine &getPPCTargetMachine() const {
376 return getTM<PPCTargetMachine>();
379 void addIRPasses() override;
380 bool addPreISel() override;
381 bool addILPOpts() override;
382 bool addInstSelector() override;
383 void addMachineSSAOptimization() override;
384 void addPreRegAlloc() override;
385 void addPreSched2() override;
386 void addPreEmitPass() override;
388 createMachineScheduler(MachineSchedContext *C) const override {
389 return createPPCMachineScheduler(C);
392 createPostMachineScheduler(MachineSchedContext *C) const override {
393 return createPPCPostMachineScheduler(C);
397 } // end anonymous namespace
399 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
400 return new PPCPassConfig(*this, PM);
403 void PPCPassConfig::addIRPasses() {
404 if (TM->getOptLevel() != CodeGenOpt::None)
405 addPass(createPPCBoolRetToIntPass());
406 addPass(createAtomicExpandPass());
408 // For the BG/Q (or if explicitly requested), add explicit data prefetch
410 bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
411 getOptLevel() != CodeGenOpt::None;
412 if (EnablePrefetch.getNumOccurrences() > 0)
413 UsePrefetching = EnablePrefetch;
415 addPass(createLoopDataPrefetchPass());
417 if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
418 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
419 // and lower a GEP with multiple indices to either arithmetic operations or
420 // multiple GEPs with single index.
421 addPass(createSeparateConstOffsetFromGEPPass(true));
422 // Call EarlyCSE pass to find and remove subexpressions in the lowered
424 addPass(createEarlyCSEPass());
425 // Do loop invariant code motion in case part of the lowered result is
427 addPass(createLICMPass());
430 TargetPassConfig::addIRPasses();
433 bool PPCPassConfig::addPreISel() {
434 if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
435 addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
437 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
438 addPass(createHardwareLoopsPass());
443 bool PPCPassConfig::addILPOpts() {
444 addPass(&EarlyIfConverterID);
446 if (EnableMachineCombinerPass)
447 addPass(&MachineCombinerID);
452 bool PPCPassConfig::addInstSelector() {
453 // Install an instruction selector.
454 addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
457 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
458 addPass(createPPCCTRLoopsVerify());
461 addPass(createPPCVSXCopyPass());
465 void PPCPassConfig::addMachineSSAOptimization() {
466 // PPCBranchCoalescingPass need to be done before machine sinking
467 // since it merges empty blocks.
468 if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
469 addPass(createPPCBranchCoalescingPass());
470 TargetPassConfig::addMachineSSAOptimization();
471 // For little endian, remove where possible the vector swap instructions
472 // introduced at code generation to normalize vector element order.
473 if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
474 !DisableVSXSwapRemoval)
475 addPass(createPPCVSXSwapRemovalPass());
476 // Reduce the number of cr-logical ops.
477 if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
478 addPass(createPPCReduceCRLogicalsPass());
479 // Target-specific peephole cleanups performed after instruction
481 if (!DisableMIPeephole) {
482 addPass(createPPCMIPeepholePass());
483 addPass(&DeadMachineInstructionElimID);
487 void PPCPassConfig::addPreRegAlloc() {
488 if (getOptLevel() != CodeGenOpt::None) {
489 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
490 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
494 // FIXME: We probably don't need to run these for -fPIE.
495 if (getPPCTargetMachine().isPositionIndependent()) {
496 // FIXME: LiveVariables should not be necessary here!
497 // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
498 // LiveVariables. This (unnecessary) dependency has been removed now,
499 // however a stage-2 clang build fails without LiveVariables computed here.
500 addPass(&LiveVariablesID, false);
501 addPass(createPPCTLSDynamicCallPass());
503 if (EnableExtraTOCRegDeps)
504 addPass(createPPCTOCRegDepsPass());
506 if (getOptLevel() != CodeGenOpt::None)
507 addPass(&MachinePipelinerID);
510 void PPCPassConfig::addPreSched2() {
511 if (getOptLevel() != CodeGenOpt::None) {
512 addPass(&IfConverterID);
514 // This optimization must happen after anything that might do store-to-load
515 // forwarding. Here we're after RA (and, thus, when spills are inserted)
516 // but before post-RA scheduling.
517 if (!DisableQPXLoadSplat)
518 addPass(createPPCQPXLoadSplatPass());
522 void PPCPassConfig::addPreEmitPass() {
523 addPass(createPPCPreEmitPeepholePass());
524 addPass(createPPCExpandISELPass());
526 if (getOptLevel() != CodeGenOpt::None)
527 addPass(createPPCEarlyReturnPass(), false);
528 // Must run branch selection immediately preceding the asm printer.
529 addPass(createPPCBranchSelectionPass(), false);
533 PPCTargetMachine::getTargetTransformInfo(const Function &F) {
534 return TargetTransformInfo(PPCTTIImpl(this, F));
537 static MachineSchedRegistry
538 PPCPreRASchedRegistry("ppc-prera",
539 "Run PowerPC PreRA specific scheduler",
540 createPPCMachineScheduler);
542 static MachineSchedRegistry
543 PPCPostRASchedRegistry("ppc-postra",
544 "Run PowerPC PostRA specific scheduler",
545 createPPCPostMachineScheduler);