1 //===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements the RISCVDisassembler class.
11 //===----------------------------------------------------------------------===//
13 #include "MCTargetDesc/RISCVMCTargetDesc.h"
14 #include "TargetInfo/RISCVTargetInfo.h"
15 #include "Utils/RISCVBaseInfo.h"
16 #include "llvm/CodeGen/Register.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/Support/Endian.h"
24 #include "llvm/Support/TargetRegistry.h"
28 #define DEBUG_TYPE "riscv-disassembler"
30 typedef MCDisassembler::DecodeStatus DecodeStatus;
33 class RISCVDisassembler : public MCDisassembler {
36 RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
37 : MCDisassembler(STI, Ctx) {}
39 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
40 ArrayRef<uint8_t> Bytes, uint64_t Address,
41 raw_ostream &CStream) const override;
43 } // end anonymous namespace
45 static MCDisassembler *createRISCVDisassembler(const Target &T,
46 const MCSubtargetInfo &STI,
48 return new RISCVDisassembler(STI, Ctx);
51 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
52 // Register the disassembler for each target.
53 TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
54 createRISCVDisassembler);
55 TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
56 createRISCVDisassembler);
59 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
61 const void *Decoder) {
62 const FeatureBitset &FeatureBits =
63 static_cast<const MCDisassembler *>(Decoder)
66 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
68 if (RegNo >= 32 || (IsRV32E && RegNo >= 16))
69 return MCDisassembler::Fail;
71 Register Reg = RISCV::X0 + RegNo;
72 Inst.addOperand(MCOperand::createReg(Reg));
73 return MCDisassembler::Success;
76 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
78 const void *Decoder) {
80 return MCDisassembler::Fail;
82 Register Reg = RISCV::F0_F + RegNo;
83 Inst.addOperand(MCOperand::createReg(Reg));
84 return MCDisassembler::Success;
87 static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo,
89 const void *Decoder) {
91 return MCDisassembler::Fail;
93 Register Reg = RISCV::F8_F + RegNo;
94 Inst.addOperand(MCOperand::createReg(Reg));
95 return MCDisassembler::Success;
98 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
100 const void *Decoder) {
102 return MCDisassembler::Fail;
104 Register Reg = RISCV::F0_D + RegNo;
105 Inst.addOperand(MCOperand::createReg(Reg));
106 return MCDisassembler::Success;
109 static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo,
111 const void *Decoder) {
113 return MCDisassembler::Fail;
115 Register Reg = RISCV::F8_D + RegNo;
116 Inst.addOperand(MCOperand::createReg(Reg));
117 return MCDisassembler::Success;
120 static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo,
122 const void *Decoder) {
124 return MCDisassembler::Fail;
127 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
130 static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo,
132 const void *Decoder) {
134 return MCDisassembler::Fail;
137 return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
140 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
142 const void *Decoder) {
144 return MCDisassembler::Fail;
146 Register Reg = RISCV::X8 + RegNo;
147 Inst.addOperand(MCOperand::createReg(Reg));
148 return MCDisassembler::Success;
151 // Add implied SP operand for instructions *SP compressed instructions. The SP
152 // operand isn't explicitly encoded in the instruction.
153 static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {
154 if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
155 Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
156 Inst.getOpcode() == RISCV::C_FLWSP ||
157 Inst.getOpcode() == RISCV::C_FSWSP ||
158 Inst.getOpcode() == RISCV::C_FLDSP ||
159 Inst.getOpcode() == RISCV::C_FSDSP ||
160 Inst.getOpcode() == RISCV::C_ADDI4SPN) {
161 DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
163 if (Inst.getOpcode() == RISCV::C_ADDI16SP) {
164 DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
165 DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
169 template <unsigned N>
170 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
171 int64_t Address, const void *Decoder) {
172 assert(isUInt<N>(Imm) && "Invalid immediate");
173 addImplySP(Inst, Address, Decoder);
174 Inst.addOperand(MCOperand::createImm(Imm));
175 return MCDisassembler::Success;
178 template <unsigned N>
179 static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
181 const void *Decoder) {
183 return MCDisassembler::Fail;
184 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
187 template <unsigned N>
188 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
189 int64_t Address, const void *Decoder) {
190 assert(isUInt<N>(Imm) && "Invalid immediate");
191 addImplySP(Inst, Address, Decoder);
192 // Sign-extend the number in the bottom N bits of Imm
193 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
194 return MCDisassembler::Success;
197 template <unsigned N>
198 static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
200 const void *Decoder) {
202 return MCDisassembler::Fail;
203 return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
206 template <unsigned N>
207 static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm,
209 const void *Decoder) {
210 assert(isUInt<N>(Imm) && "Invalid immediate");
211 // Sign-extend the number in the bottom N bits of Imm after accounting for
212 // the fact that the N bit immediate is stored in N-1 bits (the LSB is
214 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
215 return MCDisassembler::Success;
218 static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm,
220 const void *Decoder) {
221 assert(isUInt<6>(Imm) && "Invalid immediate");
223 Imm = (SignExtend64<6>(Imm) & 0xfffff);
225 Inst.addOperand(MCOperand::createImm(Imm));
226 return MCDisassembler::Success;
229 static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm,
231 const void *Decoder) {
232 assert(isUInt<3>(Imm) && "Invalid immediate");
233 if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
234 return MCDisassembler::Fail;
236 Inst.addOperand(MCOperand::createImm(Imm));
237 return MCDisassembler::Success;
240 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
241 uint64_t Address, const void *Decoder);
243 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
244 uint64_t Address, const void *Decoder);
246 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
248 const void *Decoder);
250 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
251 uint64_t Address, const void *Decoder);
253 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
255 const void *Decoder);
257 #include "RISCVGenDisassemblerTables.inc"
259 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
260 uint64_t Address, const void *Decoder) {
262 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
263 DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
265 assert(Result == MCDisassembler::Success && "Invalid immediate");
266 return MCDisassembler::Success;
269 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
271 const void *Decoder) {
272 DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
274 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
275 DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
277 assert(Result == MCDisassembler::Success && "Invalid immediate");
278 return MCDisassembler::Success;
281 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
283 const void *Decoder) {
284 DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
285 Inst.addOperand(Inst.getOperand(0));
287 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
288 DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
290 assert(Result == MCDisassembler::Success && "Invalid immediate");
291 return MCDisassembler::Success;
294 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder) {
296 unsigned Rd = fieldFromInstruction(Insn, 7, 5);
297 unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
298 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
299 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
300 return MCDisassembler::Success;
303 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
305 const void *Decoder) {
306 unsigned Rd = fieldFromInstruction(Insn, 7, 5);
307 unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
308 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
309 Inst.addOperand(Inst.getOperand(0));
310 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
311 return MCDisassembler::Success;
314 DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
315 ArrayRef<uint8_t> Bytes,
317 raw_ostream &CS) const {
318 // TODO: This will need modification when supporting instruction set
319 // extensions with instructions > 32-bits (up to 176 bits wide).
323 // It's a 32 bit instruction if bit 0 and 1 are 1.
324 if ((Bytes[0] & 0x3) == 0x3) {
325 if (Bytes.size() < 4) {
327 return MCDisassembler::Fail;
329 Insn = support::endian::read32le(Bytes.data());
330 LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
331 Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
334 if (Bytes.size() < 2) {
336 return MCDisassembler::Fail;
338 Insn = support::endian::read16le(Bytes.data());
340 if (!STI.getFeatureBits()[RISCV::Feature64Bit]) {
342 dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n");
343 // Calling the auto-generated decoder function.
344 Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address,
346 if (Result != MCDisassembler::Fail) {
352 LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n");
353 // Calling the auto-generated decoder function.
354 Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);