1 //===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements the RISCVDisassembler class.
11 //===----------------------------------------------------------------------===//
13 #include "MCTargetDesc/RISCVMCTargetDesc.h"
14 #include "TargetInfo/RISCVTargetInfo.h"
15 #include "Utils/RISCVBaseInfo.h"
16 #include "llvm/CodeGen/Register.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/Endian.h"
25 #include "llvm/Support/TargetRegistry.h"
29 #define DEBUG_TYPE "riscv-disassembler"
31 typedef MCDisassembler::DecodeStatus DecodeStatus;
34 class RISCVDisassembler : public MCDisassembler {
35 std::unique_ptr<MCInstrInfo const> const MCII;
38 RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
39 MCInstrInfo const *MCII)
40 : MCDisassembler(STI, Ctx), MCII(MCII) {}
42 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
43 ArrayRef<uint8_t> Bytes, uint64_t Address,
44 raw_ostream &CStream) const override;
46 } // end anonymous namespace
48 static MCDisassembler *createRISCVDisassembler(const Target &T,
49 const MCSubtargetInfo &STI,
51 return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
54 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
55 // Register the disassembler for each target.
56 TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
57 createRISCVDisassembler);
58 TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
59 createRISCVDisassembler);
62 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
64 const void *Decoder) {
65 const FeatureBitset &FeatureBits =
66 static_cast<const MCDisassembler *>(Decoder)
69 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
71 if (RegNo >= 32 || (IsRV32E && RegNo >= 16))
72 return MCDisassembler::Fail;
74 Register Reg = RISCV::X0 + RegNo;
75 Inst.addOperand(MCOperand::createReg(Reg));
76 return MCDisassembler::Success;
79 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
81 const void *Decoder) {
83 return MCDisassembler::Fail;
85 Register Reg = RISCV::F0_F + RegNo;
86 Inst.addOperand(MCOperand::createReg(Reg));
87 return MCDisassembler::Success;
90 static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo,
92 const void *Decoder) {
94 return MCDisassembler::Fail;
96 Register Reg = RISCV::F8_F + RegNo;
97 Inst.addOperand(MCOperand::createReg(Reg));
98 return MCDisassembler::Success;
101 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
103 const void *Decoder) {
105 return MCDisassembler::Fail;
107 Register Reg = RISCV::F0_D + RegNo;
108 Inst.addOperand(MCOperand::createReg(Reg));
109 return MCDisassembler::Success;
112 static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo,
114 const void *Decoder) {
116 return MCDisassembler::Fail;
118 Register Reg = RISCV::F8_D + RegNo;
119 Inst.addOperand(MCOperand::createReg(Reg));
120 return MCDisassembler::Success;
123 static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo,
125 const void *Decoder) {
127 return MCDisassembler::Fail;
130 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
133 static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo,
135 const void *Decoder) {
137 return MCDisassembler::Fail;
140 return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
143 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
145 const void *Decoder) {
147 return MCDisassembler::Fail;
149 Register Reg = RISCV::X8 + RegNo;
150 Inst.addOperand(MCOperand::createReg(Reg));
151 return MCDisassembler::Success;
154 static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo,
156 const void *Decoder) {
158 return MCDisassembler::Fail;
160 Register Reg = RISCV::V0 + RegNo;
161 Inst.addOperand(MCOperand::createReg(Reg));
162 return MCDisassembler::Success;
165 static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo,
166 uint64_t Address, const void *Decoder) {
167 Register Reg = RISCV::NoRegister;
170 return MCDisassembler::Fail;
177 Inst.addOperand(MCOperand::createReg(Reg));
178 return MCDisassembler::Success;
181 // Add implied SP operand for instructions *SP compressed instructions. The SP
182 // operand isn't explicitly encoded in the instruction.
183 static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {
184 if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
185 Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
186 Inst.getOpcode() == RISCV::C_FLWSP ||
187 Inst.getOpcode() == RISCV::C_FSWSP ||
188 Inst.getOpcode() == RISCV::C_FLDSP ||
189 Inst.getOpcode() == RISCV::C_FSDSP ||
190 Inst.getOpcode() == RISCV::C_ADDI4SPN) {
191 DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
193 if (Inst.getOpcode() == RISCV::C_ADDI16SP) {
194 DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
195 DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
199 template <unsigned N>
200 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
201 int64_t Address, const void *Decoder) {
202 assert(isUInt<N>(Imm) && "Invalid immediate");
203 addImplySP(Inst, Address, Decoder);
204 Inst.addOperand(MCOperand::createImm(Imm));
205 return MCDisassembler::Success;
208 template <unsigned N>
209 static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
211 const void *Decoder) {
213 return MCDisassembler::Fail;
214 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
217 template <unsigned N>
218 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
219 int64_t Address, const void *Decoder) {
220 assert(isUInt<N>(Imm) && "Invalid immediate");
221 addImplySP(Inst, Address, Decoder);
222 // Sign-extend the number in the bottom N bits of Imm
223 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
224 return MCDisassembler::Success;
227 template <unsigned N>
228 static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
230 const void *Decoder) {
232 return MCDisassembler::Fail;
233 return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
236 template <unsigned N>
237 static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm,
239 const void *Decoder) {
240 assert(isUInt<N>(Imm) && "Invalid immediate");
241 // Sign-extend the number in the bottom N bits of Imm after accounting for
242 // the fact that the N bit immediate is stored in N-1 bits (the LSB is
244 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
245 return MCDisassembler::Success;
248 static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm,
250 const void *Decoder) {
251 assert(isUInt<6>(Imm) && "Invalid immediate");
253 Imm = (SignExtend64<6>(Imm) & 0xfffff);
255 Inst.addOperand(MCOperand::createImm(Imm));
256 return MCDisassembler::Success;
259 static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm,
261 const void *Decoder) {
262 assert(isUInt<3>(Imm) && "Invalid immediate");
263 if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
264 return MCDisassembler::Fail;
266 Inst.addOperand(MCOperand::createImm(Imm));
267 return MCDisassembler::Success;
270 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
271 uint64_t Address, const void *Decoder);
273 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
274 uint64_t Address, const void *Decoder);
276 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
278 const void *Decoder);
280 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
283 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
285 const void *Decoder);
287 #include "RISCVGenDisassemblerTables.inc"
289 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
290 uint64_t Address, const void *Decoder) {
292 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
293 DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
295 assert(Result == MCDisassembler::Success && "Invalid immediate");
296 return MCDisassembler::Success;
299 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
301 const void *Decoder) {
302 DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
304 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
305 DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
307 assert(Result == MCDisassembler::Success && "Invalid immediate");
308 return MCDisassembler::Success;
311 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
313 const void *Decoder) {
314 DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
315 Inst.addOperand(Inst.getOperand(0));
317 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
318 DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
320 assert(Result == MCDisassembler::Success && "Invalid immediate");
321 return MCDisassembler::Success;
324 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
325 uint64_t Address, const void *Decoder) {
326 unsigned Rd = fieldFromInstruction(Insn, 7, 5);
327 unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
328 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
329 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
330 return MCDisassembler::Success;
333 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
335 const void *Decoder) {
336 unsigned Rd = fieldFromInstruction(Insn, 7, 5);
337 unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
338 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
339 Inst.addOperand(Inst.getOperand(0));
340 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
341 return MCDisassembler::Success;
344 DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
345 ArrayRef<uint8_t> Bytes,
347 raw_ostream &CS) const {
348 // TODO: This will need modification when supporting instruction set
349 // extensions with instructions > 32-bits (up to 176 bits wide).
353 // It's a 32 bit instruction if bit 0 and 1 are 1.
354 if ((Bytes[0] & 0x3) == 0x3) {
355 if (Bytes.size() < 4) {
357 return MCDisassembler::Fail;
359 Insn = support::endian::read32le(Bytes.data());
360 LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
361 Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
364 if (Bytes.size() < 2) {
366 return MCDisassembler::Fail;
368 Insn = support::endian::read16le(Bytes.data());
370 if (!STI.getFeatureBits()[RISCV::Feature64Bit]) {
372 dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n");
373 // Calling the auto-generated decoder function.
374 Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address,
376 if (Result != MCDisassembler::Fail) {
382 if (STI.getFeatureBits()[RISCV::FeatureExtZbproposedc] &&
383 STI.getFeatureBits()[RISCV::FeatureStdExtC]) {
385 dbgs() << "Trying RVBC32 table (BitManip 16-bit Instruction):\n");
386 // Calling the auto-generated decoder function.
387 Result = decodeInstruction(DecoderTableRVBC16, MI, Insn, Address,
389 if (Result != MCDisassembler::Fail) {
395 LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n");
396 // Calling the auto-generated decoder function.
397 Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);