1 //===-- RISCVInstPrinter.cpp - Convert RISCV MCInst to asm syntax ---------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This class prints an RISCV MCInst to a .s file.
11 //===----------------------------------------------------------------------===//
13 #include "RISCVInstPrinter.h"
14 #include "MCTargetDesc/RISCVMCExpr.h"
15 #include "Utils/RISCVBaseInfo.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/MC/MCSymbol.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/FormattedStream.h"
27 #define DEBUG_TYPE "asm-printer"
29 // Include the auto-generated portion of the assembly writer.
30 #define PRINT_ALIAS_INSTR
31 #include "RISCVGenAsmWriter.inc"
33 // Include the auto-generated portion of the compress emitter.
34 #define GEN_UNCOMPRESS_INSTR
35 #include "RISCVGenCompressInstEmitter.inc"
38 NoAliases("riscv-no-aliases",
39 cl::desc("Disable the emission of assembler pseudo instructions"),
40 cl::init(false), cl::Hidden);
42 void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
43 StringRef Annot, const MCSubtargetInfo &STI) {
45 const MCInst *NewMI = MI;
46 MCInst UncompressedMI;
48 Res = uncompressInst(UncompressedMI, *MI, MRI, STI);
50 NewMI = const_cast<MCInst *>(&UncompressedMI);
51 if (NoAliases || !printAliasInstr(NewMI, STI, O))
52 printInstruction(NewMI, STI, O);
53 printAnnotation(O, Annot);
56 void RISCVInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
57 O << getRegisterName(RegNo);
60 void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
61 const MCSubtargetInfo &STI, raw_ostream &O,
62 const char *Modifier) {
63 assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
64 const MCOperand &MO = MI->getOperand(OpNo);
67 printRegName(O, MO.getReg());
76 assert(MO.isExpr() && "Unknown operand kind in printOperand");
77 MO.getExpr()->print(O, &MAI);
80 void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
81 const MCSubtargetInfo &STI,
83 unsigned Imm = MI->getOperand(OpNo).getImm();
84 auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm);
85 if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits()))
91 void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
92 const MCSubtargetInfo &STI,
94 unsigned FenceArg = MI->getOperand(OpNo).getImm();
95 assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg");
97 if ((FenceArg & RISCVFenceField::I) != 0)
99 if ((FenceArg & RISCVFenceField::O) != 0)
101 if ((FenceArg & RISCVFenceField::R) != 0)
103 if ((FenceArg & RISCVFenceField::W) != 0)
109 void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
110 const MCSubtargetInfo &STI, raw_ostream &O) {
112 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm());
113 O << RISCVFPRndMode::roundingModeToString(FRMArg);
116 void RISCVInstPrinter::printAtomicMemOp(const MCInst *MI, unsigned OpNo,
117 const MCSubtargetInfo &STI,
119 const MCOperand &MO = MI->getOperand(OpNo);
121 assert(MO.isReg() && "printAtomicMemOp can only print register operands");
123 printRegName(O, MO.getReg());