contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp

   1 //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 ///
   9 /// This file provides RISCV-specific target descriptions.
  10 ///
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "RISCVMCTargetDesc.h"
  14 #include "RISCVELFStreamer.h"
  15 #include "RISCVInstPrinter.h"
  16 #include "RISCVMCAsmInfo.h"
  17 #include "RISCVTargetStreamer.h"
  18 #include "TargetInfo/RISCVTargetInfo.h"
  19 #include "llvm/ADT/STLExtras.h"
  20 #include "llvm/MC/MCAsmInfo.h"
  21 #include "llvm/MC/MCInstrInfo.h"
  22 #include "llvm/MC/MCRegisterInfo.h"
  23 #include "llvm/MC/MCStreamer.h"
  24 #include "llvm/MC/MCSubtargetInfo.h"
  25 #include "llvm/Support/ErrorHandling.h"
  26 #include "llvm/Support/TargetRegistry.h"
  27
  28 #define GET_INSTRINFO_MC_DESC
  29 #include "RISCVGenInstrInfo.inc"
  30
  31 #define GET_REGINFO_MC_DESC
  32 #include "RISCVGenRegisterInfo.inc"
  33
  34 #define GET_SUBTARGETINFO_MC_DESC
  35 #include "RISCVGenSubtargetInfo.inc"
  36
  37 using namespace llvm;
  38
  39 static MCInstrInfo *createRISCVMCInstrInfo() {
  40   MCInstrInfo *X = new MCInstrInfo();
  41   InitRISCVMCInstrInfo(X);
  42   return X;
  43 }
  44
  45 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
  46   MCRegisterInfo *X = new MCRegisterInfo();
  47   InitRISCVMCRegisterInfo(X, RISCV::X1);
  48   return X;
  49 }
  50
  51 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
  52                                        const Triple &TT) {
  53   MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
  54
  55   unsigned SP = MRI.getDwarfRegNum(RISCV::X2, true);
  56   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
  57   MAI->addInitialFrameState(Inst);
  58
  59   return MAI;
  60 }
  61
  62 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
  63                                                    StringRef CPU, StringRef FS) {
  64   std::string CPUName = CPU;
  65   if (CPUName.empty())
  66     CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
  67   return createRISCVMCSubtargetInfoImpl(TT, CPUName, FS);
  68 }
  69
  70 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
  71                                                unsigned SyntaxVariant,
  72                                                const MCAsmInfo &MAI,
  73                                                const MCInstrInfo &MII,
  74                                                const MCRegisterInfo &MRI) {
  75   return new RISCVInstPrinter(MAI, MII, MRI);
  76 }
  77
  78 static MCTargetStreamer *
  79 createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
  80   const Triple &TT = STI.getTargetTriple();
  81   if (TT.isOSBinFormatELF())
  82     return new RISCVTargetELFStreamer(S, STI);
  83   return nullptr;
  84 }
  85
  86 static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S,
  87                                                       formatted_raw_ostream &OS,
  88                                                       MCInstPrinter *InstPrint,
  89                                                       bool isVerboseAsm) {
  90   return new RISCVTargetAsmStreamer(S, OS);
  91 }
  92
  93 extern "C" void LLVMInitializeRISCVTargetMC() {
  94   for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
  95     TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
  96     TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
  97     TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
  98     TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
  99     TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
 100     TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
 101     TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
 102     TargetRegistry::RegisterObjectTargetStreamer(
 103         *T, createRISCVObjectTargetStreamer);
 104
 105     // Register the asm target streamer.
 106     TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
 107   }
 108 }