contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.td

   1 //===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 include "llvm/Target/Target.td"
  10
  11 //===----------------------------------------------------------------------===//
  12 // RISC-V subtarget features and instruction predicates.
  13 //===----------------------------------------------------------------------===//
  14
  15 def FeatureStdExtM
  16     : SubtargetFeature<"m", "HasStdExtM", "true",
  17                        "'M' (Integer Multiplication and Division)">;
  18 def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
  19                            AssemblerPredicate<(all_of FeatureStdExtM),
  20                            "'M' (Integer Multiplication and Division)">;
  21
  22 def FeatureStdExtZmmul
  23     : SubtargetFeature<"zmmul", "HasStdExtZmmul", "true",
  24                        "'Zmmul' (Integer Multiplication)">;
  25 def HasStdExtZmmul : Predicate<"Subtarget->hasStdExtZmmul()">,
  26                                AssemblerPredicate<(all_of FeatureStdExtZmmul),
  27                                "'Zmmul' (Integer Multiplication)">;
  28
  29 def HasStdExtMOrZmmul
  30     : Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
  31                 AssemblerPredicate<(any_of FeatureStdExtM, FeatureStdExtZmmul),
  32                                    "'M' (Integer Multiplication and Division) or "
  33                                    "'Zmmul' (Integer Multiplication)">;
  34
  35 def FeatureStdExtA
  36     : SubtargetFeature<"a", "HasStdExtA", "true",
  37                        "'A' (Atomic Instructions)">;
  38 def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
  39                            AssemblerPredicate<(all_of FeatureStdExtA),
  40                            "'A' (Atomic Instructions)">;
  41
  42 def FeatureStdExtF
  43     : SubtargetFeature<"f", "HasStdExtF", "true",
  44                        "'F' (Single-Precision Floating-Point)">;
  45 def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
  46                            AssemblerPredicate<(all_of FeatureStdExtF),
  47                            "'F' (Single-Precision Floating-Point)">;
  48
  49 def FeatureStdExtD
  50     : SubtargetFeature<"d", "HasStdExtD", "true",
  51                        "'D' (Double-Precision Floating-Point)",
  52                        [FeatureStdExtF]>;
  53 def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
  54                            AssemblerPredicate<(all_of FeatureStdExtD),
  55                            "'D' (Double-Precision Floating-Point)">;
  56
  57 def FeatureStdExtZihintpause
  58     : SubtargetFeature<"zihintpause", "HasStdExtZihintpause", "true",
  59                        "'zihintpause' (Pause Hint)">;
  60 def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
  61                                      AssemblerPredicate<(all_of FeatureStdExtZihintpause),
  62                                      "'Zihintpause' (Pause Hint)">;
  63
  64 def FeatureStdExtZfhmin
  65     : SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true",
  66                        "'Zfhmin' (Half-Precision Floating-Point Minimal)",
  67                        [FeatureStdExtF]>;
  68 def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
  69                              AssemblerPredicate<(all_of FeatureStdExtZfhmin),
  70                              "'Zfhmin' (Half-Precision Floating-Point Minimal)">;
  71
  72 def FeatureStdExtZfh
  73     : SubtargetFeature<"zfh", "HasStdExtZfh", "true",
  74                        "'Zfh' (Half-Precision Floating-Point)",
  75                        [FeatureStdExtF]>;
  76 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
  77                              AssemblerPredicate<(all_of FeatureStdExtZfh),
  78                              "'Zfh' (Half-Precision Floating-Point)">;
  79
  80 def HasStdExtZfhOrZfhmin
  81     : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZfhmin()">,
  82                 AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin),
  83                                    "'Zfh' (Half-Precision Floating-Point) or "
  84                                    "'Zfhmin' (Half-Precision Floating-Point Minimal)">;
  85
  86 def FeatureStdExtZfinx
  87     : SubtargetFeature<"zfinx", "HasStdExtZfinx", "true",
  88                        "'Zfinx' (Float in Integer)">;
  89 def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
  90                                AssemblerPredicate<(all_of FeatureStdExtZfinx),
  91                                "'Zfinx' (Float in Integer)">;
  92
  93 def FeatureStdExtZdinx
  94     : SubtargetFeature<"zdinx", "HasStdExtZdinx", "true",
  95                        "'Zdinx' (Double in Integer)",
  96                        [FeatureStdExtZfinx]>;
  97 def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
  98                                AssemblerPredicate<(all_of FeatureStdExtZdinx),
  99                                "'Zdinx' (Double in Integer)">;
 100
 101 def FeatureStdExtZhinxmin
 102     : SubtargetFeature<"zhinxmin", "HasStdExtZhinxmin", "true",
 103                        "'Zhinxmin' (Half Float in Integer Minimal)",
 104                        [FeatureStdExtZfinx]>;
 105 def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
 106                                   AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
 107                                   "'Zhinxmin' (Half Float in Integer Minimal)">;
 108
 109 def FeatureStdExtZhinx
 110     : SubtargetFeature<"zhinx", "HasStdExtZhinx", "true",
 111                        "'Zhinx' (Half Float in Integer)",
 112                        [FeatureStdExtZfinx]>;
 113 def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
 114                                AssemblerPredicate<(all_of FeatureStdExtZhinx),
 115                                "'Zhinx' (Half Float in Integer)">;
 116
 117 def HasStdExtZhinxOrZhinxmin
 118     : Predicate<"Subtarget->hasStdExtZhinx() || Subtarget->hasStdExtZhinxmin()">,
 119                 AssemblerPredicate<(any_of FeatureStdExtZhinx, FeatureStdExtZhinxmin),
 120                                    "'Zhinx' (Half Float in Integer) or "
 121                                    "'Zhinxmin' (Half Float in Integer Minimal)">;
 122
 123 def FeatureStdExtC
 124     : SubtargetFeature<"c", "HasStdExtC", "true",
 125                        "'C' (Compressed Instructions)">;
 126 def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
 127                            AssemblerPredicate<(all_of FeatureStdExtC),
 128                            "'C' (Compressed Instructions)">;
 129
 130 def FeatureStdExtZba
 131     : SubtargetFeature<"zba", "HasStdExtZba", "true",
 132                        "'Zba' (Address Generation Instructions)">;
 133 def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
 134                              AssemblerPredicate<(all_of FeatureStdExtZba),
 135                              "'Zba' (Address Generation Instructions)">;
 136 def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
 137
 138 def FeatureStdExtZbb
 139     : SubtargetFeature<"zbb", "HasStdExtZbb", "true",
 140                        "'Zbb' (Basic Bit-Manipulation)">;
 141 def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
 142                              AssemblerPredicate<(all_of FeatureStdExtZbb),
 143                              "'Zbb' (Basic Bit-Manipulation)">;
 144
 145 def FeatureStdExtZbc
 146     : SubtargetFeature<"zbc", "HasStdExtZbc", "true",
 147                        "'Zbc' (Carry-Less Multiplication)">;
 148 def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
 149                              AssemblerPredicate<(all_of FeatureStdExtZbc),
 150                              "'Zbc' (Carry-Less Multiplication)">;
 151
 152 def FeatureStdExtZbe
 153     : SubtargetFeature<"experimental-zbe", "HasStdExtZbe", "true",
 154                        "'Zbe' (Extract-Deposit 'Zb' Instructions)">;
 155 def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">,
 156                              AssemblerPredicate<(all_of FeatureStdExtZbe),
 157                              "'Zbe' (Extract-Deposit 'Zb' Instructions)">;
 158
 159 def FeatureStdExtZbf
 160     : SubtargetFeature<"experimental-zbf", "HasStdExtZbf", "true",
 161                        "'Zbf' (Bit-Field 'Zb' Instructions)">;
 162 def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">,
 163                              AssemblerPredicate<(all_of FeatureStdExtZbf),
 164                              "'Zbf' (Bit-Field 'Zb' Instructions)">;
 165
 166 def FeatureStdExtZbm
 167     : SubtargetFeature<"experimental-zbm", "HasStdExtZbm", "true",
 168                        "'Zbm' (Matrix 'Zb' Instructions)">;
 169 def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">,
 170                              AssemblerPredicate<(all_of FeatureStdExtZbm),
 171                              "'Zbm' (Matrix 'Zb' Instructions)">;
 172
 173 def FeatureStdExtZbp
 174     : SubtargetFeature<"experimental-zbp", "HasStdExtZbp", "true",
 175                        "'Zbp' (Permutation 'Zb' Instructions)">;
 176 def HasStdExtZbp : Predicate<"Subtarget->hasStdExtZbp()">,
 177                              AssemblerPredicate<(all_of FeatureStdExtZbp),
 178                              "'Zbp' (Permutation 'Zb' Instructions)">;
 179
 180 def FeatureStdExtZbr
 181     : SubtargetFeature<"experimental-zbr", "HasStdExtZbr", "true",
 182                        "'Zbr' (Polynomial Reduction 'Zb' Instructions)">;
 183 def HasStdExtZbr : Predicate<"Subtarget->hasStdExtZbr()">,
 184                              AssemblerPredicate<(all_of FeatureStdExtZbr),
 185                              "'Zbr' (Polynomial Reduction 'Zb' Instructions)">;
 186
 187 def FeatureStdExtZbs
 188     : SubtargetFeature<"zbs", "HasStdExtZbs", "true",
 189                        "'Zbs' (Single-Bit Instructions)">;
 190 def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 191                              AssemblerPredicate<(all_of FeatureStdExtZbs),
 192                              "'Zbs' (Single-Bit Instructions)">;
 193
 194 def FeatureStdExtZbt
 195     : SubtargetFeature<"experimental-zbt", "HasStdExtZbt", "true",
 196                        "'Zbt' (Ternary 'Zb' Instructions)">;
 197 def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">,
 198                              AssemblerPredicate<(all_of FeatureStdExtZbt),
 199                              "'Zbt' (Ternary 'Zb' Instructions)">;
 200
 201 // Some instructions belong to both the basic and the permutation
 202 // subextensions. They should be enabled if either has been specified.
 203 def HasStdExtZbbOrZbp
 204     : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">,
 205                 AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp),
 206                                    "'Zbb' (Basic Bit-Manipulation) or "
 207                                    "'Zbp' (Permutation 'Zb' Instructions)">;
 208
 209 def FeatureStdExtZbkb
 210     : SubtargetFeature<"zbkb", "HasStdExtZbkb", "true",
 211                        "'Zbkb' (Bitmanip instructions for Cryptography)">;
 212 def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
 213                              AssemblerPredicate<(all_of FeatureStdExtZbkb),
 214                              "'Zbkb' (Bitmanip instructions for Cryptography)">;
 215
 216 def FeatureStdExtZbkx
 217     : SubtargetFeature<"zbkx", "HasStdExtZbkx", "true",
 218                        "'Zbkx' (Crossbar permutation instructions)">;
 219 def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
 220                              AssemblerPredicate<(all_of FeatureStdExtZbkx),
 221                              "'Zbkx' (Crossbar permutation instructions)">;
 222
 223 def HasStdExtZbpOrZbkx
 224     : Predicate<"Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkx()">,
 225                 AssemblerPredicate<(any_of FeatureStdExtZbp, FeatureStdExtZbkx),
 226                                    "'Zbp' (Permutation 'Zb' Instructions) or "
 227                                    "'Zbkx' (Crossbar permutation instructions)">;
 228
 229 def HasStdExtZbpOrZbkb
 230     : Predicate<"Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">,
 231                 AssemblerPredicate<(any_of FeatureStdExtZbp, FeatureStdExtZbkb),
 232                                    "'Zbp' (Permutation 'Zb' Instructions) or "
 233                                    "'Zbkb' (Bitmanip instructions for Cryptography)">;
 234
 235 def HasStdExtZbbOrZbkb
 236     : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()">,
 237                 AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb),
 238                                    "'Zbb' (Basic Bit-Manipulation) or "
 239                                    "'Zbkb' (Bitmanip instructions for Cryptography)">;
 240
 241 def HasStdExtZbbOrZbpOrZbkb
 242     : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">,
 243                 AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp, FeatureStdExtZbkb),
 244                                    "'Zbb' (Basic Bit-Manipulation) or "
 245                                    "'Zbp' (Permutation 'Zb' Instructions) or "
 246                                    "'Zbkb' (Bitmanip instructions for Cryptography)">;
 247
 248 // The Carry-less multiply subextension for cryptography is a subset of basic carry-less multiply subextension. The former should be enabled if the latter is enabled.
 249 def FeatureStdExtZbkc
 250     : SubtargetFeature<"zbkc", "HasStdExtZbkc", "true",
 251                        "'Zbkc' (Carry-less multiply instructions for Cryptography)">;
 252 def HasStdExtZbkc
 253     : Predicate<"Subtarget->hasStdExtZbkc()">,
 254                              AssemblerPredicate<(all_of FeatureStdExtZbkc),
 255                              "'Zbkc' (Carry-less multiply instructions for Cryptography)">;
 256
 257 def HasStdExtZbcOrZbkc
 258     : Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">,
 259                 AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc),
 260                                    "'Zbc' (Carry-Less Multiplication) or "
 261                                    "'Zbkc' (Carry-less multiply instructions for Cryptography)">;
 262
 263 def FeatureStdExtZknd
 264     : SubtargetFeature<"zknd", "HasStdExtZknd", "true",
 265                        "'Zknd' (NIST Suite: AES Decryption)">;
 266 def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
 267                              AssemblerPredicate<(all_of FeatureStdExtZknd),
 268                              "'Zknd' (NIST Suite: AES Decryption)">;
 269
 270 def FeatureStdExtZkne
 271     : SubtargetFeature<"zkne", "HasStdExtZkne", "true",
 272                        "'Zkne' (NIST Suite: AES Encryption)">;
 273 def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
 274                              AssemblerPredicate<(all_of FeatureStdExtZkne),
 275                              "'Zkne' (NIST Suite: AES Encryption)">;
 276
 277 // Some instructions belong to both Zknd and Zkne subextensions.
 278 // They should be enabled if either has been specified.
 279 def HasStdExtZkndOrZkne
 280     : Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">,
 281                 AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne),
 282                                    "'Zknd' (NIST Suite: AES Decryption) or "
 283                                    "'Zkne' (NIST Suite: AES Encryption)">;
 284
 285 def FeatureStdExtZknh
 286     : SubtargetFeature<"zknh", "HasStdExtZknh", "true",
 287                        "'Zknh' (NIST Suite: Hash Function Instructions)">;
 288 def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
 289                              AssemblerPredicate<(all_of FeatureStdExtZknh),
 290                              "'Zknh' (NIST Suite: Hash Function Instructions)">;
 291
 292 def FeatureStdExtZksed
 293     : SubtargetFeature<"zksed", "HasStdExtZksed", "true",
 294                        "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
 295 def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
 296                              AssemblerPredicate<(all_of FeatureStdExtZksed),
 297                              "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
 298
 299 def FeatureStdExtZksh
 300     : SubtargetFeature<"zksh", "HasStdExtZksh", "true",
 301                        "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
 302 def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
 303                              AssemblerPredicate<(all_of FeatureStdExtZksh),
 304                              "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
 305
 306 def FeatureStdExtZkr
 307     : SubtargetFeature<"zkr", "HasStdExtZkr", "true",
 308                        "'Zkr' (Entropy Source Extension)">;
 309 def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
 310                              AssemblerPredicate<(all_of FeatureStdExtZkr),
 311                              "'Zkr' (Entropy Source Extension)">;
 312
 313 def FeatureStdExtZkn
 314     : SubtargetFeature<"zkn", "HasStdExtZkn", "true",
 315                        "'Zkn' (NIST Algorithm Suite)",
 316                        [FeatureStdExtZbkb,
 317                         FeatureStdExtZbkc,
 318                         FeatureStdExtZbkx,
 319                         FeatureStdExtZkne,
 320                         FeatureStdExtZknd,
 321                         FeatureStdExtZknh]>;
 322
 323 def FeatureStdExtZks
 324     : SubtargetFeature<"zks", "HasStdExtZks", "true",
 325                        "'Zks' (ShangMi Algorithm Suite)",
 326                        [FeatureStdExtZbkb,
 327                         FeatureStdExtZbkc,
 328                         FeatureStdExtZbkx,
 329                         FeatureStdExtZksed,
 330                         FeatureStdExtZksh]>;
 331
 332 def FeatureStdExtZkt
 333     : SubtargetFeature<"zkt", "HasStdExtZkt", "true",
 334                        "'Zkt' (Data Independent Execution Latency)">;
 335
 336 def FeatureStdExtZk
 337     : SubtargetFeature<"zk", "HasStdExtZk", "true",
 338                        "'Zk' (Standard scalar cryptography extension)",
 339                        [FeatureStdExtZkn,
 340                         FeatureStdExtZkr,
 341                         FeatureStdExtZkt]>;
 342
 343 def FeatureNoRVCHints
 344     : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
 345                        "Disable RVC Hint Instructions.">;
 346 def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
 347                   AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
 348                                       "RVC Hint Instructions">;
 349
 350 def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "32",
 351                        "'Zvl' (Minimum Vector Length) 32">;
 352
 353 foreach i = { 6-15 } in {
 354     defvar I = !shl(1, i);
 355     def FeatureStdExtZvl#I#b :
 356         SubtargetFeature<"zvl"#I#"b", "ZvlLen", !cast<string>(I),
 357                         "'Zvl' (Minimum Vector Length) "#I,
 358                         [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
 359 }
 360
 361 def FeatureStdExtZve32x
 362     : SubtargetFeature<"zve32x", "HasStdExtZve32x", "true",
 363                        "'Zve32x' (Vector Extensions for Embedded Processors "
 364                        "with maximal 32 EEW)",
 365                        [FeatureStdExtZvl32b]>;
 366
 367 def FeatureStdExtZve32f
 368     : SubtargetFeature<"zve32f", "HasStdExtZve32f", "true",
 369                        "'Zve32f' (Vector Extensions for Embedded Processors "
 370                        "with maximal 32 EEW and F extension)",
 371                        [FeatureStdExtZve32x]>;
 372
 373 def FeatureStdExtZve64x
 374     : SubtargetFeature<"zve64x", "HasStdExtZve64x", "true",
 375                        "'Zve64x' (Vector Extensions for Embedded Processors "
 376                        "with maximal 64 EEW)", [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
 377
 378 def FeatureStdExtZve64f
 379     : SubtargetFeature<"zve64f", "HasStdExtZve64f", "true",
 380                        "'Zve64f' (Vector Extensions for Embedded Processors "
 381                        "with maximal 64 EEW and F extension)",
 382                        [FeatureStdExtZve32f, FeatureStdExtZve64x]>;
 383
 384 def FeatureStdExtZve64d
 385     : SubtargetFeature<"zve64d", "HasStdExtZve64d", "true",
 386                        "'Zve64d' (Vector Extensions for Embedded Processors "
 387                        "with maximal 64 EEW, F and D extension)",
 388                        [FeatureStdExtZve64f]>;
 389
 390 def FeatureStdExtV
 391     : SubtargetFeature<"v", "HasStdExtV", "true",
 392                        "'V' (Vector Extension for Application Processors)",
 393                        [FeatureStdExtZvl128b, FeatureStdExtZve64d, FeatureStdExtF, FeatureStdExtD]>;
 394
 395 def HasVInstructions    : Predicate<"Subtarget->hasVInstructions()">,
 396       AssemblerPredicate<
 397           (any_of FeatureStdExtZve32x),
 398           "'V' (Vector Extension for Application Processors), 'Zve32x' or "
 399           "'Zve64x' (Vector Extensions for Embedded Processors)">;
 400 def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">,
 401       AssemblerPredicate<
 402           (any_of FeatureStdExtZve64x),
 403           "'V' (Vector Extension for Application Processors) or 'Zve64x' "
 404           "(Vector Extensions for Embedded Processors)">;
 405 def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">,
 406       AssemblerPredicate<
 407           (any_of FeatureStdExtZve32f),
 408           "'V' (Vector Extension for Application Processors), 'Zve32f', "
 409           "'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors)">;
 410
 411 def FeatureStdExtZvfh
 412     : SubtargetFeature<"experimental-zvfh", "HasStdExtZvfh", "true",
 413                        "'Zvfh' (Vector Half-Precision Floating-Point)",
 414                        [FeatureStdExtZve32f]>;
 415
 416 def FeatureStdExtZicbom
 417     : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
 418                        "'Zicbom' (Cache-Block Management Instructions)">;
 419 def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
 420                                 AssemblerPredicate<(all_of FeatureStdExtZicbom),
 421                                 "'Zicbom' (Cache-Block Management Instructions)">;
 422
 423 def FeatureStdExtZicboz
 424     : SubtargetFeature<"zicboz", "HasStdExtZicboz", "true",
 425                        "'Zicboz' (Cache-Block Zero Instructions)">;
 426 def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
 427                                 AssemblerPredicate<(all_of FeatureStdExtZicboz),
 428                                 "'Zicboz' (Cache-Block Zero Instructions)">;
 429
 430 def FeatureStdExtZicbop
 431     : SubtargetFeature<"zicbop", "HasStdExtZicbop", "true",
 432                        "'Zicbop' (Cache-Block Prefetch Instructions)">;
 433 def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
 434                                 AssemblerPredicate<(all_of FeatureStdExtZicbop),
 435                                 "'Zicbop' (Cache-Block Prefetch Instructions)">;
 436
 437 def Feature64Bit
 438     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
 439 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
 440                        AssemblerPredicate<(all_of Feature64Bit),
 441                        "RV64I Base Instruction Set">;
 442 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
 443                        AssemblerPredicate<(all_of (not Feature64Bit)),
 444                        "RV32I Base Instruction Set">;
 445
 446 defvar RV32 = DefaultMode;
 447 def RV64           : HwMode<"+64bit">;
 448
 449 def FeatureRV32E
 450     : SubtargetFeature<"e", "IsRV32E", "true",
 451                        "Implements RV32E (provides 16 rather than 32 GPRs)">;
 452 def IsRV32E : Predicate<"Subtarget->isRV32E()">,
 453                         AssemblerPredicate<(all_of FeatureRV32E)>;
 454
 455 def FeatureRelax
 456     : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
 457                        "Enable Linker relaxation.">;
 458
 459 foreach i = {1-31} in
 460     def FeatureReserveX#i :
 461         SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
 462                          "true", "Reserve X"#i>;
 463
 464 def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
 465                                           "true", "Enable save/restore.">;
 466
 467 def FeatureUnalignedScalarMem
 468    : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",
 469                       "true", "Has reasonably performant unaligned scalar "
 470                       "loads and stores">;
 471
 472 def TuneLUIADDIFusion
 473     : SubtargetFeature<"lui-addi-fusion", "HasLUIADDIFusion",
 474                        "true", "Enable LUI+ADDI macrofusion">;
 475
 476 def TuneNoDefaultUnroll
 477     : SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false",
 478                        "Disable default unroll preference.">;
 479
 480 def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
 481                                    "SiFive 7-Series processors",
 482                                    [TuneNoDefaultUnroll]>;
 483
 484 //===----------------------------------------------------------------------===//
 485 // Named operands for CSR instructions.
 486 //===----------------------------------------------------------------------===//
 487
 488 include "RISCVSystemOperands.td"
 489
 490 //===----------------------------------------------------------------------===//
 491 // Registers, calling conventions, instruction descriptions.
 492 //===----------------------------------------------------------------------===//
 493
 494 include "RISCVSchedule.td"
 495 include "RISCVRegisterInfo.td"
 496 include "RISCVCallingConv.td"
 497 include "RISCVInstrInfo.td"
 498 include "RISCVRegisterBanks.td"
 499 include "RISCVSchedRocket.td"
 500 include "RISCVSchedSiFive7.td"
 501
 502 //===----------------------------------------------------------------------===//
 503 // RISC-V processors supported.
 504 //===----------------------------------------------------------------------===//
 505
 506 def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
 507 def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
 508 // Support generic for compatibility with other targets. The triple will be used
 509 // to change to the appropriate rv32/rv64 version.
 510 def : ProcessorModel<"generic", NoSchedModel, []>;
 511
 512 def : ProcessorModel<"rocket-rv32", RocketModel, []>;
 513 def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
 514
 515 def : ProcessorModel<"sifive-7-rv32", SiFive7Model, [],
 516                      [TuneSiFive7]>;
 517 def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit],
 518                      [TuneSiFive7]>;
 519
 520 def : ProcessorModel<"sifive-e20", RocketModel, [FeatureStdExtM,
 521                                                  FeatureStdExtC]>;
 522
 523 def : ProcessorModel<"sifive-e21", RocketModel, [FeatureStdExtM,
 524                                                  FeatureStdExtA,
 525                                                  FeatureStdExtC]>;
 526
 527 def : ProcessorModel<"sifive-e24", RocketModel, [FeatureStdExtM,
 528                                                  FeatureStdExtA,
 529                                                  FeatureStdExtF,
 530                                                  FeatureStdExtC]>;
 531
 532 def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM,
 533                                                  FeatureStdExtA,
 534                                                  FeatureStdExtC]>;
 535
 536 def : ProcessorModel<"sifive-e34", RocketModel, [FeatureStdExtM,
 537                                                  FeatureStdExtA,
 538                                                  FeatureStdExtF,
 539                                                  FeatureStdExtC]>;
 540
 541 def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM,
 542                                                   FeatureStdExtA,
 543                                                   FeatureStdExtF,
 544                                                   FeatureStdExtC],
 545                      [TuneSiFive7]>;
 546
 547 def : ProcessorModel<"sifive-s21", RocketModel, [Feature64Bit,
 548                                                  FeatureStdExtM,
 549                                                  FeatureStdExtA,
 550                                                  FeatureStdExtC]>;
 551
 552 def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
 553                                                  FeatureStdExtM,
 554                                                  FeatureStdExtA,
 555                                                  FeatureStdExtC]>;
 556
 557 def : ProcessorModel<"sifive-s54", RocketModel, [Feature64Bit,
 558                                                  FeatureStdExtM,
 559                                                  FeatureStdExtA,
 560                                                  FeatureStdExtF,
 561                                                  FeatureStdExtD,
 562                                                  FeatureStdExtC]>;
 563
 564 def : ProcessorModel<"sifive-s76", SiFive7Model, [Feature64Bit,
 565                                                   FeatureStdExtM,
 566                                                   FeatureStdExtA,
 567                                                   FeatureStdExtF,
 568                                                   FeatureStdExtD,
 569                                                   FeatureStdExtC],
 570                      [TuneSiFive7]>;
 571
 572 def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
 573                                                  FeatureStdExtM,
 574                                                  FeatureStdExtA,
 575                                                  FeatureStdExtF,
 576                                                  FeatureStdExtD,
 577                                                  FeatureStdExtC]>;
 578
 579 def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit,
 580                                                   FeatureStdExtM,
 581                                                   FeatureStdExtA,
 582                                                   FeatureStdExtF,
 583                                                   FeatureStdExtD,
 584                                                   FeatureStdExtC],
 585                      [TuneSiFive7]>;
 586
 587 //===----------------------------------------------------------------------===//
 588 // Define the RISC-V target.
 589 //===----------------------------------------------------------------------===//
 590
 591 def RISCVInstrInfo : InstrInfo {
 592   let guessInstructionProperties = 0;
 593 }
 594
 595 def RISCVAsmParser : AsmParser {
 596   let ShouldEmitMatchRegisterAltName = 1;
 597   let AllowDuplicateRegisterNames = 1;
 598 }
 599
 600 def RISCVAsmWriter : AsmWriter {
 601   int PassSubtarget = 1;
 602 }
 603
 604 def RISCV : Target {
 605   let InstructionSet = RISCVInstrInfo;
 606   let AssemblyParsers = [RISCVAsmParser];
 607   let AssemblyWriters = [RISCVAsmWriter];
 608   let AllowRegisterRenaming = 1;
 609 }