1 //===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 include "llvm/Target/Target.td"
11 //===----------------------------------------------------------------------===//
12 // RISC-V subtarget features and instruction predicates.
13 //===----------------------------------------------------------------------===//
16 : SubtargetFeature<"m", "HasStdExtM", "true",
17 "'M' (Integer Multiplication and Division)">;
18 def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
19 AssemblerPredicate<"FeatureStdExtM",
20 "'M' (Integer Multiplication and Division)">;
23 : SubtargetFeature<"a", "HasStdExtA", "true",
24 "'A' (Atomic Instructions)">;
25 def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
26 AssemblerPredicate<"FeatureStdExtA",
27 "'A' (Atomic Instructions)">;
30 : SubtargetFeature<"f", "HasStdExtF", "true",
31 "'F' (Single-Precision Floating-Point)">;
32 def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
33 AssemblerPredicate<"FeatureStdExtF",
34 "'F' (Single-Precision Floating-Point)">;
37 : SubtargetFeature<"d", "HasStdExtD", "true",
38 "'D' (Double-Precision Floating-Point)",
40 def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
41 AssemblerPredicate<"FeatureStdExtD",
42 "'D' (Double-Precision Floating-Point)">;
45 : SubtargetFeature<"c", "HasStdExtC", "true",
46 "'C' (Compressed Instructions)">;
47 def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
48 AssemblerPredicate<"FeatureStdExtC",
49 "'C' (Compressed Instructions)">;
52 : SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true",
53 "Enable RVC Hint Instructions.">;
54 def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
55 AssemblerPredicate<"FeatureRVCHints",
56 "RVC Hint Instructions">;
59 : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
60 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
61 AssemblerPredicate<"Feature64Bit",
62 "RV64I Base Instruction Set">;
63 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
64 AssemblerPredicate<"!Feature64Bit",
65 "RV32I Base Instruction Set">;
67 def RV64 : HwMode<"+64bit">;
68 def RV32 : HwMode<"-64bit">;
71 : SubtargetFeature<"e", "IsRV32E", "true",
72 "Implements RV32E (provides 16 rather than 32 GPRs)">;
73 def IsRV32E : Predicate<"Subtarget->isRV32E()">,
74 AssemblerPredicate<"FeatureRV32E">;
77 : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
78 "Enable Linker relaxation.">;
81 def FeatureReserveX#i :
82 SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
83 "true", "Reserve X"#i>;
85 //===----------------------------------------------------------------------===//
86 // Named operands for CSR instructions.
87 //===----------------------------------------------------------------------===//
89 include "RISCVSystemOperands.td"
91 //===----------------------------------------------------------------------===//
92 // Registers, calling conventions, instruction descriptions.
93 //===----------------------------------------------------------------------===//
95 include "RISCVSchedule.td"
96 include "RISCVRegisterInfo.td"
97 include "RISCVCallingConv.td"
98 include "RISCVInstrInfo.td"
99 include "RISCVRegisterBanks.td"
100 include "RISCVSchedRocket32.td"
101 include "RISCVSchedRocket64.td"
103 //===----------------------------------------------------------------------===//
104 // RISC-V processors supported.
105 //===----------------------------------------------------------------------===//
107 def : ProcessorModel<"generic-rv32", NoSchedModel, [FeatureRVCHints]>;
109 def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit,
112 def : ProcessorModel<"rocket-rv32", Rocket32Model, [FeatureRVCHints]>;
114 def : ProcessorModel<"rocket-rv64", Rocket64Model, [Feature64Bit,
118 //===----------------------------------------------------------------------===//
119 // Define the RISC-V target.
120 //===----------------------------------------------------------------------===//
122 def RISCVInstrInfo : InstrInfo {
123 let guessInstructionProperties = 0;
126 def RISCVAsmParser : AsmParser {
127 let ShouldEmitMatchRegisterAltName = 1;
128 let AllowDuplicateRegisterNames = 1;
131 def RISCVAsmWriter : AsmWriter {
132 int PassSubtarget = 1;
136 let InstructionSet = RISCVInstrInfo;
137 let AssemblyParsers = [RISCVAsmParser];
138 let AssemblyWriters = [RISCVAsmWriter];
139 let AllowRegisterRenaming = 1;