1 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the RISCV implementation of the TargetInstrInfo class.
11 //===----------------------------------------------------------------------===//
13 #include "RISCVInstrInfo.h"
15 #include "RISCVSubtarget.h"
16 #include "RISCVTargetMachine.h"
17 #include "Utils/RISCVMatInt.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
27 #define GET_INSTRINFO_CTOR_DTOR
28 #include "RISCVGenInstrInfo.inc"
32 RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI)
33 : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP),
36 unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
37 int &FrameIndex) const {
38 switch (MI.getOpcode()) {
53 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
54 MI.getOperand(2).getImm() == 0) {
55 FrameIndex = MI.getOperand(1).getIndex();
56 return MI.getOperand(0).getReg();
62 unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
63 int &FrameIndex) const {
64 switch (MI.getOpcode()) {
76 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
77 MI.getOperand(1).getImm() == 0) {
78 FrameIndex = MI.getOperand(0).getIndex();
79 return MI.getOperand(2).getReg();
85 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
86 MachineBasicBlock::iterator MBBI,
87 const DebugLoc &DL, unsigned DstReg,
88 unsigned SrcReg, bool KillSrc) const {
89 if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
90 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
91 .addReg(SrcReg, getKillRegState(KillSrc))
98 if (RISCV::FPR32RegClass.contains(DstReg, SrcReg))
100 else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg))
101 Opc = RISCV::FSGNJ_D;
103 llvm_unreachable("Impossible reg-to-reg copy");
105 BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
106 .addReg(SrcReg, getKillRegState(KillSrc))
107 .addReg(SrcReg, getKillRegState(KillSrc));
110 void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
111 MachineBasicBlock::iterator I,
112 unsigned SrcReg, bool IsKill, int FI,
113 const TargetRegisterClass *RC,
114 const TargetRegisterInfo *TRI) const {
117 DL = I->getDebugLoc();
121 if (RISCV::GPRRegClass.hasSubClassEq(RC))
122 Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
123 RISCV::SW : RISCV::SD;
124 else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
126 else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
129 llvm_unreachable("Can't store this register to stack slot");
131 BuildMI(MBB, I, DL, get(Opcode))
132 .addReg(SrcReg, getKillRegState(IsKill))
137 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
138 MachineBasicBlock::iterator I,
139 unsigned DstReg, int FI,
140 const TargetRegisterClass *RC,
141 const TargetRegisterInfo *TRI) const {
144 DL = I->getDebugLoc();
148 if (RISCV::GPRRegClass.hasSubClassEq(RC))
149 Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
150 RISCV::LW : RISCV::LD;
151 else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
153 else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
156 llvm_unreachable("Can't load this register from stack slot");
158 BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
161 void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
162 MachineBasicBlock::iterator MBBI,
163 const DebugLoc &DL, Register DstReg, uint64_t Val,
164 MachineInstr::MIFlag Flag) const {
165 MachineFunction *MF = MBB.getParent();
166 MachineRegisterInfo &MRI = MF->getRegInfo();
167 bool IsRV64 = MF->getSubtarget<RISCVSubtarget>().is64Bit();
168 Register SrcReg = RISCV::X0;
169 Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass);
172 if (!IsRV64 && !isInt<32>(Val))
173 report_fatal_error("Should only materialize 32-bit constants for RV32");
175 RISCVMatInt::InstSeq Seq;
176 RISCVMatInt::generateInstSeq(Val, IsRV64, Seq);
177 assert(Seq.size() > 0);
179 for (RISCVMatInt::Inst &Inst : Seq) {
180 // Write the final result to DstReg if it's the last instruction in the Seq.
181 // Otherwise, write the result to the temp register.
182 if (++Num == Seq.size())
185 if (Inst.Opc == RISCV::LUI) {
186 BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result)
190 BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
191 .addReg(SrcReg, RegState::Kill)
195 // Only the first instruction has X0 as its source.
200 // The contents of values added to Cond are not examined outside of
201 // RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we
202 // push BranchOpcode, Reg1, Reg2.
203 static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
204 SmallVectorImpl<MachineOperand> &Cond) {
205 // Block ends with fall-through condbranch.
206 assert(LastInst.getDesc().isConditionalBranch() &&
207 "Unknown conditional branch");
208 Target = LastInst.getOperand(2).getMBB();
209 Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
210 Cond.push_back(LastInst.getOperand(0));
211 Cond.push_back(LastInst.getOperand(1));
214 static unsigned getOppositeBranchOpcode(int Opc) {
217 llvm_unreachable("Unrecognized conditional branch");
233 bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
234 MachineBasicBlock *&TBB,
235 MachineBasicBlock *&FBB,
236 SmallVectorImpl<MachineOperand> &Cond,
237 bool AllowModify) const {
241 // If the block has no terminators, it just falls into the block after it.
242 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
243 if (I == MBB.end() || !isUnpredicatedTerminator(*I))
246 // Count the number of terminators and find the first unconditional or
248 MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
249 int NumTerminators = 0;
250 for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
253 if (J->getDesc().isUnconditionalBranch() ||
254 J->getDesc().isIndirectBranch()) {
255 FirstUncondOrIndirectBr = J.getReverse();
259 // If AllowModify is true, we can erase any terminators after
260 // FirstUncondOrIndirectBR.
261 if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
262 while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
263 std::next(FirstUncondOrIndirectBr)->eraseFromParent();
266 I = FirstUncondOrIndirectBr;
269 // We can't handle blocks that end in an indirect branch.
270 if (I->getDesc().isIndirectBranch())
273 // We can't handle blocks with more than 2 terminators.
274 if (NumTerminators > 2)
277 // Handle a single unconditional branch.
278 if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
279 TBB = I->getOperand(0).getMBB();
283 // Handle a single conditional branch.
284 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
285 parseCondBranch(*I, TBB, Cond);
289 // Handle a conditional branch followed by an unconditional branch.
290 if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
291 I->getDesc().isUnconditionalBranch()) {
292 parseCondBranch(*std::prev(I), TBB, Cond);
293 FBB = I->getOperand(0).getMBB();
297 // Otherwise, we can't handle this.
301 unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,
302 int *BytesRemoved) const {
305 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
309 if (!I->getDesc().isUnconditionalBranch() &&
310 !I->getDesc().isConditionalBranch())
313 // Remove the branch.
315 *BytesRemoved += getInstSizeInBytes(*I);
316 I->eraseFromParent();
320 if (I == MBB.begin())
323 if (!I->getDesc().isConditionalBranch())
326 // Remove the branch.
328 *BytesRemoved += getInstSizeInBytes(*I);
329 I->eraseFromParent();
333 // Inserts a branch into the end of the specific MachineBasicBlock, returning
334 // the number of instructions inserted.
335 unsigned RISCVInstrInfo::insertBranch(
336 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
337 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
341 // Shouldn't be a fall through.
342 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
343 assert((Cond.size() == 3 || Cond.size() == 0) &&
344 "RISCV branch conditions have two components!");
346 // Unconditional branch.
348 MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB);
350 *BytesAdded += getInstSizeInBytes(MI);
354 // Either a one or two-way conditional branch.
355 unsigned Opc = Cond[0].getImm();
356 MachineInstr &CondMI =
357 *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
359 *BytesAdded += getInstSizeInBytes(CondMI);
361 // One-way conditional branch.
365 // Two-way conditional branch.
366 MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB);
368 *BytesAdded += getInstSizeInBytes(MI);
372 unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
373 MachineBasicBlock &DestBB,
376 RegScavenger *RS) const {
377 assert(RS && "RegScavenger required for long branching");
378 assert(MBB.empty() &&
379 "new block should be inserted for expanding unconditional branch");
380 assert(MBB.pred_size() == 1);
382 MachineFunction *MF = MBB.getParent();
383 MachineRegisterInfo &MRI = MF->getRegInfo();
384 const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget());
386 if (TM.isPositionIndependent())
387 report_fatal_error("Unable to insert indirect branch");
389 if (!isInt<32>(BrOffset))
391 "Branch offsets outside of the signed 32-bit range not supported");
393 // FIXME: A virtual register must be used initially, as the register
394 // scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch
395 // uses the same workaround).
396 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
399 MachineInstr &LuiMI = *BuildMI(MBB, II, DL, get(RISCV::LUI), ScratchReg)
400 .addMBB(&DestBB, RISCVII::MO_HI);
401 BuildMI(MBB, II, DL, get(RISCV::PseudoBRIND))
402 .addReg(ScratchReg, RegState::Kill)
403 .addMBB(&DestBB, RISCVII::MO_LO);
405 RS->enterBasicBlockEnd(MBB);
406 unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
407 LuiMI.getIterator(), false, 0);
408 MRI.replaceRegWith(ScratchReg, Scav);
410 RS->setRegUsed(Scav);
414 bool RISCVInstrInfo::reverseBranchCondition(
415 SmallVectorImpl<MachineOperand> &Cond) const {
416 assert((Cond.size() == 3) && "Invalid branch condition!");
417 Cond[0].setImm(getOppositeBranchOpcode(Cond[0].getImm()));
422 RISCVInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
423 assert(MI.getDesc().isBranch() && "Unexpected opcode!");
424 // The branch target is always the last operand.
425 int NumOp = MI.getNumExplicitOperands();
426 return MI.getOperand(NumOp - 1).getMBB();
429 bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
430 int64_t BrOffset) const {
431 // Ideally we could determine the supported branch offset from the
432 // RISCVII::FormMask, but this can't be used for Pseudo instructions like
436 llvm_unreachable("Unexpected opcode!");
443 return isIntN(13, BrOffset);
445 case RISCV::PseudoBR:
446 return isIntN(21, BrOffset);
450 unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
451 unsigned Opcode = MI.getOpcode();
454 default: { return get(Opcode).getSize(); }
455 case TargetOpcode::EH_LABEL:
456 case TargetOpcode::IMPLICIT_DEF:
457 case TargetOpcode::KILL:
458 case TargetOpcode::DBG_VALUE:
460 case RISCV::PseudoCALLReg:
461 case RISCV::PseudoCALL:
462 case RISCV::PseudoTAIL:
463 case RISCV::PseudoLLA:
464 case RISCV::PseudoLA:
465 case RISCV::PseudoLA_TLS_IE:
466 case RISCV::PseudoLA_TLS_GD:
468 case TargetOpcode::INLINEASM:
469 case TargetOpcode::INLINEASM_BR: {
470 const MachineFunction &MF = *MI.getParent()->getParent();
471 const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget());
472 return getInlineAsmLength(MI.getOperand(0).getSymbolName(),
478 bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
479 const unsigned Opcode = MI.getOpcode();
486 return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0);
488 return MI.isAsCheapAsAMove();
491 bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
492 StringRef &ErrInfo) const {
493 const MCInstrInfo *MCII = STI.getInstrInfo();
494 MCInstrDesc const &Desc = MCII->get(MI.getOpcode());
496 for (auto &OI : enumerate(Desc.operands())) {
497 unsigned OpType = OI.value().OperandType;
498 if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM &&
499 OpType <= RISCVOp::OPERAND_LAST_RISCV_IMM) {
500 const MachineOperand &MO = MI.getOperand(OI.index());
502 int64_t Imm = MO.getImm();
506 llvm_unreachable("Unexpected operand type");
507 case RISCVOp::OPERAND_UIMM4:
510 case RISCVOp::OPERAND_UIMM5:
513 case RISCVOp::OPERAND_UIMM12:
514 Ok = isUInt<12>(Imm);
516 case RISCVOp::OPERAND_SIMM12:
519 case RISCVOp::OPERAND_SIMM13_LSB0:
520 Ok = isShiftedInt<12, 1>(Imm);
522 case RISCVOp::OPERAND_UIMM20:
523 Ok = isUInt<20>(Imm);
525 case RISCVOp::OPERAND_SIMM21_LSB0:
526 Ok = isShiftedInt<20, 1>(Imm);
528 case RISCVOp::OPERAND_UIMMLOG2XLEN:
529 if (STI.getTargetTriple().isArch64Bit())
536 ErrInfo = "Invalid immediate";