1 //===-- RISCVInstrInfoD.td - RISC-V 'D' instructions -------*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the RISC-V instructions from the standard 'D',
10 // Double-Precision Floating-Point instruction set extension.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // RISC-V specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDT_RISCVBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
21 def SDT_RISCVSplitF64 : SDTypeProfile<2, 1, [SDTCisVT<0, i32>,
25 def RISCVBuildPairF64 : SDNode<"RISCVISD::BuildPairF64", SDT_RISCVBuildPairF64>;
26 def RISCVSplitF64 : SDNode<"RISCVISD::SplitF64", SDT_RISCVSplitF64>;
28 //===----------------------------------------------------------------------===//
29 // Instruction Class Templates
30 //===----------------------------------------------------------------------===//
32 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
33 class FPFMAD_rrr_frm<RISCVOpcode opcode, string opcodestr>
34 : RVInstR4<0b01, opcode, (outs FPR64:$rd),
35 (ins FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, frmarg:$funct3),
36 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
38 class FPFMADDynFrmAlias<FPFMAD_rrr_frm Inst, string OpcodeStr>
39 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
40 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
42 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
43 class FPALUD_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
44 : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR64:$rd),
45 (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">,
46 Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
48 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
49 class FPALUD_rr_frm<bits<7> funct7, string opcodestr>
50 : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR64:$rd),
51 (ins FPR64:$rs1, FPR64:$rs2, frmarg:$funct3), opcodestr,
52 "$rd, $rs1, $rs2, $funct3">,
53 Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
55 class FPALUDDynFrmAlias<FPALUD_rr_frm Inst, string OpcodeStr>
56 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
57 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, 0b111)>;
59 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
60 class FPCmpD_rr<bits<3> funct3, string opcodestr>
61 : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd),
62 (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">,
63 Sched<[WriteFCmp64, ReadFCmp64, ReadFCmp64]>;
65 //===----------------------------------------------------------------------===//
67 //===----------------------------------------------------------------------===//
69 let Predicates = [HasStdExtD] in {
71 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
72 def FLD : RVInstI<0b011, OPC_LOAD_FP, (outs FPR64:$rd),
73 (ins GPR:$rs1, simm12:$imm12),
74 "fld", "$rd, ${imm12}(${rs1})">,
75 Sched<[WriteFLD64, ReadMemBase]>;
77 // Operands for stores are in the order srcreg, base, offset rather than
78 // reflecting the order these fields are specified in the instruction
80 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
81 def FSD : RVInstS<0b011, OPC_STORE_FP, (outs),
82 (ins FPR64:$rs2, GPR:$rs1, simm12:$imm12),
83 "fsd", "$rs2, ${imm12}(${rs1})">,
84 Sched<[WriteFST64, ReadStoreData, ReadMemBase]>;
86 def FMADD_D : FPFMAD_rrr_frm<OPC_MADD, "fmadd.d">,
87 Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
88 def : FPFMADDynFrmAlias<FMADD_D, "fmadd.d">;
89 def FMSUB_D : FPFMAD_rrr_frm<OPC_MSUB, "fmsub.d">,
90 Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
91 def : FPFMADDynFrmAlias<FMSUB_D, "fmsub.d">;
92 def FNMSUB_D : FPFMAD_rrr_frm<OPC_NMSUB, "fnmsub.d">,
93 Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
94 def : FPFMADDynFrmAlias<FNMSUB_D, "fnmsub.d">;
95 def FNMADD_D : FPFMAD_rrr_frm<OPC_NMADD, "fnmadd.d">,
96 Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
97 def : FPFMADDynFrmAlias<FNMADD_D, "fnmadd.d">;
99 def FADD_D : FPALUD_rr_frm<0b0000001, "fadd.d">;
100 def : FPALUDDynFrmAlias<FADD_D, "fadd.d">;
101 def FSUB_D : FPALUD_rr_frm<0b0000101, "fsub.d">;
102 def : FPALUDDynFrmAlias<FSUB_D, "fsub.d">;
103 def FMUL_D : FPALUD_rr_frm<0b0001001, "fmul.d">;
104 def : FPALUDDynFrmAlias<FMUL_D, "fmul.d">;
105 def FDIV_D : FPALUD_rr_frm<0b0001101, "fdiv.d">;
106 def : FPALUDDynFrmAlias<FDIV_D, "fdiv.d">;
108 def FSQRT_D : FPUnaryOp_r_frm<0b0101101, FPR64, FPR64, "fsqrt.d">,
109 Sched<[WriteFSqrt32, ReadFSqrt32]> {
112 def : FPUnaryOpDynFrmAlias<FSQRT_D, "fsqrt.d", FPR64, FPR64>;
114 def FSGNJ_D : FPALUD_rr<0b0010001, 0b000, "fsgnj.d">;
115 def FSGNJN_D : FPALUD_rr<0b0010001, 0b001, "fsgnjn.d">;
116 def FSGNJX_D : FPALUD_rr<0b0010001, 0b010, "fsgnjx.d">;
117 def FMIN_D : FPALUD_rr<0b0010101, 0b000, "fmin.d">;
118 def FMAX_D : FPALUD_rr<0b0010101, 0b001, "fmax.d">;
120 def FCVT_S_D : FPUnaryOp_r_frm<0b0100000, FPR32, FPR64, "fcvt.s.d">,
121 Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]> {
124 def : FPUnaryOpDynFrmAlias<FCVT_S_D, "fcvt.s.d", FPR32, FPR64>;
126 def FCVT_D_S : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR32, "fcvt.d.s">,
127 Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]> {
131 def FEQ_D : FPCmpD_rr<0b010, "feq.d">;
132 def FLT_D : FPCmpD_rr<0b001, "flt.d">;
133 def FLE_D : FPCmpD_rr<0b000, "fle.d">;
135 def FCLASS_D : FPUnaryOp_r<0b1110001, 0b001, GPR, FPR64, "fclass.d">,
136 Sched<[WriteFClass64, ReadFClass64]> {
140 def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.w.d">,
141 Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]> {
144 def : FPUnaryOpDynFrmAlias<FCVT_W_D, "fcvt.w.d", GPR, FPR64>;
146 def FCVT_WU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.wu.d">,
147 Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]> {
150 def : FPUnaryOpDynFrmAlias<FCVT_WU_D, "fcvt.wu.d", GPR, FPR64>;
152 def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w">,
153 Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]> {
157 def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu">,
158 Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]> {
161 } // Predicates = [HasStdExtD]
163 let Predicates = [HasStdExtD, IsRV64] in {
164 def FCVT_L_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.l.d">,
165 Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]> {
168 def : FPUnaryOpDynFrmAlias<FCVT_L_D, "fcvt.l.d", GPR, FPR64>;
170 def FCVT_LU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.lu.d">,
171 Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]> {
174 def : FPUnaryOpDynFrmAlias<FCVT_LU_D, "fcvt.lu.d", GPR, FPR64>;
176 def FMV_X_D : FPUnaryOp_r<0b1110001, 0b000, GPR, FPR64, "fmv.x.d">,
177 Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]> {
181 def FCVT_D_L : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.l">,
182 Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]> {
185 def : FPUnaryOpDynFrmAlias<FCVT_D_L, "fcvt.d.l", FPR64, GPR>;
187 def FCVT_D_LU : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.lu">,
188 Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]> {
191 def : FPUnaryOpDynFrmAlias<FCVT_D_LU, "fcvt.d.lu", FPR64, GPR>;
193 def FMV_D_X : FPUnaryOp_r<0b1111001, 0b000, FPR64, GPR, "fmv.d.x">,
194 Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]> {
197 } // Predicates = [HasStdExtD, IsRV64]
199 //===----------------------------------------------------------------------===//
200 // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
201 //===----------------------------------------------------------------------===//
203 let Predicates = [HasStdExtD] in {
204 def : InstAlias<"fld $rd, (${rs1})", (FLD FPR64:$rd, GPR:$rs1, 0), 0>;
205 def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>;
207 def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
208 def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
209 def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
211 // fgt.d/fge.d are recognised by the GNU assembler but the canonical
212 // flt.d/fle.d forms will always be printed. Therefore, set a zero weight.
213 def : InstAlias<"fgt.d $rd, $rs, $rt",
214 (FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
215 def : InstAlias<"fge.d $rd, $rs, $rt",
216 (FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
218 def PseudoFLD : PseudoFloatLoad<"fld", FPR64>;
219 def PseudoFSD : PseudoStore<"fsd", FPR64>;
220 } // Predicates = [HasStdExtD]
222 //===----------------------------------------------------------------------===//
223 // Pseudo-instructions and codegen patterns
224 //===----------------------------------------------------------------------===//
226 class PatFpr64Fpr64<SDPatternOperator OpNode, RVInstR Inst>
227 : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2)>;
229 class PatFpr64Fpr64DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
230 : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2, 0b111)>;
232 let Predicates = [HasStdExtD] in {
234 /// Float conversion operations
236 // f64 -> f32, f32 -> f64
237 def : Pat<(fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, 0b111)>;
238 def : Pat<(fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1)>;
240 // [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so
241 // are defined later.
243 /// Float arithmetic operations
245 def : PatFpr64Fpr64DynFrm<fadd, FADD_D>;
246 def : PatFpr64Fpr64DynFrm<fsub, FSUB_D>;
247 def : PatFpr64Fpr64DynFrm<fmul, FMUL_D>;
248 def : PatFpr64Fpr64DynFrm<fdiv, FDIV_D>;
250 def : Pat<(fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b111)>;
252 def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>;
253 def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>;
255 def : PatFpr64Fpr64<fcopysign, FSGNJ_D>;
256 def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>;
257 def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2))>;
258 def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2,
261 // fmadd: rs1 * rs2 + rs3
262 def : Pat<(fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),
263 (FMADD_D $rs1, $rs2, $rs3, 0b111)>;
265 // fmsub: rs1 * rs2 - rs3
266 def : Pat<(fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),
267 (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
269 // fnmsub: -rs1 * rs2 + rs3
270 def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3),
271 (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
273 // fnmadd: -rs1 * rs2 - rs3
274 def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)),
275 (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
277 // The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the
278 // canonical NaN when giving a signaling NaN. This doesn't match the LLVM
279 // behaviour (see https://bugs.llvm.org/show_bug.cgi?id=27363). However, the
280 // draft 2.3 ISA spec changes the definition of fmin and fmax in a way that
281 // matches LLVM's fminnum and fmaxnum
282 // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
283 def : PatFpr64Fpr64<fminnum, FMIN_D>;
284 def : PatFpr64Fpr64<fmaxnum, FMAX_D>;
288 def : PatFpr64Fpr64<seteq, FEQ_D>;
289 def : PatFpr64Fpr64<setoeq, FEQ_D>;
290 def : PatFpr64Fpr64<setlt, FLT_D>;
291 def : PatFpr64Fpr64<setolt, FLT_D>;
292 def : PatFpr64Fpr64<setle, FLE_D>;
293 def : PatFpr64Fpr64<setole, FLE_D>;
295 // Define pattern expansions for setcc operations which aren't directly
296 // handled by a RISC-V instruction and aren't expanded in the SelectionDAG
299 def : Pat<(seto FPR64:$rs1, FPR64:$rs2),
300 (AND (FEQ_D FPR64:$rs1, FPR64:$rs1),
301 (FEQ_D FPR64:$rs2, FPR64:$rs2))>;
303 def : Pat<(setuo FPR64:$rs1, FPR64:$rs2),
304 (SLTIU (AND (FEQ_D FPR64:$rs1, FPR64:$rs1),
305 (FEQ_D FPR64:$rs2, FPR64:$rs2)),
308 def Select_FPR64_Using_CC_GPR : SelectCC_rrirr<FPR64, GPR>;
312 defm : LdPat<load, FLD>;
316 defm : StPat<store, FSD, FPR64>;
318 /// Pseudo-instructions needed for the soft-float ABI with RV32D
320 // Moves two GPRs to an FPR.
321 let usesCustomInserter = 1 in
322 def BuildPairF64Pseudo
323 : Pseudo<(outs FPR64:$dst), (ins GPR:$src1, GPR:$src2),
324 [(set FPR64:$dst, (RISCVBuildPairF64 GPR:$src1, GPR:$src2))]>;
326 // Moves an FPR to two GPRs.
327 let usesCustomInserter = 1 in
329 : Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64:$src),
330 [(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64:$src))]>;
332 } // Predicates = [HasStdExtD]
334 let Predicates = [HasStdExtD, IsRV32] in {
335 // double->[u]int. Round-to-zero must be used.
336 def : Pat<(fp_to_sint FPR64:$rs1), (FCVT_W_D FPR64:$rs1, 0b001)>;
337 def : Pat<(fp_to_uint FPR64:$rs1), (FCVT_WU_D FPR64:$rs1, 0b001)>;
340 def : Pat<(sint_to_fp GPR:$rs1), (FCVT_D_W GPR:$rs1)>;
341 def : Pat<(uint_to_fp GPR:$rs1), (FCVT_D_WU GPR:$rs1)>;
342 } // Predicates = [HasStdExtD, IsRV32]
344 let Predicates = [HasStdExtD, IsRV64] in {
345 def : Pat<(bitconvert GPR:$rs1), (FMV_D_X GPR:$rs1)>;
346 def : Pat<(bitconvert FPR64:$rs1), (FMV_X_D FPR64:$rs1)>;
348 // FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe
349 // because fpto[u|s]i produce poison if the value can't fit into the target.
350 // We match the single case below because fcvt.wu.d sign-extends its result so
351 // is cheaper than fcvt.lu.d+sext.w.
352 def : Pat<(sext_inreg (zexti32 (fp_to_uint FPR64:$rs1)), i32),
353 (FCVT_WU_D $rs1, 0b001)>;
356 def : Pat<(sint_to_fp (sext_inreg GPR:$rs1, i32)), (FCVT_D_W $rs1)>;
357 def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_D_WU $rs1)>;
359 def : Pat<(fp_to_sint FPR64:$rs1), (FCVT_L_D FPR64:$rs1, 0b001)>;
360 def : Pat<(fp_to_uint FPR64:$rs1), (FCVT_LU_D FPR64:$rs1, 0b001)>;
362 // [u]int64->fp. Match GCC and default to using dynamic rounding mode.
363 def : Pat<(sint_to_fp GPR:$rs1), (FCVT_D_L GPR:$rs1, 0b111)>;
364 def : Pat<(uint_to_fp GPR:$rs1), (FCVT_D_LU GPR:$rs1, 0b111)>;
365 } // Predicates = [HasStdExtD, IsRV64]