contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoD.td

   1 //===-- RISCVInstrInfoD.td - RISC-V 'D' instructions -------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file describes the RISC-V instructions from the standard 'D',
  10 // Double-Precision Floating-Point instruction set extension.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // RISC-V specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17
  18 def SDT_RISCVBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
  19                                                  SDTCisVT<1, i32>,
  20                                                  SDTCisSameAs<1, 2>]>;
  21 def SDT_RISCVSplitF64     : SDTypeProfile<2, 1, [SDTCisVT<0, i32>,
  22                                                  SDTCisVT<1, i32>,
  23                                                  SDTCisVT<2, f64>]>;
  24
  25 def RISCVBuildPairF64 : SDNode<"RISCVISD::BuildPairF64", SDT_RISCVBuildPairF64>;
  26 def RISCVSplitF64     : SDNode<"RISCVISD::SplitF64", SDT_RISCVSplitF64>;
  27
  28 //===----------------------------------------------------------------------===//
  29 // Instruction Class Templates
  30 //===----------------------------------------------------------------------===//
  31
  32 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
  33 class FPFMAD_rrr_frm<RISCVOpcode opcode, string opcodestr>
  34     : RVInstR4<0b01, opcode, (outs FPR64:$rd),
  35                (ins FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, frmarg:$funct3),
  36                 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
  37
  38 class FPFMADDynFrmAlias<FPFMAD_rrr_frm Inst, string OpcodeStr>
  39     : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
  40                 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
  41
  42 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
  43 class FPALUD_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
  44     : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR64:$rd),
  45               (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">;
  46
  47 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
  48 class FPALUD_rr_frm<bits<7> funct7, string opcodestr>
  49     : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR64:$rd),
  50                 (ins FPR64:$rs1, FPR64:$rs2, frmarg:$funct3), opcodestr,
  51                  "$rd, $rs1, $rs2, $funct3">;
  52
  53 class FPALUDDynFrmAlias<FPALUD_rr_frm Inst, string OpcodeStr>
  54     : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
  55                 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, 0b111)>;
  56
  57 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
  58 class FPCmpD_rr<bits<3> funct3, string opcodestr>
  59     : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd),
  60               (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">,
  61       Sched<[WriteFCmp64, ReadFCmp64, ReadFCmp64]>;
  62
  63 //===----------------------------------------------------------------------===//
  64 // Instructions
  65 //===----------------------------------------------------------------------===//
  66
  67 let Predicates = [HasStdExtD] in {
  68
  69 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
  70 def FLD : RVInstI<0b011, OPC_LOAD_FP, (outs FPR64:$rd),
  71                   (ins GPR:$rs1, simm12:$imm12),
  72                   "fld", "$rd, ${imm12}(${rs1})">,
  73           Sched<[WriteFLD64, ReadFMemBase]>;
  74
  75 // Operands for stores are in the order srcreg, base, offset rather than
  76 // reflecting the order these fields are specified in the instruction
  77 // encoding.
  78 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
  79 def FSD : RVInstS<0b011, OPC_STORE_FP, (outs),
  80                   (ins FPR64:$rs2, GPR:$rs1, simm12:$imm12),
  81                    "fsd", "$rs2, ${imm12}(${rs1})">,
  82           Sched<[WriteFST64, ReadStoreData, ReadFMemBase]>;
  83
  84 def FMADD_D  : FPFMAD_rrr_frm<OPC_MADD, "fmadd.d">,
  85                Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
  86 def          : FPFMADDynFrmAlias<FMADD_D, "fmadd.d">;
  87 def FMSUB_D  : FPFMAD_rrr_frm<OPC_MSUB, "fmsub.d">,
  88                Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
  89 def          : FPFMADDynFrmAlias<FMSUB_D, "fmsub.d">;
  90 def FNMSUB_D : FPFMAD_rrr_frm<OPC_NMSUB, "fnmsub.d">,
  91                Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
  92 def          : FPFMADDynFrmAlias<FNMSUB_D, "fnmsub.d">;
  93 def FNMADD_D : FPFMAD_rrr_frm<OPC_NMADD, "fnmadd.d">,
  94                Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
  95 def          : FPFMADDynFrmAlias<FNMADD_D, "fnmadd.d">;
  96
  97 def FADD_D : FPALUD_rr_frm<0b0000001, "fadd.d">,
  98              Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
  99 def        : FPALUDDynFrmAlias<FADD_D, "fadd.d">;
 100 def FSUB_D : FPALUD_rr_frm<0b0000101, "fsub.d">,
 101              Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
 102 def        : FPALUDDynFrmAlias<FSUB_D, "fsub.d">;
 103 def FMUL_D : FPALUD_rr_frm<0b0001001, "fmul.d">,
 104              Sched<[WriteFMul64, ReadFMul64, ReadFMul64]>;
 105 def        : FPALUDDynFrmAlias<FMUL_D, "fmul.d">;
 106 def FDIV_D : FPALUD_rr_frm<0b0001101, "fdiv.d">,
 107              Sched<[WriteFDiv64, ReadFDiv64, ReadFDiv64]>;
 108 def        : FPALUDDynFrmAlias<FDIV_D, "fdiv.d">;
 109
 110 def FSQRT_D : FPUnaryOp_r_frm<0b0101101, FPR64, FPR64, "fsqrt.d">,
 111               Sched<[WriteFSqrt64, ReadFSqrt64]> {
 112   let rs2 = 0b00000;
 113 }
 114 def         : FPUnaryOpDynFrmAlias<FSQRT_D, "fsqrt.d", FPR64, FPR64>;
 115
 116 def FSGNJ_D  : FPALUD_rr<0b0010001, 0b000, "fsgnj.d">,
 117                Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>;
 118 def FSGNJN_D : FPALUD_rr<0b0010001, 0b001, "fsgnjn.d">,
 119                Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>;
 120 def FSGNJX_D : FPALUD_rr<0b0010001, 0b010, "fsgnjx.d">,
 121                Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>;
 122 def FMIN_D   : FPALUD_rr<0b0010101, 0b000, "fmin.d">,
 123                Sched<[WriteFMinMax64, ReadFMinMax64, ReadFMinMax64]>;
 124 def FMAX_D   : FPALUD_rr<0b0010101, 0b001, "fmax.d">,
 125                Sched<[WriteFMinMax64, ReadFMinMax64, ReadFMinMax64]>;
 126
 127 def FCVT_S_D : FPUnaryOp_r_frm<0b0100000, FPR32, FPR64, "fcvt.s.d">,
 128                Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]> {
 129   let rs2 = 0b00001;
 130 }
 131 def          : FPUnaryOpDynFrmAlias<FCVT_S_D, "fcvt.s.d", FPR32, FPR64>;
 132
 133 def FCVT_D_S : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR32, "fcvt.d.s">,
 134                Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]> {
 135   let rs2 = 0b00000;
 136 }
 137
 138 def FEQ_D : FPCmpD_rr<0b010, "feq.d">;
 139 def FLT_D : FPCmpD_rr<0b001, "flt.d">;
 140 def FLE_D : FPCmpD_rr<0b000, "fle.d">;
 141
 142 def FCLASS_D : FPUnaryOp_r<0b1110001, 0b001, GPR, FPR64, "fclass.d">,
 143                Sched<[WriteFClass64, ReadFClass64]> {
 144   let rs2 = 0b00000;
 145 }
 146
 147 def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.w.d">,
 148                Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]> {
 149   let rs2 = 0b00000;
 150 }
 151 def          : FPUnaryOpDynFrmAlias<FCVT_W_D, "fcvt.w.d", GPR, FPR64>;
 152
 153 def FCVT_WU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.wu.d">,
 154                 Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]> {
 155   let rs2 = 0b00001;
 156 }
 157 def           : FPUnaryOpDynFrmAlias<FCVT_WU_D, "fcvt.wu.d", GPR, FPR64>;
 158
 159 def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w">,
 160                Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]> {
 161   let rs2 = 0b00000;
 162 }
 163
 164 def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu">,
 165                 Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]> {
 166   let rs2 = 0b00001;
 167 }
 168 } // Predicates = [HasStdExtD]
 169
 170 let Predicates = [HasStdExtD, IsRV64] in {
 171 def FCVT_L_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.l.d">,
 172                Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]> {
 173   let rs2 = 0b00010;
 174 }
 175 def          : FPUnaryOpDynFrmAlias<FCVT_L_D, "fcvt.l.d", GPR, FPR64>;
 176
 177 def FCVT_LU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.lu.d">,
 178                 Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]> {
 179   let rs2 = 0b00011;
 180 }
 181 def           : FPUnaryOpDynFrmAlias<FCVT_LU_D, "fcvt.lu.d", GPR, FPR64>;
 182
 183 def FMV_X_D : FPUnaryOp_r<0b1110001, 0b000, GPR, FPR64, "fmv.x.d">,
 184               Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]> {
 185   let rs2 = 0b00000;
 186 }
 187
 188 def FCVT_D_L : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.l">,
 189                Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]> {
 190   let rs2 = 0b00010;
 191 }
 192 def          : FPUnaryOpDynFrmAlias<FCVT_D_L, "fcvt.d.l", FPR64, GPR>;
 193
 194 def FCVT_D_LU : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.lu">,
 195                 Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]> {
 196   let rs2 = 0b00011;
 197 }
 198 def           : FPUnaryOpDynFrmAlias<FCVT_D_LU, "fcvt.d.lu", FPR64, GPR>;
 199
 200 def FMV_D_X : FPUnaryOp_r<0b1111001, 0b000, FPR64, GPR, "fmv.d.x">,
 201               Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]> {
 202   let rs2 = 0b00000;
 203 }
 204 } // Predicates = [HasStdExtD, IsRV64]
 205
 206 //===----------------------------------------------------------------------===//
 207 // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
 208 //===----------------------------------------------------------------------===//
 209
 210 let Predicates = [HasStdExtD] in {
 211 def : InstAlias<"fld $rd, (${rs1})",  (FLD FPR64:$rd,  GPR:$rs1, 0), 0>;
 212 def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>;
 213
 214 def : InstAlias<"fmv.d $rd, $rs",  (FSGNJ_D  FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
 215 def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
 216 def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
 217
 218 // fgt.d/fge.d are recognised by the GNU assembler but the canonical
 219 // flt.d/fle.d forms will always be printed. Therefore, set a zero weight.
 220 def : InstAlias<"fgt.d $rd, $rs, $rt",
 221                 (FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
 222 def : InstAlias<"fge.d $rd, $rs, $rt",
 223                 (FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
 224
 225 def PseudoFLD  : PseudoFloatLoad<"fld", FPR64>;
 226 def PseudoFSD  : PseudoStore<"fsd", FPR64>;
 227 } // Predicates = [HasStdExtD]
 228
 229 //===----------------------------------------------------------------------===//
 230 // Pseudo-instructions and codegen patterns
 231 //===----------------------------------------------------------------------===//
 232
 233 class PatFpr64Fpr64<SDPatternOperator OpNode, RVInstR Inst>
 234     : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2)>;
 235
 236 class PatFpr64Fpr64DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
 237     : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2, 0b111)>;
 238
 239 let Predicates = [HasStdExtD] in {
 240
 241 /// Float conversion operations
 242
 243 // f64 -> f32, f32 -> f64
 244 def : Pat<(fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, 0b111)>;
 245 def : Pat<(fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1)>;
 246
 247 // [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so
 248 // are defined later.
 249
 250 /// Float arithmetic operations
 251
 252 def : PatFpr64Fpr64DynFrm<fadd, FADD_D>;
 253 def : PatFpr64Fpr64DynFrm<fsub, FSUB_D>;
 254 def : PatFpr64Fpr64DynFrm<fmul, FMUL_D>;
 255 def : PatFpr64Fpr64DynFrm<fdiv, FDIV_D>;
 256
 257 def : Pat<(fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b111)>;
 258
 259 def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>;
 260 def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>;
 261
 262 def : PatFpr64Fpr64<fcopysign, FSGNJ_D>;
 263 def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>;
 264 def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2))>;
 265 def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2,
 266                                                               0b111))>;
 267
 268 // fmadd: rs1 * rs2 + rs3
 269 def : Pat<(fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),
 270           (FMADD_D $rs1, $rs2, $rs3, 0b111)>;
 271
 272 // fmsub: rs1 * rs2 - rs3
 273 def : Pat<(fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),
 274           (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
 275
 276 // fnmsub: -rs1 * rs2 + rs3
 277 def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3),
 278           (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
 279
 280 // fnmadd: -rs1 * rs2 - rs3
 281 def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)),
 282           (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
 283
 284 // The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the
 285 // canonical NaN when giving a signaling NaN. This doesn't match the LLVM
 286 // behaviour (see https://bugs.llvm.org/show_bug.cgi?id=27363). However, the
 287 // draft 2.3 ISA spec changes the definition of fmin and fmax in a way that
 288 // matches LLVM's fminnum and fmaxnum
 289 // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
 290 def : PatFpr64Fpr64<fminnum, FMIN_D>;
 291 def : PatFpr64Fpr64<fmaxnum, FMAX_D>;
 292
 293 /// Setcc
 294
 295 def : PatFpr64Fpr64<seteq, FEQ_D>;
 296 def : PatFpr64Fpr64<setoeq, FEQ_D>;
 297 def : PatFpr64Fpr64<setlt, FLT_D>;
 298 def : PatFpr64Fpr64<setolt, FLT_D>;
 299 def : PatFpr64Fpr64<setle, FLE_D>;
 300 def : PatFpr64Fpr64<setole, FLE_D>;
 301
 302 // Define pattern expansions for setcc operations which aren't directly
 303 // handled by a RISC-V instruction and aren't expanded in the SelectionDAG
 304 // Legalizer.
 305
 306 def : Pat<(seto FPR64:$rs1, FPR64:$rs2),
 307           (AND (FEQ_D FPR64:$rs1, FPR64:$rs1),
 308                (FEQ_D FPR64:$rs2, FPR64:$rs2))>;
 309 def : Pat<(seto FPR64:$rs1, FPR64:$rs1),
 310           (FEQ_D $rs1, $rs1)>;
 311
 312 def : Pat<(setuo FPR64:$rs1, FPR64:$rs2),
 313           (SLTIU (AND (FEQ_D FPR64:$rs1, FPR64:$rs1),
 314                       (FEQ_D FPR64:$rs2, FPR64:$rs2)),
 315                  1)>;
 316 def : Pat<(setuo FPR64:$rs1, FPR64:$rs1),
 317           (SLTIU (FEQ_D $rs1, $rs1), 1)>;
 318
 319 def Select_FPR64_Using_CC_GPR : SelectCC_rrirr<FPR64, GPR>;
 320
 321 /// Loads
 322
 323 defm : LdPat<load, FLD>;
 324
 325 /// Stores
 326
 327 defm : StPat<store, FSD, FPR64>;
 328
 329 /// Pseudo-instructions needed for the soft-float ABI with RV32D
 330
 331 // Moves two GPRs to an FPR.
 332 let usesCustomInserter = 1 in
 333 def BuildPairF64Pseudo
 334     : Pseudo<(outs FPR64:$dst), (ins GPR:$src1, GPR:$src2),
 335              [(set FPR64:$dst, (RISCVBuildPairF64 GPR:$src1, GPR:$src2))]>;
 336
 337 // Moves an FPR to two GPRs.
 338 let usesCustomInserter = 1 in
 339 def SplitF64Pseudo
 340     : Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64:$src),
 341              [(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64:$src))]>;
 342
 343 } // Predicates = [HasStdExtD]
 344
 345 let Predicates = [HasStdExtD, IsRV32] in {
 346
 347 /// Float constants
 348 def : Pat<(f64 (fpimm0)), (FCVT_D_W X0)>;
 349
 350 // double->[u]int. Round-to-zero must be used.
 351 def : Pat<(fp_to_sint FPR64:$rs1), (FCVT_W_D FPR64:$rs1, 0b001)>;
 352 def : Pat<(fp_to_uint FPR64:$rs1), (FCVT_WU_D FPR64:$rs1, 0b001)>;
 353
 354 // [u]int->double.
 355 def : Pat<(sint_to_fp GPR:$rs1), (FCVT_D_W GPR:$rs1)>;
 356 def : Pat<(uint_to_fp GPR:$rs1), (FCVT_D_WU GPR:$rs1)>;
 357 } // Predicates = [HasStdExtD, IsRV32]
 358
 359 let Predicates = [HasStdExtD, IsRV64] in {
 360
 361 /// Float constants
 362 def : Pat<(f64 (fpimm0)), (FMV_D_X X0)>;
 363
 364 def : Pat<(bitconvert GPR:$rs1), (FMV_D_X GPR:$rs1)>;
 365 def : Pat<(bitconvert FPR64:$rs1), (FMV_X_D FPR64:$rs1)>;
 366
 367 // FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe
 368 // because fpto[u|s]i produce poison if the value can't fit into the target.
 369 // We match the single case below because fcvt.wu.d sign-extends its result so
 370 // is cheaper than fcvt.lu.d+sext.w.
 371 def : Pat<(sext_inreg (zexti32 (fp_to_uint FPR64:$rs1)), i32),
 372           (FCVT_WU_D $rs1, 0b001)>;
 373
 374 // [u]int32->fp
 375 def : Pat<(sint_to_fp (sext_inreg GPR:$rs1, i32)), (FCVT_D_W $rs1)>;
 376 def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_D_WU $rs1)>;
 377
 378 def : Pat<(fp_to_sint FPR64:$rs1), (FCVT_L_D FPR64:$rs1, 0b001)>;
 379 def : Pat<(fp_to_uint FPR64:$rs1), (FCVT_LU_D FPR64:$rs1, 0b001)>;
 380
 381 // [u]int64->fp. Match GCC and default to using dynamic rounding mode.
 382 def : Pat<(sint_to_fp GPR:$rs1), (FCVT_D_L GPR:$rs1, 0b111)>;
 383 def : Pat<(uint_to_fp GPR:$rs1), (FCVT_D_LU GPR:$rs1, 0b111)>;
 384 } // Predicates = [HasStdExtD, IsRV64]