1 //==- RISCVSchedRocket.td - Rocket Scheduling Definitions ----*- tablegen -*-=//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // ===---------------------------------------------------------------------===//
10 // The following definitions describe the simpler per-operand machine model.
11 // This works with MachineScheduler. See MCSchedule.h for details.
13 // Rocket machine model for scheduling and other instruction cost heuristics.
14 def RocketModel : SchedMachineModel {
15 let MicroOpBufferSize = 0; // Rocket is in-order.
16 let IssueWidth = 1; // 1 micro-op is dispatched per cycle.
18 let MispredictPenalty = 3;
19 let CompleteModel = false;
20 let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
21 HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
22 HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
23 HasVInstructions, HasVInstructionsI64];
26 //===----------------------------------------------------------------------===//
27 // Define each kind of processor resource and number available.
29 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
30 // Rocket is in-order.
32 let BufferSize = 0 in {
33 def RocketUnitALU : ProcResource<1>; // Int ALU
34 def RocketUnitIMul : ProcResource<1>; // Int Multiply
35 def RocketUnitMem : ProcResource<1>; // Load/Store
36 def RocketUnitB : ProcResource<1>; // Branch
38 def RocketUnitFPALU : ProcResource<1>; // FP ALU
41 let BufferSize = 1 in {
42 def RocketUnitIDiv : ProcResource<1>; // Int Division
43 def RocketUnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt
46 //===----------------------------------------------------------------------===//
48 let SchedModel = RocketModel in {
51 def : WriteRes<WriteJmp, [RocketUnitB]>;
52 def : WriteRes<WriteJal, [RocketUnitB]>;
53 def : WriteRes<WriteJalr, [RocketUnitB]>;
54 def : WriteRes<WriteJmpReg, [RocketUnitB]>;
56 // Integer arithmetic and logic
57 def : WriteRes<WriteIALU32, [RocketUnitALU]>;
58 def : WriteRes<WriteIALU, [RocketUnitALU]>;
59 def : WriteRes<WriteShiftImm32, [RocketUnitALU]>;
60 def : WriteRes<WriteShiftImm, [RocketUnitALU]>;
61 def : WriteRes<WriteShiftReg32, [RocketUnitALU]>;
62 def : WriteRes<WriteShiftReg, [RocketUnitALU]>;
64 // Integer multiplication
66 def : WriteRes<WriteIMul, [RocketUnitIMul]>;
67 def : WriteRes<WriteIMul32, [RocketUnitIMul]>;
71 // Worst case latency is used.
72 def : WriteRes<WriteIDiv32, [RocketUnitIDiv]> {
74 let ResourceCycles = [34];
76 def : WriteRes<WriteIDiv, [RocketUnitIDiv]> {
78 let ResourceCycles = [33];
82 def : WriteRes<WriteSTB, [RocketUnitMem]>;
83 def : WriteRes<WriteSTH, [RocketUnitMem]>;
84 def : WriteRes<WriteSTW, [RocketUnitMem]>;
85 def : WriteRes<WriteSTD, [RocketUnitMem]>;
86 def : WriteRes<WriteFST32, [RocketUnitMem]>;
87 def : WriteRes<WriteFST64, [RocketUnitMem]>;
90 def : WriteRes<WriteLDB, [RocketUnitMem]>;
91 def : WriteRes<WriteLDH, [RocketUnitMem]>;
95 def : WriteRes<WriteLDW, [RocketUnitMem]>;
96 def : WriteRes<WriteLDWU, [RocketUnitMem]>;
97 def : WriteRes<WriteLDD, [RocketUnitMem]>;
98 def : WriteRes<WriteFLD32, [RocketUnitMem]>;
99 def : WriteRes<WriteFLD64, [RocketUnitMem]>;
102 def : WriteRes<WriteAtomicW, [RocketUnitMem]>;
103 def : WriteRes<WriteAtomicD, [RocketUnitMem]>;
105 def : WriteRes<WriteAtomicLDW, [RocketUnitMem]>;
106 def : WriteRes<WriteAtomicLDD, [RocketUnitMem]>;
109 def : WriteRes<WriteAtomicSTW, [RocketUnitMem]>;
110 def : WriteRes<WriteAtomicSTD, [RocketUnitMem]>;
114 def : WriteRes<WriteFALU32, [RocketUnitFPALU]>;
115 def : WriteRes<WriteFSGNJ32, [RocketUnitFPALU]>;
116 def : WriteRes<WriteFMinMax32, [RocketUnitFPALU]>;
121 def : WriteRes<WriteFALU64, [RocketUnitFPALU]>;
122 def : WriteRes<WriteFSGNJ64, [RocketUnitFPALU]>;
123 def : WriteRes<WriteFMinMax64, [RocketUnitFPALU]>;
128 def : WriteRes<WriteFCvtI32ToF32, [RocketUnitFPALU]>;
129 def : WriteRes<WriteFCvtI32ToF64, [RocketUnitFPALU]>;
130 def : WriteRes<WriteFCvtI64ToF32, [RocketUnitFPALU]>;
131 def : WriteRes<WriteFCvtI64ToF64, [RocketUnitFPALU]>;
132 def : WriteRes<WriteFCvtF32ToI32, [RocketUnitFPALU]>;
133 def : WriteRes<WriteFCvtF32ToI64, [RocketUnitFPALU]>;
134 def : WriteRes<WriteFCvtF64ToI32, [RocketUnitFPALU]>;
135 def : WriteRes<WriteFCvtF64ToI64, [RocketUnitFPALU]>;
136 def : WriteRes<WriteFCvtF32ToF64, [RocketUnitFPALU]>;
137 def : WriteRes<WriteFCvtF64ToF32, [RocketUnitFPALU]>;
139 def : WriteRes<WriteFClass32, [RocketUnitFPALU]>;
140 def : WriteRes<WriteFClass64, [RocketUnitFPALU]>;
141 def : WriteRes<WriteFCmp32, [RocketUnitFPALU]>;
142 def : WriteRes<WriteFCmp64, [RocketUnitFPALU]>;
143 def : WriteRes<WriteFMovF32ToI32, [RocketUnitFPALU]>;
144 def : WriteRes<WriteFMovI32ToF32, [RocketUnitFPALU]>;
145 def : WriteRes<WriteFMovF64ToI64, [RocketUnitFPALU]>;
146 def : WriteRes<WriteFMovI64ToF64, [RocketUnitFPALU]>;
151 def : WriteRes<WriteFMul32, [RocketUnitFPALU]>;
152 def : WriteRes<WriteFMA32, [RocketUnitFPALU]>;
156 def : WriteRes<WriteFMul64, [RocketUnitFPALU]>;
157 def : WriteRes<WriteFMA64, [RocketUnitFPALU]>;
161 // FP division unit on Rocket is not pipelined, so set resource cycles to latency.
162 let Latency = 20, ResourceCycles = [20] in {
163 def : WriteRes<WriteFDiv32, [RocketUnitFPDivSqrt]>;
164 def : WriteRes<WriteFDiv64, [RocketUnitFPDivSqrt]>;
167 // FP square root unit on Rocket is not pipelined, so set resource cycles to latency.
168 def : WriteRes<WriteFSqrt32, [RocketUnitFPDivSqrt]> { let Latency = 20;
169 let ResourceCycles = [20]; }
170 def : WriteRes<WriteFSqrt64, [RocketUnitFPDivSqrt]> { let Latency = 25;
171 let ResourceCycles = [25]; }
174 def : WriteRes<WriteCSR, []>;
175 def : WriteRes<WriteNop, []>;
177 def : InstRW<[WriteIALU], (instrs COPY)>;
179 //===----------------------------------------------------------------------===//
180 // Bypass and advance
181 def : ReadAdvance<ReadJmp, 0>;
182 def : ReadAdvance<ReadJalr, 0>;
183 def : ReadAdvance<ReadCSR, 0>;
184 def : ReadAdvance<ReadStoreData, 0>;
185 def : ReadAdvance<ReadMemBase, 0>;
186 def : ReadAdvance<ReadIALU, 0>;
187 def : ReadAdvance<ReadIALU32, 0>;
188 def : ReadAdvance<ReadShiftImm, 0>;
189 def : ReadAdvance<ReadShiftImm32, 0>;
190 def : ReadAdvance<ReadShiftReg, 0>;
191 def : ReadAdvance<ReadShiftReg32, 0>;
192 def : ReadAdvance<ReadIDiv, 0>;
193 def : ReadAdvance<ReadIDiv32, 0>;
194 def : ReadAdvance<ReadIMul, 0>;
195 def : ReadAdvance<ReadIMul32, 0>;
196 def : ReadAdvance<ReadAtomicWA, 0>;
197 def : ReadAdvance<ReadAtomicWD, 0>;
198 def : ReadAdvance<ReadAtomicDA, 0>;
199 def : ReadAdvance<ReadAtomicDD, 0>;
200 def : ReadAdvance<ReadAtomicLDW, 0>;
201 def : ReadAdvance<ReadAtomicLDD, 0>;
202 def : ReadAdvance<ReadAtomicSTW, 0>;
203 def : ReadAdvance<ReadAtomicSTD, 0>;
204 def : ReadAdvance<ReadFMemBase, 0>;
205 def : ReadAdvance<ReadFALU32, 0>;
206 def : ReadAdvance<ReadFALU64, 0>;
207 def : ReadAdvance<ReadFMul32, 0>;
208 def : ReadAdvance<ReadFMA32, 0>;
209 def : ReadAdvance<ReadFMul64, 0>;
210 def : ReadAdvance<ReadFMA64, 0>;
211 def : ReadAdvance<ReadFDiv32, 0>;
212 def : ReadAdvance<ReadFDiv64, 0>;
213 def : ReadAdvance<ReadFSqrt32, 0>;
214 def : ReadAdvance<ReadFSqrt64, 0>;
215 def : ReadAdvance<ReadFCmp32, 0>;
216 def : ReadAdvance<ReadFCmp64, 0>;
217 def : ReadAdvance<ReadFSGNJ32, 0>;
218 def : ReadAdvance<ReadFSGNJ64, 0>;
219 def : ReadAdvance<ReadFMinMax32, 0>;
220 def : ReadAdvance<ReadFMinMax64, 0>;
221 def : ReadAdvance<ReadFCvtF32ToI32, 0>;
222 def : ReadAdvance<ReadFCvtF32ToI64, 0>;
223 def : ReadAdvance<ReadFCvtF64ToI32, 0>;
224 def : ReadAdvance<ReadFCvtF64ToI64, 0>;
225 def : ReadAdvance<ReadFCvtI32ToF32, 0>;
226 def : ReadAdvance<ReadFCvtI32ToF64, 0>;
227 def : ReadAdvance<ReadFCvtI64ToF32, 0>;
228 def : ReadAdvance<ReadFCvtI64ToF64, 0>;
229 def : ReadAdvance<ReadFCvtF32ToF64, 0>;
230 def : ReadAdvance<ReadFCvtF64ToF32, 0>;
231 def : ReadAdvance<ReadFMovF32ToI32, 0>;
232 def : ReadAdvance<ReadFMovI32ToF32, 0>;
233 def : ReadAdvance<ReadFMovF64ToI64, 0>;
234 def : ReadAdvance<ReadFMovI64ToF64, 0>;
235 def : ReadAdvance<ReadFClass32, 0>;
236 def : ReadAdvance<ReadFClass64, 0>;
238 //===----------------------------------------------------------------------===//
239 // Unsupported extensions
240 defm : UnsupportedSchedV;
241 defm : UnsupportedSchedZba;
242 defm : UnsupportedSchedZbb;
243 defm : UnsupportedSchedZbc;
244 defm : UnsupportedSchedZbs;
245 defm : UnsupportedSchedZbf;
246 defm : UnsupportedSchedZfh;