contrib/llvm-project/llvm/lib/Target/RISCV/RISCVSubtarget.cpp

   1 //===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the RISCV specific subclass of TargetSubtargetInfo.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "RISCVSubtarget.h"
  14 #include "RISCV.h"
  15 #include "RISCVCallLowering.h"
  16 #include "RISCVFrameLowering.h"
  17 #include "RISCVLegalizerInfo.h"
  18 #include "RISCVRegisterBankInfo.h"
  19 #include "RISCVTargetMachine.h"
  20 #include "llvm/Support/TargetRegistry.h"
  21
  22 using namespace llvm;
  23
  24 #define DEBUG_TYPE "riscv-subtarget"
  25
  26 #define GET_SUBTARGETINFO_TARGET_DESC
  27 #define GET_SUBTARGETINFO_CTOR
  28 #include "RISCVGenSubtargetInfo.inc"
  29
  30 void RISCVSubtarget::anchor() {}
  31
  32 RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
  33     const Triple &TT, StringRef CPU, StringRef FS, StringRef ABIName) {
  34   // Determine default and user-specified characteristics
  35   bool Is64Bit = TT.isArch64Bit();
  36   std::string CPUName = CPU;
  37   if (CPUName.empty())
  38     CPUName = Is64Bit ? "generic-rv64" : "generic-rv32";
  39   ParseSubtargetFeatures(CPUName, FS);
  40   if (Is64Bit) {
  41     XLenVT = MVT::i64;
  42     XLen = 64;
  43   }
  44
  45   TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
  46   RISCVFeatures::validate(TT, getFeatureBits());
  47   return *this;
  48 }
  49
  50 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
  51                                StringRef ABIName, const TargetMachine &TM)
  52     : RISCVGenSubtargetInfo(TT, CPU, FS),
  53       UserReservedRegister(RISCV::NUM_TARGET_REGS),
  54       FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),
  55       InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
  56   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
  57   Legalizer.reset(new RISCVLegalizerInfo(*this));
  58
  59   auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
  60   RegBankInfo.reset(RBI);
  61   InstSelector.reset(createRISCVInstructionSelector(
  62       *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
  63 }
  64
  65 const CallLowering *RISCVSubtarget::getCallLowering() const {
  66   return CallLoweringInfo.get();
  67 }
  68
  69 InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
  70   return InstSelector.get();
  71 }
  72
  73 const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
  74   return Legalizer.get();
  75 }
  76
  77 const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
  78   return RegBankInfo.get();
  79 }