1 //===-- RISCVTargetTransformInfo.cpp - RISC-V specific TTI ----------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 #include "RISCVTargetTransformInfo.h"
10 #include "Utils/RISCVMatInt.h"
11 #include "llvm/Analysis/TargetTransformInfo.h"
12 #include "llvm/CodeGen/BasicTTIImpl.h"
13 #include "llvm/CodeGen/TargetLowering.h"
16 #define DEBUG_TYPE "riscvtti"
18 int RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
19 assert(Ty->isIntegerTy() &&
20 "getIntImmCost can only estimate cost of materialising integers");
22 // We have a Zero register, so 0 is always free.
26 // Otherwise, we check how many instructions it will take to materialise.
27 const DataLayout &DL = getDataLayout();
28 return RISCVMatInt::getIntMatCost(Imm, DL.getTypeSizeInBits(Ty),
32 int RISCVTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
34 assert(Ty->isIntegerTy() &&
35 "getIntImmCost can only estimate cost of materialising integers");
37 // We have a Zero register, so 0 is always free.
41 // Some instructions in RISC-V can take a 12-bit immediate. Some of these are
42 // commutative, in others the immediate comes from a specific argument index.
43 bool Takes12BitImm = false;
44 unsigned ImmArgIdx = ~0U;
47 case Instruction::GetElementPtr:
48 // Never hoist any arguments to a GetElementPtr. CodeGenPrepare will
49 // split up large offsets in GEP into better parts than ConstantHoisting
52 case Instruction::Add:
53 case Instruction::And:
55 case Instruction::Xor:
56 case Instruction::Mul:
59 case Instruction::Sub:
60 case Instruction::Shl:
61 case Instruction::LShr:
62 case Instruction::AShr:
71 // Check immediate is the correct argument...
72 if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx) {
73 // ... and fits into the 12-bit immediate.
74 if (Imm.getMinSignedBits() <= 64 &&
75 getTLI()->isLegalAddImmediate(Imm.getSExtValue())) {
80 // Otherwise, use the full materialisation cost.
81 return getIntImmCost(Imm, Ty);
84 // By default, prevent hoisting.
88 int RISCVTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
89 const APInt &Imm, Type *Ty) {
90 // Prevent hoisting in unknown cases.