1 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains small standalone enum definitions for the RISCV target
10 // useful for the compiler back-end and the MC libraries.
12 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
16 #include "RISCVRegisterInfo.h"
17 #include "MCTargetDesc/RISCVMCTargetDesc.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/SubtargetFeature.h"
25 // RISCVII - This namespace holds all of the target specific flags that
26 // instruction info tracks. All definitions must match RISCVInstrFormats.td.
51 // RISC-V Specific Machine Operand Flags
67 // Used to differentiate between target-specific "direct" flags and "bitmask"
68 // flags. A machine operand can only have one "direct" flag, but can have
69 // multiple "bitmask" flags.
70 MO_DIRECT_FLAG_MASK = 15
72 } // namespace RISCVII
75 enum OperandType : unsigned {
76 OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
77 OPERAND_UIMM4 = OPERAND_FIRST_RISCV_IMM,
85 OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN
87 } // namespace RISCVOp
89 // Describes the predecessor/successor bits used in the FENCE instruction.
90 namespace RISCVFenceField {
99 // Describes the supported floating point rounding mode encodings.
100 namespace RISCVFPRndMode {
111 inline static StringRef roundingModeToString(RoundingMode RndMode) {
114 llvm_unreachable("Unknown floating point rounding mode");
115 case RISCVFPRndMode::RNE:
117 case RISCVFPRndMode::RTZ:
119 case RISCVFPRndMode::RDN:
121 case RISCVFPRndMode::RUP:
123 case RISCVFPRndMode::RMM:
125 case RISCVFPRndMode::DYN:
130 inline static RoundingMode stringToRoundingMode(StringRef Str) {
131 return StringSwitch<RoundingMode>(Str)
132 .Case("rne", RISCVFPRndMode::RNE)
133 .Case("rtz", RISCVFPRndMode::RTZ)
134 .Case("rdn", RISCVFPRndMode::RDN)
135 .Case("rup", RISCVFPRndMode::RUP)
136 .Case("rmm", RISCVFPRndMode::RMM)
137 .Case("dyn", RISCVFPRndMode::DYN)
138 .Default(RISCVFPRndMode::Invalid);
141 inline static bool isValidRoundingMode(unsigned Mode) {
145 case RISCVFPRndMode::RNE:
146 case RISCVFPRndMode::RTZ:
147 case RISCVFPRndMode::RDN:
148 case RISCVFPRndMode::RUP:
149 case RISCVFPRndMode::RMM:
150 case RISCVFPRndMode::DYN:
154 } // namespace RISCVFPRndMode
156 namespace RISCVSysReg {
160 // FIXME: add these additional fields when needed.
161 // Privilege Access: Read, Write, Read-Only.
162 // unsigned ReadWrite;
163 // Privilege Mode: User, System or Machine.
167 // Register number without the privilege bits.
169 FeatureBitset FeaturesRequired;
172 bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const {
173 // Not in 32-bit mode.
174 if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
176 // No required feature associated with the system register.
177 if (FeaturesRequired.none())
179 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
183 #define GET_SysRegsList_DECL
184 #include "RISCVGenSystemOperands.inc"
185 } // end namespace RISCVSysReg
200 // Returns the target ABI, or else a StringError if the requested ABIName is
201 // not supported for the given TT and FeatureBits combination.
202 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
205 ABI getTargetABI(StringRef ABIName);
207 // Returns the register used to hold the stack pointer after realignment.
210 } // namespace RISCVABI
212 namespace RISCVFeatures {
214 // Validates if the given combination of features are valid for the target
215 // triple. Exits with report_fatal_error if not.
216 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
218 } // namespace RISCVFeatures