contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZ.td

   1 //===-- SystemZ.td - Describe the SystemZ target machine -----*- tblgen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 //===----------------------------------------------------------------------===//
  10 // Target-independent interfaces which we are implementing
  11 //===----------------------------------------------------------------------===//
  12
  13 include "llvm/Target/Target.td"
  14
  15 //===----------------------------------------------------------------------===//
  16 // SystemZ subtarget features
  17 //===----------------------------------------------------------------------===//
  18
  19 include "SystemZFeatures.td"
  20
  21 //===----------------------------------------------------------------------===//
  22 // SystemZ subtarget scheduling models
  23 //===----------------------------------------------------------------------===//
  24
  25 include "SystemZSchedule.td"
  26
  27 //===----------------------------------------------------------------------===//
  28 // SystemZ supported processors
  29 //===----------------------------------------------------------------------===//
  30
  31 include "SystemZProcessors.td"
  32
  33 //===----------------------------------------------------------------------===//
  34 // Register file description
  35 //===----------------------------------------------------------------------===//
  36
  37 include "SystemZRegisterInfo.td"
  38
  39 //===----------------------------------------------------------------------===//
  40 // Calling convention description
  41 //===----------------------------------------------------------------------===//
  42
  43 include "SystemZCallingConv.td"
  44
  45 //===----------------------------------------------------------------------===//
  46 // Instruction descriptions
  47 //===----------------------------------------------------------------------===//
  48
  49 include "SystemZOperators.td"
  50 include "SystemZOperands.td"
  51 include "SystemZPatterns.td"
  52 include "SystemZInstrFormats.td"
  53 include "SystemZInstrInfo.td"
  54 include "SystemZInstrVector.td"
  55 include "SystemZInstrFP.td"
  56 include "SystemZInstrHFP.td"
  57 include "SystemZInstrDFP.td"
  58 include "SystemZInstrSystem.td"
  59
  60 def SystemZInstrInfo : InstrInfo { let guessInstructionProperties = 0; }
  61
  62 //===----------------------------------------------------------------------===//
  63 // Assembly parser
  64 //===----------------------------------------------------------------------===//
  65
  66 def SystemZAsmParser : AsmParser {
  67   let ShouldEmitMatchRegisterName = 0;
  68 }
  69
  70 //===----------------------------------------------------------------------===//
  71 // Top-level target declaration
  72 //===----------------------------------------------------------------------===//
  73
  74 def SystemZ : Target {
  75   let InstructionSet = SystemZInstrInfo;
  76   let AssemblyParsers = [SystemZAsmParser];
  77   let AllowRegisterRenaming = 1;
  78 }