1 //===-- SystemZAsmPrinter.cpp - SystemZ LLVM assembly printer -------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Streams SystemZ assembly language and associated data, in the form of
10 // MCInsts and MCExprs respectively.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZAsmPrinter.h"
15 #include "MCTargetDesc/SystemZInstPrinter.h"
16 #include "SystemZConstantPoolValue.h"
17 #include "SystemZMCInstLower.h"
18 #include "TargetInfo/SystemZTargetInfo.h"
19 #include "llvm/BinaryFormat/ELF.h"
20 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
21 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
22 #include "llvm/IR/Mangler.h"
23 #include "llvm/MC/MCExpr.h"
24 #include "llvm/MC/MCInstBuilder.h"
25 #include "llvm/MC/MCSectionELF.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/Support/TargetRegistry.h"
31 // Return an RI instruction like MI with opcode Opcode, but with the
32 // GR64 register operands turned into GR32s.
33 static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) {
35 return MCInstBuilder(Opcode)
36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
37 .addImm(MI->getOperand(1).getImm());
39 return MCInstBuilder(Opcode)
40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))
42 .addImm(MI->getOperand(2).getImm());
45 // Return an RI instruction like MI with opcode Opcode, but with the
46 // GR64 register operands turned into GRH32s.
47 static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) {
49 return MCInstBuilder(Opcode)
50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
51 .addImm(MI->getOperand(1).getImm());
53 return MCInstBuilder(Opcode)
54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))
56 .addImm(MI->getOperand(2).getImm());
59 // Return an RI instruction like MI with opcode Opcode, but with the
60 // R2 register turned into a GR64.
61 static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode) {
62 return MCInstBuilder(Opcode)
63 .addReg(MI->getOperand(0).getReg())
64 .addReg(MI->getOperand(1).getReg())
65 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()))
66 .addImm(MI->getOperand(3).getImm())
67 .addImm(MI->getOperand(4).getImm())
68 .addImm(MI->getOperand(5).getImm());
71 static const MCSymbolRefExpr *getTLSGetOffset(MCContext &Context) {
72 StringRef Name = "__tls_get_offset";
73 return MCSymbolRefExpr::create(Context.getOrCreateSymbol(Name),
74 MCSymbolRefExpr::VK_PLT,
78 static const MCSymbolRefExpr *getGlobalOffsetTable(MCContext &Context) {
79 StringRef Name = "_GLOBAL_OFFSET_TABLE_";
80 return MCSymbolRefExpr::create(Context.getOrCreateSymbol(Name),
81 MCSymbolRefExpr::VK_None,
85 // MI is an instruction that accepts an optional alignment hint,
86 // and which was already lowered to LoweredMI. If the alignment
87 // of the original memory operand is known, update LoweredMI to
88 // an instruction with the corresponding hint set.
89 static void lowerAlignmentHint(const MachineInstr *MI, MCInst &LoweredMI,
91 if (!MI->hasOneMemOperand())
93 const MachineMemOperand *MMO = *MI->memoperands_begin();
94 unsigned AlignmentHint = 0;
95 if (MMO->getAlign() >= Align(16))
97 else if (MMO->getAlign() >= Align(8))
99 if (AlignmentHint == 0)
102 LoweredMI.setOpcode(Opcode);
103 LoweredMI.addOperand(MCOperand::createImm(AlignmentHint));
106 // MI loads the high part of a vector from memory. Return an instruction
107 // that uses replicating vector load Opcode to do the same thing.
108 static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode) {
109 return MCInstBuilder(Opcode)
110 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
111 .addReg(MI->getOperand(1).getReg())
112 .addImm(MI->getOperand(2).getImm())
113 .addReg(MI->getOperand(3).getReg());
116 // MI stores the high part of a vector to memory. Return an instruction
117 // that uses elemental vector store Opcode to do the same thing.
118 static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) {
119 return MCInstBuilder(Opcode)
120 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
121 .addReg(MI->getOperand(1).getReg())
122 .addImm(MI->getOperand(2).getImm())
123 .addReg(MI->getOperand(3).getReg())
127 void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
128 SystemZMCInstLower Lower(MF->getContext(), *this);
130 switch (MI->getOpcode()) {
131 case SystemZ::Return:
132 LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D);
135 case SystemZ::CondReturn:
136 LoweredMI = MCInstBuilder(SystemZ::BCR)
137 .addImm(MI->getOperand(0).getImm())
138 .addImm(MI->getOperand(1).getImm())
139 .addReg(SystemZ::R14D);
142 case SystemZ::CRBReturn:
143 LoweredMI = MCInstBuilder(SystemZ::CRB)
144 .addReg(MI->getOperand(0).getReg())
145 .addReg(MI->getOperand(1).getReg())
146 .addImm(MI->getOperand(2).getImm())
147 .addReg(SystemZ::R14D)
151 case SystemZ::CGRBReturn:
152 LoweredMI = MCInstBuilder(SystemZ::CGRB)
153 .addReg(MI->getOperand(0).getReg())
154 .addReg(MI->getOperand(1).getReg())
155 .addImm(MI->getOperand(2).getImm())
156 .addReg(SystemZ::R14D)
160 case SystemZ::CIBReturn:
161 LoweredMI = MCInstBuilder(SystemZ::CIB)
162 .addReg(MI->getOperand(0).getReg())
163 .addImm(MI->getOperand(1).getImm())
164 .addImm(MI->getOperand(2).getImm())
165 .addReg(SystemZ::R14D)
169 case SystemZ::CGIBReturn:
170 LoweredMI = MCInstBuilder(SystemZ::CGIB)
171 .addReg(MI->getOperand(0).getReg())
172 .addImm(MI->getOperand(1).getImm())
173 .addImm(MI->getOperand(2).getImm())
174 .addReg(SystemZ::R14D)
178 case SystemZ::CLRBReturn:
179 LoweredMI = MCInstBuilder(SystemZ::CLRB)
180 .addReg(MI->getOperand(0).getReg())
181 .addReg(MI->getOperand(1).getReg())
182 .addImm(MI->getOperand(2).getImm())
183 .addReg(SystemZ::R14D)
187 case SystemZ::CLGRBReturn:
188 LoweredMI = MCInstBuilder(SystemZ::CLGRB)
189 .addReg(MI->getOperand(0).getReg())
190 .addReg(MI->getOperand(1).getReg())
191 .addImm(MI->getOperand(2).getImm())
192 .addReg(SystemZ::R14D)
196 case SystemZ::CLIBReturn:
197 LoweredMI = MCInstBuilder(SystemZ::CLIB)
198 .addReg(MI->getOperand(0).getReg())
199 .addImm(MI->getOperand(1).getImm())
200 .addImm(MI->getOperand(2).getImm())
201 .addReg(SystemZ::R14D)
205 case SystemZ::CLGIBReturn:
206 LoweredMI = MCInstBuilder(SystemZ::CLGIB)
207 .addReg(MI->getOperand(0).getReg())
208 .addImm(MI->getOperand(1).getImm())
209 .addImm(MI->getOperand(2).getImm())
210 .addReg(SystemZ::R14D)
214 case SystemZ::CallBRASL:
215 LoweredMI = MCInstBuilder(SystemZ::BRASL)
216 .addReg(SystemZ::R14D)
217 .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));
220 case SystemZ::CallBASR:
221 LoweredMI = MCInstBuilder(SystemZ::BASR)
222 .addReg(SystemZ::R14D)
223 .addReg(MI->getOperand(0).getReg());
226 case SystemZ::CallJG:
227 LoweredMI = MCInstBuilder(SystemZ::JG)
228 .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));
231 case SystemZ::CallBRCL:
232 LoweredMI = MCInstBuilder(SystemZ::BRCL)
233 .addImm(MI->getOperand(0).getImm())
234 .addImm(MI->getOperand(1).getImm())
235 .addExpr(Lower.getExpr(MI->getOperand(2), MCSymbolRefExpr::VK_PLT));
238 case SystemZ::CallBR:
239 LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R1D);
242 case SystemZ::CallBCR:
243 LoweredMI = MCInstBuilder(SystemZ::BCR)
244 .addImm(MI->getOperand(0).getImm())
245 .addImm(MI->getOperand(1).getImm())
246 .addReg(SystemZ::R1D);
249 case SystemZ::CRBCall:
250 LoweredMI = MCInstBuilder(SystemZ::CRB)
251 .addReg(MI->getOperand(0).getReg())
252 .addReg(MI->getOperand(1).getReg())
253 .addImm(MI->getOperand(2).getImm())
254 .addReg(SystemZ::R1D)
258 case SystemZ::CGRBCall:
259 LoweredMI = MCInstBuilder(SystemZ::CGRB)
260 .addReg(MI->getOperand(0).getReg())
261 .addReg(MI->getOperand(1).getReg())
262 .addImm(MI->getOperand(2).getImm())
263 .addReg(SystemZ::R1D)
267 case SystemZ::CIBCall:
268 LoweredMI = MCInstBuilder(SystemZ::CIB)
269 .addReg(MI->getOperand(0).getReg())
270 .addImm(MI->getOperand(1).getImm())
271 .addImm(MI->getOperand(2).getImm())
272 .addReg(SystemZ::R1D)
276 case SystemZ::CGIBCall:
277 LoweredMI = MCInstBuilder(SystemZ::CGIB)
278 .addReg(MI->getOperand(0).getReg())
279 .addImm(MI->getOperand(1).getImm())
280 .addImm(MI->getOperand(2).getImm())
281 .addReg(SystemZ::R1D)
285 case SystemZ::CLRBCall:
286 LoweredMI = MCInstBuilder(SystemZ::CLRB)
287 .addReg(MI->getOperand(0).getReg())
288 .addReg(MI->getOperand(1).getReg())
289 .addImm(MI->getOperand(2).getImm())
290 .addReg(SystemZ::R1D)
294 case SystemZ::CLGRBCall:
295 LoweredMI = MCInstBuilder(SystemZ::CLGRB)
296 .addReg(MI->getOperand(0).getReg())
297 .addReg(MI->getOperand(1).getReg())
298 .addImm(MI->getOperand(2).getImm())
299 .addReg(SystemZ::R1D)
303 case SystemZ::CLIBCall:
304 LoweredMI = MCInstBuilder(SystemZ::CLIB)
305 .addReg(MI->getOperand(0).getReg())
306 .addImm(MI->getOperand(1).getImm())
307 .addImm(MI->getOperand(2).getImm())
308 .addReg(SystemZ::R1D)
312 case SystemZ::CLGIBCall:
313 LoweredMI = MCInstBuilder(SystemZ::CLGIB)
314 .addReg(MI->getOperand(0).getReg())
315 .addImm(MI->getOperand(1).getImm())
316 .addImm(MI->getOperand(2).getImm())
317 .addReg(SystemZ::R1D)
321 case SystemZ::TLS_GDCALL:
322 LoweredMI = MCInstBuilder(SystemZ::BRASL)
323 .addReg(SystemZ::R14D)
324 .addExpr(getTLSGetOffset(MF->getContext()))
325 .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_TLSGD));
328 case SystemZ::TLS_LDCALL:
329 LoweredMI = MCInstBuilder(SystemZ::BRASL)
330 .addReg(SystemZ::R14D)
331 .addExpr(getTLSGetOffset(MF->getContext()))
332 .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_TLSLDM));
336 LoweredMI = MCInstBuilder(SystemZ::LARL)
337 .addReg(MI->getOperand(0).getReg())
338 .addExpr(getGlobalOffsetTable(MF->getContext()));
341 case SystemZ::IILF64:
342 LoweredMI = MCInstBuilder(SystemZ::IILF)
343 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
344 .addImm(MI->getOperand(2).getImm());
347 case SystemZ::IIHF64:
348 LoweredMI = MCInstBuilder(SystemZ::IIHF)
349 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
350 .addImm(MI->getOperand(2).getImm());
353 case SystemZ::RISBHH:
354 case SystemZ::RISBHL:
355 LoweredMI = lowerRIEfLow(MI, SystemZ::RISBHG);
358 case SystemZ::RISBLH:
359 case SystemZ::RISBLL:
360 LoweredMI = lowerRIEfLow(MI, SystemZ::RISBLG);
363 case SystemZ::VLVGP32:
364 LoweredMI = MCInstBuilder(SystemZ::VLVGP)
365 .addReg(MI->getOperand(0).getReg())
366 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(1).getReg()))
367 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()));
372 LoweredMI = MCInstBuilder(SystemZ::VLR)
373 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
374 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()));
378 Lower.lower(MI, LoweredMI);
379 lowerAlignmentHint(MI, LoweredMI, SystemZ::VLAlign);
383 Lower.lower(MI, LoweredMI);
384 lowerAlignmentHint(MI, LoweredMI, SystemZ::VSTAlign);
388 Lower.lower(MI, LoweredMI);
389 lowerAlignmentHint(MI, LoweredMI, SystemZ::VLMAlign);
393 Lower.lower(MI, LoweredMI);
394 lowerAlignmentHint(MI, LoweredMI, SystemZ::VSTMAlign);
398 LoweredMI = lowerSubvectorLoad(MI, SystemZ::VLREPF);
402 LoweredMI = lowerSubvectorLoad(MI, SystemZ::VLREPG);
406 LoweredMI = lowerSubvectorStore(MI, SystemZ::VSTEF);
410 LoweredMI = lowerSubvectorStore(MI, SystemZ::VSTEG);
414 LoweredMI = MCInstBuilder(SystemZ::VLGVF)
415 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(0).getReg()))
416 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()))
417 .addReg(0).addImm(0);
421 LoweredMI = MCInstBuilder(SystemZ::VLVGF)
422 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
423 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
424 .addReg(MI->getOperand(1).getReg())
425 .addReg(0).addImm(0);
428 #define LOWER_LOW(NAME) \
429 case SystemZ::NAME##64: LoweredMI = lowerRILow(MI, SystemZ::NAME); break
445 #define LOWER_HIGH(NAME) \
446 case SystemZ::NAME##64: LoweredMI = lowerRIHigh(MI, SystemZ::NAME); break
462 case SystemZ::Serialize:
463 if (MF->getSubtarget<SystemZSubtarget>().hasFastSerialization())
464 LoweredMI = MCInstBuilder(SystemZ::BCRAsm)
465 .addImm(14).addReg(SystemZ::R0D);
467 LoweredMI = MCInstBuilder(SystemZ::BCRAsm)
468 .addImm(15).addReg(SystemZ::R0D);
471 // Emit nothing here but a comment if we can.
472 case SystemZ::MemBarrier:
473 OutStreamer->emitRawComment("MEMBARRIER");
476 // We want to emit "j .+2" for traps, jumping to the relative immediate field
477 // of the jump instruction, which is an illegal instruction. We cannot emit a
478 // "." symbol, so create and emit a temp label before the instruction and use
480 case SystemZ::Trap: {
481 MCSymbol *DotSym = OutContext.createTempSymbol();
482 OutStreamer->emitLabel(DotSym);
484 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(DotSym, OutContext);
485 const MCConstantExpr *ConstExpr = MCConstantExpr::create(2, OutContext);
486 LoweredMI = MCInstBuilder(SystemZ::J)
487 .addExpr(MCBinaryExpr::createAdd(Expr, ConstExpr, OutContext));
491 // Conditional traps will create a branch on condition instruction that jumps
492 // to the relative immediate field of the jump instruction. (eg. "jo .+2")
493 case SystemZ::CondTrap: {
494 MCSymbol *DotSym = OutContext.createTempSymbol();
495 OutStreamer->emitLabel(DotSym);
497 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(DotSym, OutContext);
498 const MCConstantExpr *ConstExpr = MCConstantExpr::create(2, OutContext);
499 LoweredMI = MCInstBuilder(SystemZ::BRC)
500 .addImm(MI->getOperand(0).getImm())
501 .addImm(MI->getOperand(1).getImm())
502 .addExpr(MCBinaryExpr::createAdd(Expr, ConstExpr, OutContext));
506 case TargetOpcode::FENTRY_CALL:
507 LowerFENTRY_CALL(*MI, Lower);
510 case TargetOpcode::STACKMAP:
514 case TargetOpcode::PATCHPOINT:
515 LowerPATCHPOINT(*MI, Lower);
519 Lower.lower(MI, LoweredMI);
522 EmitToStreamer(*OutStreamer, LoweredMI);
525 // Emit the largest nop instruction smaller than or equal to NumBytes
526 // bytes. Return the size of nop emitted.
527 static unsigned EmitNop(MCContext &OutContext, MCStreamer &OutStreamer,
528 unsigned NumBytes, const MCSubtargetInfo &STI) {
530 llvm_unreachable("Zero nops?");
533 else if (NumBytes < 4) {
534 OutStreamer.emitInstruction(
535 MCInstBuilder(SystemZ::BCRAsm).addImm(0).addReg(SystemZ::R0D), STI);
538 else if (NumBytes < 6) {
539 OutStreamer.emitInstruction(
540 MCInstBuilder(SystemZ::BCAsm).addImm(0).addReg(0).addImm(0).addReg(0),
545 MCSymbol *DotSym = OutContext.createTempSymbol();
546 const MCSymbolRefExpr *Dot = MCSymbolRefExpr::create(DotSym, OutContext);
547 OutStreamer.emitLabel(DotSym);
548 OutStreamer.emitInstruction(
549 MCInstBuilder(SystemZ::BRCLAsm).addImm(0).addExpr(Dot), STI);
554 void SystemZAsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,
555 SystemZMCInstLower &Lower) {
556 MCContext &Ctx = MF->getContext();
557 if (MF->getFunction().hasFnAttribute("mrecord-mcount")) {
558 MCSymbol *DotSym = OutContext.createTempSymbol();
559 OutStreamer->PushSection();
560 OutStreamer->SwitchSection(
561 Ctx.getELFSection("__mcount_loc", ELF::SHT_PROGBITS, ELF::SHF_ALLOC));
562 OutStreamer->emitSymbolValue(DotSym, 8);
563 OutStreamer->PopSection();
564 OutStreamer->emitLabel(DotSym);
567 if (MF->getFunction().hasFnAttribute("mnop-mcount")) {
568 EmitNop(Ctx, *OutStreamer, 6, getSubtargetInfo());
572 MCSymbol *fentry = Ctx.getOrCreateSymbol("__fentry__");
573 const MCSymbolRefExpr *Op =
574 MCSymbolRefExpr::create(fentry, MCSymbolRefExpr::VK_PLT, Ctx);
575 OutStreamer->emitInstruction(
576 MCInstBuilder(SystemZ::BRASL).addReg(SystemZ::R0D).addExpr(Op),
580 void SystemZAsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
581 const SystemZInstrInfo *TII =
582 static_cast<const SystemZInstrInfo *>(MF->getSubtarget().getInstrInfo());
584 unsigned NumNOPBytes = MI.getOperand(1).getImm();
586 auto &Ctx = OutStreamer->getContext();
587 MCSymbol *MILabel = Ctx.createTempSymbol();
588 OutStreamer->emitLabel(MILabel);
590 SM.recordStackMap(*MILabel, MI);
591 assert(NumNOPBytes % 2 == 0 && "Invalid number of NOP bytes requested!");
593 // Scan ahead to trim the shadow.
594 unsigned ShadowBytes = 0;
595 const MachineBasicBlock &MBB = *MI.getParent();
596 MachineBasicBlock::const_iterator MII(MI);
598 while (ShadowBytes < NumNOPBytes) {
599 if (MII == MBB.end() ||
600 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
601 MII->getOpcode() == TargetOpcode::STACKMAP)
603 ShadowBytes += TII->getInstSizeInBytes(*MII);
610 while (ShadowBytes < NumNOPBytes)
611 ShadowBytes += EmitNop(OutContext, *OutStreamer, NumNOPBytes - ShadowBytes,
615 // Lower a patchpoint of the form:
616 // [<def>], <id>, <numBytes>, <target>, <numArgs>
617 void SystemZAsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
618 SystemZMCInstLower &Lower) {
619 auto &Ctx = OutStreamer->getContext();
620 MCSymbol *MILabel = Ctx.createTempSymbol();
621 OutStreamer->emitLabel(MILabel);
623 SM.recordPatchPoint(*MILabel, MI);
624 PatchPointOpers Opers(&MI);
626 unsigned EncodedBytes = 0;
627 const MachineOperand &CalleeMO = Opers.getCallTarget();
629 if (CalleeMO.isImm()) {
630 uint64_t CallTarget = CalleeMO.getImm();
632 unsigned ScratchIdx = -1;
633 unsigned ScratchReg = 0;
635 ScratchIdx = Opers.getNextScratchIdx(ScratchIdx + 1);
636 ScratchReg = MI.getOperand(ScratchIdx).getReg();
637 } while (ScratchReg == SystemZ::R0D);
639 // Materialize the call target address
640 EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::LLILF)
642 .addImm(CallTarget & 0xFFFFFFFF));
644 if (CallTarget >> 32) {
645 EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::IIHF)
647 .addImm(CallTarget >> 32));
651 EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::BASR)
652 .addReg(SystemZ::R14D)
653 .addReg(ScratchReg));
656 } else if (CalleeMO.isGlobal()) {
657 const MCExpr *Expr = Lower.getExpr(CalleeMO, MCSymbolRefExpr::VK_PLT);
658 EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::BRASL)
659 .addReg(SystemZ::R14D)
665 unsigned NumBytes = Opers.getNumPatchBytes();
666 assert(NumBytes >= EncodedBytes &&
667 "Patchpoint can't request size less than the length of a call.");
668 assert((NumBytes - EncodedBytes) % 2 == 0 &&
669 "Invalid number of NOP bytes requested!");
670 while (EncodedBytes < NumBytes)
671 EncodedBytes += EmitNop(OutContext, *OutStreamer, NumBytes - EncodedBytes,
675 // Convert a SystemZ-specific constant pool modifier into the associated
676 // MCSymbolRefExpr variant kind.
677 static MCSymbolRefExpr::VariantKind
678 getModifierVariantKind(SystemZCP::SystemZCPModifier Modifier) {
680 case SystemZCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
681 case SystemZCP::TLSLDM: return MCSymbolRefExpr::VK_TLSLDM;
682 case SystemZCP::DTPOFF: return MCSymbolRefExpr::VK_DTPOFF;
683 case SystemZCP::NTPOFF: return MCSymbolRefExpr::VK_NTPOFF;
685 llvm_unreachable("Invalid SystemCPModifier!");
688 void SystemZAsmPrinter::emitMachineConstantPoolValue(
689 MachineConstantPoolValue *MCPV) {
690 auto *ZCPV = static_cast<SystemZConstantPoolValue*>(MCPV);
693 MCSymbolRefExpr::create(getSymbol(ZCPV->getGlobalValue()),
694 getModifierVariantKind(ZCPV->getModifier()),
696 uint64_t Size = getDataLayout().getTypeAllocSize(ZCPV->getType());
698 OutStreamer->emitValue(Expr, Size);
701 bool SystemZAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
702 const char *ExtraCode,
705 return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
706 SystemZMCInstLower Lower(MF->getContext(), *this);
707 MCOperand MO(Lower.lowerOperand(MI->getOperand(OpNo)));
708 SystemZInstPrinter::printOperand(MO, MAI, OS);
712 bool SystemZAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
714 const char *ExtraCode,
716 SystemZInstPrinter::printAddress(MI->getOperand(OpNo).getReg(),
717 MI->getOperand(OpNo + 1).getImm(),
718 MI->getOperand(OpNo + 2).getReg(), OS);
722 void SystemZAsmPrinter::emitEndOfAsmFile(Module &M) {
726 // Force static initialization.
727 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmPrinter() {
728 RegisterAsmPrinter<SystemZAsmPrinter> X(getTheSystemZTarget());