1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the SystemZ implementation of the TargetInstrInfo class.
11 //===----------------------------------------------------------------------===//
13 #include "SystemZInstrInfo.h"
14 #include "MCTargetDesc/SystemZMCTargetDesc.h"
16 #include "SystemZInstrBuilder.h"
17 #include "SystemZSubtarget.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/CodeGen/LiveInterval.h"
20 #include "llvm/CodeGen/LiveIntervals.h"
21 #include "llvm/CodeGen/LivePhysRegs.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineMemOperand.h"
28 #include "llvm/CodeGen/MachineOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SlotIndexes.h"
31 #include "llvm/CodeGen/StackMaps.h"
32 #include "llvm/CodeGen/TargetInstrInfo.h"
33 #include "llvm/CodeGen/TargetSubtargetInfo.h"
34 #include "llvm/CodeGen/VirtRegMap.h"
35 #include "llvm/MC/MCInstrDesc.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/Support/BranchProbability.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Target/TargetMachine.h"
47 #define GET_INSTRINFO_CTOR_DTOR
48 #define GET_INSTRMAP_INFO
49 #include "SystemZGenInstrInfo.inc"
51 #define DEBUG_TYPE "systemz-II"
53 // Return a mask with Count low bits set.
54 static uint64_t allOnes(unsigned int Count) {
55 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
58 // Pin the vtable to this file.
59 void SystemZInstrInfo::anchor() {}
61 SystemZInstrInfo::SystemZInstrInfo(SystemZSubtarget &sti)
62 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
63 RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister()),
66 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
67 // each having the opcode given by NewOpcode.
68 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
69 unsigned NewOpcode) const {
70 MachineBasicBlock *MBB = MI->getParent();
71 MachineFunction &MF = *MBB->getParent();
73 // Get two load or store instructions. Use the original instruction for one
74 // of them (arbitrarily the second here) and create a clone for the other.
75 MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
76 MBB->insert(MI, EarlierMI);
78 // Set up the two 64-bit registers and remember super reg and its flags.
79 MachineOperand &HighRegOp = EarlierMI->getOperand(0);
80 MachineOperand &LowRegOp = MI->getOperand(0);
81 Register Reg128 = LowRegOp.getReg();
82 unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
83 unsigned Reg128Undef = getUndefRegState(LowRegOp.isUndef());
84 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
85 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
88 // Add implicit uses of the super register in case one of the subregs is
89 // undefined. We could track liveness and skip storing an undefined
90 // subreg, but this is hopefully rare (discovered with llvm-stress).
91 // If Reg128 was killed, set kill flag on MI.
92 unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
93 MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl);
94 MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl | Reg128Killed));
97 // The address in the first (high) instruction is already correct.
98 // Adjust the offset in the second (low) instruction.
99 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
100 MachineOperand &LowOffsetOp = MI->getOperand(2);
101 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
103 // Clear the kill flags on the registers in the first instruction.
104 if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
105 EarlierMI->getOperand(0).setIsKill(false);
106 EarlierMI->getOperand(1).setIsKill(false);
107 EarlierMI->getOperand(3).setIsKill(false);
110 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
111 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
112 assert(HighOpcode && LowOpcode && "Both offsets should be in range");
114 EarlierMI->setDesc(get(HighOpcode));
115 MI->setDesc(get(LowOpcode));
118 // Split ADJDYNALLOC instruction MI.
119 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
120 MachineBasicBlock *MBB = MI->getParent();
121 MachineFunction &MF = *MBB->getParent();
122 MachineFrameInfo &MFFrame = MF.getFrameInfo();
123 MachineOperand &OffsetMO = MI->getOperand(2);
124 SystemZCallingConventionRegisters *Regs = STI.getSpecialRegisters();
126 uint64_t Offset = (MFFrame.getMaxCallFrameSize() +
127 Regs->getCallFrameSize() +
128 Regs->getStackPointerBias() +
130 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
131 assert(NewOpcode && "No support for huge argument lists yet");
132 MI->setDesc(get(NewOpcode));
133 OffsetMO.setImm(Offset);
136 // MI is an RI-style pseudo instruction. Replace it with LowOpcode
137 // if the first operand is a low GR32 and HighOpcode if the first operand
138 // is a high GR32. ConvertHigh is true if LowOpcode takes a signed operand
139 // and HighOpcode takes an unsigned 32-bit operand. In those cases,
140 // MI has the same kind of operand as LowOpcode, so needs to be converted
141 // if HighOpcode is used.
142 void SystemZInstrInfo::expandRIPseudo(MachineInstr &MI, unsigned LowOpcode,
144 bool ConvertHigh) const {
145 Register Reg = MI.getOperand(0).getReg();
146 bool IsHigh = SystemZ::isHighReg(Reg);
147 MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));
148 if (IsHigh && ConvertHigh)
149 MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
152 // MI is a three-operand RIE-style pseudo instruction. Replace it with
153 // LowOpcodeK if the registers are both low GR32s, otherwise use a move
154 // followed by HighOpcode or LowOpcode, depending on whether the target
155 // is a high or low GR32.
156 void SystemZInstrInfo::expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
158 unsigned HighOpcode) const {
159 Register DestReg = MI.getOperand(0).getReg();
160 Register SrcReg = MI.getOperand(1).getReg();
161 bool DestIsHigh = SystemZ::isHighReg(DestReg);
162 bool SrcIsHigh = SystemZ::isHighReg(SrcReg);
163 if (!DestIsHigh && !SrcIsHigh)
164 MI.setDesc(get(LowOpcodeK));
166 if (DestReg != SrcReg) {
167 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,
168 SystemZ::LR, 32, MI.getOperand(1).isKill(),
169 MI.getOperand(1).isUndef());
170 MI.getOperand(1).setReg(DestReg);
172 MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
173 MI.tieOperands(0, 1);
177 // MI is an RXY-style pseudo instruction. Replace it with LowOpcode
178 // if the first operand is a low GR32 and HighOpcode if the first operand
180 void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
181 unsigned HighOpcode) const {
182 Register Reg = MI.getOperand(0).getReg();
183 unsigned Opcode = getOpcodeForOffset(
184 SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode,
185 MI.getOperand(2).getImm());
186 MI.setDesc(get(Opcode));
189 // MI is a load-on-condition pseudo instruction with a single register
190 // (source or destination) operand. Replace it with LowOpcode if the
191 // register is a low GR32 and HighOpcode if the register is a high GR32.
192 void SystemZInstrInfo::expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
193 unsigned HighOpcode) const {
194 Register Reg = MI.getOperand(0).getReg();
195 unsigned Opcode = SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode;
196 MI.setDesc(get(Opcode));
199 // MI is an RR-style pseudo instruction that zero-extends the low Size bits
200 // of one GRX32 into another. Replace it with LowOpcode if both operands
201 // are low registers, otherwise use RISB[LH]G.
202 void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
203 unsigned Size) const {
204 MachineInstrBuilder MIB =
205 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
206 MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
207 Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
209 // Keep the remaining operands as-is.
210 for (const MachineOperand &MO : llvm::drop_begin(MI.operands(), 2))
213 MI.eraseFromParent();
216 void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {
217 MachineBasicBlock *MBB = MI->getParent();
218 MachineFunction &MF = *MBB->getParent();
219 const Register Reg64 = MI->getOperand(0).getReg();
220 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);
222 // EAR can only load the low subregister so us a shift for %a0 to produce
223 // the GR containing %a0 and %a1.
226 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
228 .addReg(Reg64, RegState::ImplicitDefine);
230 // sllg <reg>, <reg>, 32
231 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64)
237 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
238 .addReg(SystemZ::A1);
240 // lg <reg>, 40(<reg>)
241 MI->setDesc(get(SystemZ::LG));
242 MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0);
245 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
246 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
247 // are low registers, otherwise use RISB[LH]G. Size is the number of bits
248 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
249 // KillSrc is true if this move is the last use of SrcReg.
251 SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
252 MachineBasicBlock::iterator MBBI,
253 const DebugLoc &DL, unsigned DestReg,
254 unsigned SrcReg, unsigned LowLowOpcode,
255 unsigned Size, bool KillSrc,
256 bool UndefSrc) const {
258 bool DestIsHigh = SystemZ::isHighReg(DestReg);
259 bool SrcIsHigh = SystemZ::isHighReg(SrcReg);
260 if (DestIsHigh && SrcIsHigh)
261 Opcode = SystemZ::RISBHH;
262 else if (DestIsHigh && !SrcIsHigh)
263 Opcode = SystemZ::RISBHL;
264 else if (!DestIsHigh && SrcIsHigh)
265 Opcode = SystemZ::RISBLH;
267 return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
268 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
270 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
271 return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
272 .addReg(DestReg, RegState::Undef)
273 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
274 .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
277 MachineInstr *SystemZInstrInfo::commuteInstructionImpl(MachineInstr &MI,
280 unsigned OpIdx2) const {
281 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
283 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
287 switch (MI.getOpcode()) {
288 case SystemZ::SELRMux:
289 case SystemZ::SELFHR:
292 case SystemZ::LOCRMux:
293 case SystemZ::LOCFHR:
295 case SystemZ::LOCGR: {
296 auto &WorkingMI = cloneIfNew(MI);
298 unsigned CCValid = WorkingMI.getOperand(3).getImm();
299 unsigned CCMask = WorkingMI.getOperand(4).getImm();
300 WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
301 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
305 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
309 // If MI is a simple load or store for a frame object, return the register
310 // it loads or stores and set FrameIndex to the index of the frame object.
311 // Return 0 otherwise.
313 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
314 static int isSimpleMove(const MachineInstr &MI, int &FrameIndex,
316 const MCInstrDesc &MCID = MI.getDesc();
317 if ((MCID.TSFlags & Flag) && MI.getOperand(1).isFI() &&
318 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {
319 FrameIndex = MI.getOperand(1).getIndex();
320 return MI.getOperand(0).getReg();
325 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
326 int &FrameIndex) const {
327 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
330 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
331 int &FrameIndex) const {
332 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
335 bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr &MI,
337 int &SrcFrameIndex) const {
338 // Check for MVC 0(Length,FI1),0(FI2)
339 const MachineFrameInfo &MFI = MI.getParent()->getParent()->getFrameInfo();
340 if (MI.getOpcode() != SystemZ::MVC || !MI.getOperand(0).isFI() ||
341 MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() ||
342 MI.getOperand(4).getImm() != 0)
345 // Check that Length covers the full slots.
346 int64_t Length = MI.getOperand(2).getImm();
347 unsigned FI1 = MI.getOperand(0).getIndex();
348 unsigned FI2 = MI.getOperand(3).getIndex();
349 if (MFI.getObjectSize(FI1) != Length ||
350 MFI.getObjectSize(FI2) != Length)
353 DestFrameIndex = FI1;
358 bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
359 MachineBasicBlock *&TBB,
360 MachineBasicBlock *&FBB,
361 SmallVectorImpl<MachineOperand> &Cond,
362 bool AllowModify) const {
363 // Most of the code and comments here are boilerplate.
365 // Start from the bottom of the block and work up, examining the
366 // terminator instructions.
367 MachineBasicBlock::iterator I = MBB.end();
368 while (I != MBB.begin()) {
370 if (I->isDebugInstr())
373 // Working from the bottom, when we see a non-terminator instruction, we're
375 if (!isUnpredicatedTerminator(*I))
378 // A terminator that isn't a branch can't easily be handled by this
383 // Can't handle indirect branches.
384 SystemZII::Branch Branch(getBranchInfo(*I));
385 if (!Branch.hasMBBTarget())
388 // Punt on compound branches.
389 if (Branch.Type != SystemZII::BranchNormal)
392 if (Branch.CCMask == SystemZ::CCMASK_ANY) {
393 // Handle unconditional branches.
395 TBB = Branch.getMBBTarget();
399 // If the block has any instructions after a JMP, delete them.
400 MBB.erase(std::next(I), MBB.end());
405 // Delete the JMP if it's equivalent to a fall-through.
406 if (MBB.isLayoutSuccessor(Branch.getMBBTarget())) {
408 I->eraseFromParent();
413 // TBB is used to indicate the unconditinal destination.
414 TBB = Branch.getMBBTarget();
418 // Working from the bottom, handle the first conditional branch.
420 // FIXME: add X86-style branch swap
422 TBB = Branch.getMBBTarget();
423 Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
424 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
428 // Handle subsequent conditional branches.
429 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
431 // Only handle the case where all conditional branches branch to the same
433 if (TBB != Branch.getMBBTarget())
436 // If the conditions are the same, we can leave them alone.
437 unsigned OldCCValid = Cond[0].getImm();
438 unsigned OldCCMask = Cond[1].getImm();
439 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
442 // FIXME: Try combining conditions like X86 does. Should be easy on Z!
449 unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB,
450 int *BytesRemoved) const {
451 assert(!BytesRemoved && "code size not handled");
453 // Most of the code and comments here are boilerplate.
454 MachineBasicBlock::iterator I = MBB.end();
457 while (I != MBB.begin()) {
459 if (I->isDebugInstr())
463 if (!getBranchInfo(*I).hasMBBTarget())
465 // Remove the branch.
466 I->eraseFromParent();
474 bool SystemZInstrInfo::
475 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
476 assert(Cond.size() == 2 && "Invalid condition");
477 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
481 unsigned SystemZInstrInfo::insertBranch(MachineBasicBlock &MBB,
482 MachineBasicBlock *TBB,
483 MachineBasicBlock *FBB,
484 ArrayRef<MachineOperand> Cond,
486 int *BytesAdded) const {
487 // In this function we output 32-bit branches, which should always
488 // have enough range. They can be shortened and relaxed by later code
489 // in the pipeline, if desired.
491 // Shouldn't be a fall through.
492 assert(TBB && "insertBranch must not be told to insert a fallthrough");
493 assert((Cond.size() == 2 || Cond.size() == 0) &&
494 "SystemZ branch conditions have one component!");
495 assert(!BytesAdded && "code size not handled");
498 // Unconditional branch?
499 assert(!FBB && "Unconditional branch with multiple successors!");
500 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
504 // Conditional branch.
506 unsigned CCValid = Cond[0].getImm();
507 unsigned CCMask = Cond[1].getImm();
508 BuildMI(&MBB, DL, get(SystemZ::BRC))
509 .addImm(CCValid).addImm(CCMask).addMBB(TBB);
513 // Two-way Conditional branch. Insert the second branch.
514 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
520 bool SystemZInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
521 Register &SrcReg2, int64_t &Mask,
522 int64_t &Value) const {
523 assert(MI.isCompare() && "Caller should have checked for a comparison");
525 if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&
526 MI.getOperand(1).isImm()) {
527 SrcReg = MI.getOperand(0).getReg();
529 Value = MI.getOperand(1).getImm();
537 bool SystemZInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
538 ArrayRef<MachineOperand> Pred,
539 Register DstReg, Register TrueReg,
540 Register FalseReg, int &CondCycles,
542 int &FalseCycles) const {
543 // Not all subtargets have LOCR instructions.
544 if (!STI.hasLoadStoreOnCond())
546 if (Pred.size() != 2)
549 // Check register classes.
550 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
551 const TargetRegisterClass *RC =
552 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
556 // We have LOCR instructions for 32 and 64 bit general purpose registers.
557 if ((STI.hasLoadStoreOnCond2() &&
558 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
559 SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
560 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
567 // Can't do anything else.
571 void SystemZInstrInfo::insertSelect(MachineBasicBlock &MBB,
572 MachineBasicBlock::iterator I,
573 const DebugLoc &DL, Register DstReg,
574 ArrayRef<MachineOperand> Pred,
576 Register FalseReg) const {
577 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
578 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
580 assert(Pred.size() == 2 && "Invalid condition");
581 unsigned CCValid = Pred[0].getImm();
582 unsigned CCMask = Pred[1].getImm();
585 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
586 if (STI.hasMiscellaneousExtensions3())
587 Opc = SystemZ::SELRMux;
588 else if (STI.hasLoadStoreOnCond2())
589 Opc = SystemZ::LOCRMux;
592 MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);
593 Register TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
594 Register FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
595 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
596 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
600 } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
601 if (STI.hasMiscellaneousExtensions3())
602 Opc = SystemZ::SELGR;
604 Opc = SystemZ::LOCGR;
606 llvm_unreachable("Invalid register class");
608 BuildMI(MBB, I, DL, get(Opc), DstReg)
609 .addReg(FalseReg).addReg(TrueReg)
610 .addImm(CCValid).addImm(CCMask);
613 bool SystemZInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
615 MachineRegisterInfo *MRI) const {
616 unsigned DefOpc = DefMI.getOpcode();
617 if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
618 DefOpc != SystemZ::LGHI)
620 if (DefMI.getOperand(0).getReg() != Reg)
622 int32_t ImmVal = (int32_t)DefMI.getOperand(1).getImm();
624 unsigned UseOpc = UseMI.getOpcode();
630 case SystemZ::SELRMux:
633 case SystemZ::LOCRMux:
634 if (!STI.hasLoadStoreOnCond2())
636 NewUseOpc = SystemZ::LOCHIMux;
637 if (UseMI.getOperand(2).getReg() == Reg)
639 else if (UseMI.getOperand(1).getReg() == Reg)
640 UseIdx = 2, CommuteIdx = 1;
648 if (!STI.hasLoadStoreOnCond2())
650 NewUseOpc = SystemZ::LOCGHI;
651 if (UseMI.getOperand(2).getReg() == Reg)
653 else if (UseMI.getOperand(1).getReg() == Reg)
654 UseIdx = 2, CommuteIdx = 1;
662 if (CommuteIdx != -1)
663 if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx))
666 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
667 UseMI.setDesc(get(NewUseOpc));
669 UseMI.tieOperands(0, 1);
670 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
672 DefMI.eraseFromParent();
677 bool SystemZInstrInfo::isPredicable(const MachineInstr &MI) const {
678 unsigned Opcode = MI.getOpcode();
679 if (Opcode == SystemZ::Return ||
680 Opcode == SystemZ::Return_XPLINK ||
681 Opcode == SystemZ::Trap ||
682 Opcode == SystemZ::CallJG ||
683 Opcode == SystemZ::CallBR)
688 bool SystemZInstrInfo::
689 isProfitableToIfCvt(MachineBasicBlock &MBB,
690 unsigned NumCycles, unsigned ExtraPredCycles,
691 BranchProbability Probability) const {
692 // Avoid using conditional returns at the end of a loop (since then
693 // we'd need to emit an unconditional branch to the beginning anyway,
694 // making the loop body longer). This doesn't apply for low-probability
695 // loops (eg. compare-and-swap retry), so just decide based on branch
696 // probability instead of looping structure.
697 // However, since Compare and Trap instructions cost the same as a regular
698 // Compare instruction, we should allow the if conversion to convert this
699 // into a Conditional Compare regardless of the branch probability.
700 if (MBB.getLastNonDebugInstr()->getOpcode() != SystemZ::Trap &&
701 MBB.succ_empty() && Probability < BranchProbability(1, 8))
703 // For now only convert single instructions.
704 return NumCycles == 1;
707 bool SystemZInstrInfo::
708 isProfitableToIfCvt(MachineBasicBlock &TMBB,
709 unsigned NumCyclesT, unsigned ExtraPredCyclesT,
710 MachineBasicBlock &FMBB,
711 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
712 BranchProbability Probability) const {
713 // For now avoid converting mutually-exclusive cases.
717 bool SystemZInstrInfo::
718 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
719 BranchProbability Probability) const {
720 // For now only duplicate single instructions.
721 return NumCycles == 1;
724 bool SystemZInstrInfo::PredicateInstruction(
725 MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
726 assert(Pred.size() == 2 && "Invalid condition");
727 unsigned CCValid = Pred[0].getImm();
728 unsigned CCMask = Pred[1].getImm();
729 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
730 unsigned Opcode = MI.getOpcode();
731 if (Opcode == SystemZ::Trap) {
732 MI.setDesc(get(SystemZ::CondTrap));
733 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
734 .addImm(CCValid).addImm(CCMask)
735 .addReg(SystemZ::CC, RegState::Implicit);
738 if (Opcode == SystemZ::Return || Opcode == SystemZ::Return_XPLINK) {
739 MI.setDesc(get(Opcode == SystemZ::Return ? SystemZ::CondReturn
740 : SystemZ::CondReturn_XPLINK));
741 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
744 .addReg(SystemZ::CC, RegState::Implicit);
747 if (Opcode == SystemZ::CallJG) {
748 MachineOperand FirstOp = MI.getOperand(0);
749 const uint32_t *RegMask = MI.getOperand(1).getRegMask();
752 MI.setDesc(get(SystemZ::CallBRCL));
753 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
758 .addReg(SystemZ::CC, RegState::Implicit);
761 if (Opcode == SystemZ::CallBR) {
762 MachineOperand Target = MI.getOperand(0);
763 const uint32_t *RegMask = MI.getOperand(1).getRegMask();
766 MI.setDesc(get(SystemZ::CallBCR));
767 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
768 .addImm(CCValid).addImm(CCMask)
771 .addReg(SystemZ::CC, RegState::Implicit);
777 void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
778 MachineBasicBlock::iterator MBBI,
779 const DebugLoc &DL, MCRegister DestReg,
780 MCRegister SrcReg, bool KillSrc) const {
781 // Split 128-bit GPR moves into two 64-bit moves. Add implicit uses of the
782 // super register in case one of the subregs is undefined.
783 // This handles ADDR128 too.
784 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
785 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
786 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
787 MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
788 .addReg(SrcReg, RegState::Implicit);
789 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
790 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
791 MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
792 .addReg(SrcReg, (getKillRegState(KillSrc) | RegState::Implicit));
796 if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
797 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,
802 // Move 128-bit floating-point values between VR128 and FP128.
803 if (SystemZ::VR128BitRegClass.contains(DestReg) &&
804 SystemZ::FP128BitRegClass.contains(SrcReg)) {
805 MCRegister SrcRegHi =
806 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),
807 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
808 MCRegister SrcRegLo =
809 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),
810 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
812 BuildMI(MBB, MBBI, DL, get(SystemZ::VMRHG), DestReg)
813 .addReg(SrcRegHi, getKillRegState(KillSrc))
814 .addReg(SrcRegLo, getKillRegState(KillSrc));
817 if (SystemZ::FP128BitRegClass.contains(DestReg) &&
818 SystemZ::VR128BitRegClass.contains(SrcReg)) {
819 MCRegister DestRegHi =
820 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),
821 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
822 MCRegister DestRegLo =
823 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),
824 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
826 if (DestRegHi != SrcReg)
827 copyPhysReg(MBB, MBBI, DL, DestRegHi, SrcReg, false);
828 BuildMI(MBB, MBBI, DL, get(SystemZ::VREPG), DestRegLo)
829 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1);
833 // Move CC value from a GR32.
834 if (DestReg == SystemZ::CC) {
836 SystemZ::GR32BitRegClass.contains(SrcReg) ? SystemZ::TMLH : SystemZ::TMHH;
837 BuildMI(MBB, MBBI, DL, get(Opcode))
838 .addReg(SrcReg, getKillRegState(KillSrc))
839 .addImm(3 << (SystemZ::IPM_CC - 16));
843 // Everything else needs only one instruction.
845 if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
846 Opcode = SystemZ::LGR;
847 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
848 // For z13 we prefer LDR over LER to avoid partial register dependencies.
849 Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
850 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
851 Opcode = SystemZ::LDR;
852 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
853 Opcode = SystemZ::LXR;
854 else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
855 Opcode = SystemZ::VLR32;
856 else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
857 Opcode = SystemZ::VLR64;
858 else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
859 Opcode = SystemZ::VLR;
860 else if (SystemZ::AR32BitRegClass.contains(DestReg, SrcReg))
861 Opcode = SystemZ::CPYA;
863 llvm_unreachable("Impossible reg-to-reg copy");
865 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
866 .addReg(SrcReg, getKillRegState(KillSrc));
869 void SystemZInstrInfo::storeRegToStackSlot(
870 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
871 bool isKill, int FrameIdx, const TargetRegisterClass *RC,
872 const TargetRegisterInfo *TRI) const {
873 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
875 // Callers may expect a single instruction, so keep 128-bit moves
876 // together for now and lower them after register allocation.
877 unsigned LoadOpcode, StoreOpcode;
878 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
879 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
880 .addReg(SrcReg, getKillRegState(isKill)),
884 void SystemZInstrInfo::loadRegFromStackSlot(
885 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg,
886 int FrameIdx, const TargetRegisterClass *RC,
887 const TargetRegisterInfo *TRI) const {
888 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
890 // Callers may expect a single instruction, so keep 128-bit moves
891 // together for now and lower them after register allocation.
892 unsigned LoadOpcode, StoreOpcode;
893 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
894 addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
898 // Return true if MI is a simple load or store with a 12-bit displacement
899 // and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
900 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
901 const MCInstrDesc &MCID = MI->getDesc();
902 return ((MCID.TSFlags & Flag) &&
903 isUInt<12>(MI->getOperand(2).getImm()) &&
904 MI->getOperand(3).getReg() == 0);
911 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
912 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
914 explicit operator bool() const { return RegSize; }
916 unsigned RegSize = 0;
918 unsigned ImmSize = 0;
921 } // end anonymous namespace
923 static LogicOp interpretAndImmediate(unsigned Opcode) {
925 case SystemZ::NILMux: return LogicOp(32, 0, 16);
926 case SystemZ::NIHMux: return LogicOp(32, 16, 16);
927 case SystemZ::NILL64: return LogicOp(64, 0, 16);
928 case SystemZ::NILH64: return LogicOp(64, 16, 16);
929 case SystemZ::NIHL64: return LogicOp(64, 32, 16);
930 case SystemZ::NIHH64: return LogicOp(64, 48, 16);
931 case SystemZ::NIFMux: return LogicOp(32, 0, 32);
932 case SystemZ::NILF64: return LogicOp(64, 0, 32);
933 case SystemZ::NIHF64: return LogicOp(64, 32, 32);
934 default: return LogicOp();
938 static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI) {
939 if (OldMI->registerDefIsDead(SystemZ::CC)) {
940 MachineOperand *CCDef = NewMI->findRegisterDefOperand(SystemZ::CC);
941 if (CCDef != nullptr)
942 CCDef->setIsDead(true);
946 static void transferMIFlag(MachineInstr *OldMI, MachineInstr *NewMI,
947 MachineInstr::MIFlag Flag) {
948 if (OldMI->getFlag(Flag))
949 NewMI->setFlag(Flag);
953 SystemZInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
954 LiveIntervals *LIS) const {
955 MachineBasicBlock *MBB = MI.getParent();
957 // Try to convert an AND into an RISBG-type instruction.
958 // TODO: It might be beneficial to select RISBG and shorten to AND instead.
959 if (LogicOp And = interpretAndImmediate(MI.getOpcode())) {
960 uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB;
961 // AND IMMEDIATE leaves the other bits of the register unchanged.
962 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
964 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
966 if (And.RegSize == 64) {
967 NewOpcode = SystemZ::RISBG;
968 // Prefer RISBGN if available, since it does not clobber CC.
969 if (STI.hasMiscellaneousExtensions())
970 NewOpcode = SystemZ::RISBGN;
972 NewOpcode = SystemZ::RISBMux;
976 MachineOperand &Dest = MI.getOperand(0);
977 MachineOperand &Src = MI.getOperand(1);
978 MachineInstrBuilder MIB =
979 BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpcode))
982 .addReg(Src.getReg(), getKillRegState(Src.isKill()),
988 unsigned NumOps = MI.getNumOperands();
989 for (unsigned I = 1; I < NumOps; ++I) {
990 MachineOperand &Op = MI.getOperand(I);
991 if (Op.isReg() && Op.isKill())
992 LV->replaceKillInstruction(Op.getReg(), MI, *MIB);
996 LIS->ReplaceMachineInstrInMaps(MI, *MIB);
997 transferDeadCC(&MI, MIB);
1004 MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
1005 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1006 MachineBasicBlock::iterator InsertPt, int FrameIndex,
1007 LiveIntervals *LIS, VirtRegMap *VRM) const {
1008 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1009 MachineRegisterInfo &MRI = MF.getRegInfo();
1010 const MachineFrameInfo &MFI = MF.getFrameInfo();
1011 unsigned Size = MFI.getObjectSize(FrameIndex);
1012 unsigned Opcode = MI.getOpcode();
1014 // Check CC liveness if new instruction introduces a dead def of CC.
1015 MCRegUnitIterator CCUnit(MCRegister::from(SystemZ::CC), TRI);
1016 SlotIndex MISlot = SlotIndex();
1017 LiveRange *CCLiveRange = nullptr;
1018 bool CCLiveAtMI = true;
1020 MISlot = LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
1021 CCLiveRange = &LIS->getRegUnit(*CCUnit);
1022 CCLiveAtMI = CCLiveRange->liveAt(MISlot);
1025 assert(!CCUnit.isValid() && "CC only has one reg unit.");
1027 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1028 if (!CCLiveAtMI && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1029 isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
1030 // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
1031 MachineInstr *BuiltMI = BuildMI(*InsertPt->getParent(), InsertPt,
1032 MI.getDebugLoc(), get(SystemZ::AGSI))
1033 .addFrameIndex(FrameIndex)
1035 .addImm(MI.getOperand(2).getImm());
1036 BuiltMI->findRegisterDefOperand(SystemZ::CC)->setIsDead(true);
1037 CCLiveRange->createDeadDef(MISlot, LIS->getVNInfoAllocator());
1043 // All other cases require a single operand.
1044 if (Ops.size() != 1)
1047 unsigned OpNum = Ops[0];
1049 TRI->getRegSizeInBits(*MF.getRegInfo()
1050 .getRegClass(MI.getOperand(OpNum).getReg())) &&
1051 "Invalid size combination");
1053 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1054 isInt<8>(MI.getOperand(2).getImm())) {
1055 // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
1056 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1057 MachineInstr *BuiltMI =
1058 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1059 .addFrameIndex(FrameIndex)
1061 .addImm(MI.getOperand(2).getImm());
1062 transferDeadCC(&MI, BuiltMI);
1063 transferMIFlag(&MI, BuiltMI, MachineInstr::NoSWrap);
1067 if ((Opcode == SystemZ::ALFI && OpNum == 0 &&
1068 isInt<8>((int32_t)MI.getOperand(2).getImm())) ||
1069 (Opcode == SystemZ::ALGFI && OpNum == 0 &&
1070 isInt<8>((int64_t)MI.getOperand(2).getImm()))) {
1071 // AL(G)FI %reg, CONST -> AL(G)SI %mem, CONST
1072 Opcode = (Opcode == SystemZ::ALFI ? SystemZ::ALSI : SystemZ::ALGSI);
1073 MachineInstr *BuiltMI =
1074 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1075 .addFrameIndex(FrameIndex)
1077 .addImm((int8_t)MI.getOperand(2).getImm());
1078 transferDeadCC(&MI, BuiltMI);
1082 if ((Opcode == SystemZ::SLFI && OpNum == 0 &&
1083 isInt<8>((int32_t)-MI.getOperand(2).getImm())) ||
1084 (Opcode == SystemZ::SLGFI && OpNum == 0 &&
1085 isInt<8>((int64_t)-MI.getOperand(2).getImm()))) {
1086 // SL(G)FI %reg, CONST -> AL(G)SI %mem, -CONST
1087 Opcode = (Opcode == SystemZ::SLFI ? SystemZ::ALSI : SystemZ::ALGSI);
1088 MachineInstr *BuiltMI =
1089 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1090 .addFrameIndex(FrameIndex)
1092 .addImm((int8_t)-MI.getOperand(2).getImm());
1093 transferDeadCC(&MI, BuiltMI);
1097 unsigned MemImmOpc = 0;
1099 case SystemZ::LHIMux:
1100 case SystemZ::LHI: MemImmOpc = SystemZ::MVHI; break;
1101 case SystemZ::LGHI: MemImmOpc = SystemZ::MVGHI; break;
1102 case SystemZ::CHIMux:
1103 case SystemZ::CHI: MemImmOpc = SystemZ::CHSI; break;
1104 case SystemZ::CGHI: MemImmOpc = SystemZ::CGHSI; break;
1105 case SystemZ::CLFIMux:
1107 if (isUInt<16>(MI.getOperand(1).getImm()))
1108 MemImmOpc = SystemZ::CLFHSI;
1110 case SystemZ::CLGFI:
1111 if (isUInt<16>(MI.getOperand(1).getImm()))
1112 MemImmOpc = SystemZ::CLGHSI;
1117 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1119 .addFrameIndex(FrameIndex)
1121 .addImm(MI.getOperand(1).getImm());
1123 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1124 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1125 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1126 // If we're spilling the destination of an LDGR or LGDR, store the
1127 // source register instead.
1129 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
1130 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1132 .add(MI.getOperand(1))
1133 .addFrameIndex(FrameIndex)
1137 // If we're spilling the source of an LDGR or LGDR, load the
1138 // destination register instead.
1140 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
1141 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1143 .add(MI.getOperand(0))
1144 .addFrameIndex(FrameIndex)
1150 // Look for cases where the source of a simple store or the destination
1151 // of a simple load is being spilled. Try to use MVC instead.
1153 // Although MVC is in practice a fast choice in these cases, it is still
1154 // logically a bytewise copy. This means that we cannot use it if the
1155 // load or store is volatile. We also wouldn't be able to use MVC if
1156 // the two memories partially overlap, but that case cannot occur here,
1157 // because we know that one of the memories is a full frame index.
1159 // For performance reasons, we also want to avoid using MVC if the addresses
1160 // might be equal. We don't worry about that case here, because spill slot
1161 // coloring happens later, and because we have special code to remove
1162 // MVCs that turn out to be redundant.
1163 if (OpNum == 0 && MI.hasOneMemOperand()) {
1164 MachineMemOperand *MMO = *MI.memoperands_begin();
1165 if (MMO->getSize() == Size && !MMO->isVolatile() && !MMO->isAtomic()) {
1166 // Handle conversion of loads.
1167 if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXLoad)) {
1168 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1170 .addFrameIndex(FrameIndex)
1173 .add(MI.getOperand(1))
1174 .addImm(MI.getOperand(2).getImm())
1175 .addMemOperand(MMO);
1177 // Handle conversion of stores.
1178 if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXStore)) {
1179 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1181 .add(MI.getOperand(1))
1182 .addImm(MI.getOperand(2).getImm())
1184 .addFrameIndex(FrameIndex)
1186 .addMemOperand(MMO);
1191 // If the spilled operand is the final one or the instruction is
1192 // commutable, try to change <INSN>R into <INSN>. Don't introduce a def of
1193 // CC if it is live and MI does not define it.
1194 unsigned NumOps = MI.getNumExplicitOperands();
1195 int MemOpcode = SystemZ::getMemOpcode(Opcode);
1196 if (MemOpcode == -1 ||
1197 (CCLiveAtMI && !MI.definesRegister(SystemZ::CC) &&
1198 get(MemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)))
1201 // Check if all other vregs have a usable allocation in the case of vector
1202 // to FP conversion.
1203 const MCInstrDesc &MCID = MI.getDesc();
1204 for (unsigned I = 0, E = MCID.getNumOperands(); I != E; ++I) {
1205 const MCOperandInfo &MCOI = MCID.OpInfo[I];
1206 if (MCOI.OperandType != MCOI::OPERAND_REGISTER || I == OpNum)
1208 const TargetRegisterClass *RC = TRI->getRegClass(MCOI.RegClass);
1209 if (RC == &SystemZ::VR32BitRegClass || RC == &SystemZ::VR64BitRegClass) {
1210 Register Reg = MI.getOperand(I).getReg();
1211 Register PhysReg = Register::isVirtualRegister(Reg)
1212 ? (VRM ? Register(VRM->getPhys(Reg)) : Register())
1215 !(SystemZ::FP32BitRegClass.contains(PhysReg) ||
1216 SystemZ::FP64BitRegClass.contains(PhysReg) ||
1217 SystemZ::VF128BitRegClass.contains(PhysReg)))
1221 // Fused multiply and add/sub need to have the same dst and accumulator reg.
1222 bool FusedFPOp = (Opcode == SystemZ::WFMADB || Opcode == SystemZ::WFMASB ||
1223 Opcode == SystemZ::WFMSDB || Opcode == SystemZ::WFMSSB);
1225 Register DstReg = VRM->getPhys(MI.getOperand(0).getReg());
1226 Register AccReg = VRM->getPhys(MI.getOperand(3).getReg());
1227 if (OpNum == 0 || OpNum == 3 || DstReg != AccReg)
1231 // Try to swap compare operands if possible.
1232 bool NeedsCommute = false;
1233 if ((MI.getOpcode() == SystemZ::CR || MI.getOpcode() == SystemZ::CGR ||
1234 MI.getOpcode() == SystemZ::CLR || MI.getOpcode() == SystemZ::CLGR ||
1235 MI.getOpcode() == SystemZ::WFCDB || MI.getOpcode() == SystemZ::WFCSB ||
1236 MI.getOpcode() == SystemZ::WFKDB || MI.getOpcode() == SystemZ::WFKSB) &&
1237 OpNum == 0 && prepareCompareSwapOperands(MI))
1238 NeedsCommute = true;
1240 bool CCOperands = false;
1241 if (MI.getOpcode() == SystemZ::LOCRMux || MI.getOpcode() == SystemZ::LOCGR ||
1242 MI.getOpcode() == SystemZ::SELRMux || MI.getOpcode() == SystemZ::SELGR) {
1243 assert(MI.getNumOperands() == 6 && NumOps == 5 &&
1244 "LOCR/SELR instruction operands corrupt?");
1249 // See if this is a 3-address instruction that is convertible to 2-address
1250 // and suitable for folding below. Only try this with virtual registers
1251 // and a provided VRM (during regalloc).
1252 if (NumOps == 3 && SystemZ::getTargetMemOpcode(MemOpcode) != -1) {
1256 Register DstReg = MI.getOperand(0).getReg();
1258 (Register::isVirtualRegister(DstReg) ? Register(VRM->getPhys(DstReg))
1260 Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg()
1261 : ((OpNum == 1 && MI.isCommutable())
1262 ? MI.getOperand(2).getReg()
1264 if (DstPhys && !SystemZ::GRH32BitRegClass.contains(DstPhys) && SrcReg &&
1265 Register::isVirtualRegister(SrcReg) &&
1266 DstPhys == VRM->getPhys(SrcReg))
1267 NeedsCommute = (OpNum == 1);
1273 if ((OpNum == NumOps - 1) || NeedsCommute || FusedFPOp) {
1274 const MCInstrDesc &MemDesc = get(MemOpcode);
1275 uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
1276 assert(AccessBytes != 0 && "Size of access should be known");
1277 assert(AccessBytes <= Size && "Access outside the frame index");
1278 uint64_t Offset = Size - AccessBytes;
1279 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
1280 MI.getDebugLoc(), get(MemOpcode));
1281 if (MI.isCompare()) {
1282 assert(NumOps == 2 && "Expected 2 register operands for a compare.");
1283 MIB.add(MI.getOperand(NeedsCommute ? 1 : 0));
1285 else if (FusedFPOp) {
1286 MIB.add(MI.getOperand(0));
1287 MIB.add(MI.getOperand(3));
1288 MIB.add(MI.getOperand(OpNum == 1 ? 2 : 1));
1291 MIB.add(MI.getOperand(0));
1293 MIB.add(MI.getOperand(2));
1295 for (unsigned I = 1; I < OpNum; ++I)
1296 MIB.add(MI.getOperand(I));
1298 MIB.addFrameIndex(FrameIndex).addImm(Offset);
1299 if (MemDesc.TSFlags & SystemZII::HasIndex)
1302 unsigned CCValid = MI.getOperand(NumOps).getImm();
1303 unsigned CCMask = MI.getOperand(NumOps + 1).getImm();
1304 MIB.addImm(CCValid);
1305 MIB.addImm(NeedsCommute ? CCMask ^ CCValid : CCMask);
1307 if (MIB->definesRegister(SystemZ::CC) &&
1308 (!MI.definesRegister(SystemZ::CC) ||
1309 MI.registerDefIsDead(SystemZ::CC))) {
1310 MIB->addRegisterDead(SystemZ::CC, TRI);
1312 CCLiveRange->createDeadDef(MISlot, LIS->getVNInfoAllocator());
1314 // Constrain the register classes if converted from a vector opcode. The
1315 // allocated regs are in an FP reg-class per previous check above.
1316 for (const MachineOperand &MO : MIB->operands())
1317 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
1318 Register Reg = MO.getReg();
1319 if (MRI.getRegClass(Reg) == &SystemZ::VR32BitRegClass)
1320 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass);
1321 else if (MRI.getRegClass(Reg) == &SystemZ::VR64BitRegClass)
1322 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass);
1323 else if (MRI.getRegClass(Reg) == &SystemZ::VR128BitRegClass)
1324 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass);
1327 transferDeadCC(&MI, MIB);
1328 transferMIFlag(&MI, MIB, MachineInstr::NoSWrap);
1329 transferMIFlag(&MI, MIB, MachineInstr::NoFPExcept);
1336 MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
1337 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1338 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1339 LiveIntervals *LIS) const {
1343 bool SystemZInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1344 switch (MI.getOpcode()) {
1346 splitMove(MI, SystemZ::LG);
1349 case SystemZ::ST128:
1350 splitMove(MI, SystemZ::STG);
1354 splitMove(MI, SystemZ::LD);
1358 splitMove(MI, SystemZ::STD);
1361 case SystemZ::LBMux:
1362 expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
1365 case SystemZ::LHMux:
1366 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
1369 case SystemZ::LLCRMux:
1370 expandZExtPseudo(MI, SystemZ::LLCR, 8);
1373 case SystemZ::LLHRMux:
1374 expandZExtPseudo(MI, SystemZ::LLHR, 16);
1377 case SystemZ::LLCMux:
1378 expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
1381 case SystemZ::LLHMux:
1382 expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
1386 expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
1389 case SystemZ::LOCMux:
1390 expandLOCPseudo(MI, SystemZ::LOC, SystemZ::LOCFH);
1393 case SystemZ::LOCHIMux:
1394 expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1397 case SystemZ::STCMux:
1398 expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
1401 case SystemZ::STHMux:
1402 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
1405 case SystemZ::STMux:
1406 expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
1409 case SystemZ::STOCMux:
1410 expandLOCPseudo(MI, SystemZ::STOC, SystemZ::STOCFH);
1413 case SystemZ::LHIMux:
1414 expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
1417 case SystemZ::IIFMux:
1418 expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
1421 case SystemZ::IILMux:
1422 expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
1425 case SystemZ::IIHMux:
1426 expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
1429 case SystemZ::NIFMux:
1430 expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
1433 case SystemZ::NILMux:
1434 expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
1437 case SystemZ::NIHMux:
1438 expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
1441 case SystemZ::OIFMux:
1442 expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
1445 case SystemZ::OILMux:
1446 expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
1449 case SystemZ::OIHMux:
1450 expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
1453 case SystemZ::XIFMux:
1454 expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
1457 case SystemZ::TMLMux:
1458 expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1461 case SystemZ::TMHMux:
1462 expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1465 case SystemZ::AHIMux:
1466 expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1469 case SystemZ::AHIMuxK:
1470 expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1473 case SystemZ::AFIMux:
1474 expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1477 case SystemZ::CHIMux:
1478 expandRIPseudo(MI, SystemZ::CHI, SystemZ::CIH, false);
1481 case SystemZ::CFIMux:
1482 expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1485 case SystemZ::CLFIMux:
1486 expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1490 expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1493 case SystemZ::CLMux:
1494 expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1497 case SystemZ::RISBMux: {
1498 bool DestIsHigh = SystemZ::isHighReg(MI.getOperand(0).getReg());
1499 bool SrcIsHigh = SystemZ::isHighReg(MI.getOperand(2).getReg());
1500 if (SrcIsHigh == DestIsHigh)
1501 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1503 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1504 MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);
1509 case SystemZ::ADJDYNALLOC:
1510 splitAdjDynAlloc(MI);
1513 case TargetOpcode::LOAD_STACK_GUARD:
1514 expandLoadStackGuard(&MI);
1522 unsigned SystemZInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
1523 if (MI.isInlineAsm()) {
1524 const MachineFunction *MF = MI.getParent()->getParent();
1525 const char *AsmStr = MI.getOperand(0).getSymbolName();
1526 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1528 else if (MI.getOpcode() == SystemZ::PATCHPOINT)
1529 return PatchPointOpers(&MI).getNumPatchBytes();
1530 else if (MI.getOpcode() == SystemZ::STACKMAP)
1531 return MI.getOperand(1).getImm();
1532 else if (MI.getOpcode() == SystemZ::FENTRY_CALL)
1535 return MI.getDesc().getSize();
1539 SystemZInstrInfo::getBranchInfo(const MachineInstr &MI) const {
1540 switch (MI.getOpcode()) {
1545 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
1546 SystemZ::CCMASK_ANY, &MI.getOperand(0));
1550 return SystemZII::Branch(SystemZII::BranchNormal, MI.getOperand(0).getImm(),
1551 MI.getOperand(1).getImm(), &MI.getOperand(2));
1554 case SystemZ::BRCTH:
1555 return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
1556 SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1558 case SystemZ::BRCTG:
1559 return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
1560 SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1564 return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
1565 MI.getOperand(2).getImm(), &MI.getOperand(3));
1569 return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP,
1570 MI.getOperand(2).getImm(), &MI.getOperand(3));
1574 return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
1575 MI.getOperand(2).getImm(), &MI.getOperand(3));
1577 case SystemZ::CLGIJ:
1578 case SystemZ::CLGRJ:
1579 return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP,
1580 MI.getOperand(2).getImm(), &MI.getOperand(3));
1582 case SystemZ::INLINEASM_BR:
1583 // Don't try to analyze asm goto, so pass nullptr as branch target argument.
1584 return SystemZII::Branch(SystemZII::AsmGoto, 0, 0, nullptr);
1587 llvm_unreachable("Unrecognized branch opcode");
1591 void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
1592 unsigned &LoadOpcode,
1593 unsigned &StoreOpcode) const {
1594 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1595 LoadOpcode = SystemZ::L;
1596 StoreOpcode = SystemZ::ST;
1597 } else if (RC == &SystemZ::GRH32BitRegClass) {
1598 LoadOpcode = SystemZ::LFH;
1599 StoreOpcode = SystemZ::STFH;
1600 } else if (RC == &SystemZ::GRX32BitRegClass) {
1601 LoadOpcode = SystemZ::LMux;
1602 StoreOpcode = SystemZ::STMux;
1603 } else if (RC == &SystemZ::GR64BitRegClass ||
1604 RC == &SystemZ::ADDR64BitRegClass) {
1605 LoadOpcode = SystemZ::LG;
1606 StoreOpcode = SystemZ::STG;
1607 } else if (RC == &SystemZ::GR128BitRegClass ||
1608 RC == &SystemZ::ADDR128BitRegClass) {
1609 LoadOpcode = SystemZ::L128;
1610 StoreOpcode = SystemZ::ST128;
1611 } else if (RC == &SystemZ::FP32BitRegClass) {
1612 LoadOpcode = SystemZ::LE;
1613 StoreOpcode = SystemZ::STE;
1614 } else if (RC == &SystemZ::FP64BitRegClass) {
1615 LoadOpcode = SystemZ::LD;
1616 StoreOpcode = SystemZ::STD;
1617 } else if (RC == &SystemZ::FP128BitRegClass) {
1618 LoadOpcode = SystemZ::LX;
1619 StoreOpcode = SystemZ::STX;
1620 } else if (RC == &SystemZ::VR32BitRegClass) {
1621 LoadOpcode = SystemZ::VL32;
1622 StoreOpcode = SystemZ::VST32;
1623 } else if (RC == &SystemZ::VR64BitRegClass) {
1624 LoadOpcode = SystemZ::VL64;
1625 StoreOpcode = SystemZ::VST64;
1626 } else if (RC == &SystemZ::VF128BitRegClass ||
1627 RC == &SystemZ::VR128BitRegClass) {
1628 LoadOpcode = SystemZ::VL;
1629 StoreOpcode = SystemZ::VST;
1631 llvm_unreachable("Unsupported regclass to load or store");
1634 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1636 const MachineInstr *MI) const {
1637 const MCInstrDesc &MCID = get(Opcode);
1638 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1639 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1640 // Get the instruction to use for unsigned 12-bit displacements.
1641 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1642 if (Disp12Opcode >= 0)
1643 return Disp12Opcode;
1645 // All address-related instructions can use unsigned 12-bit
1649 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1650 // Get the instruction to use for signed 20-bit displacements.
1651 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1652 if (Disp20Opcode >= 0)
1653 return Disp20Opcode;
1655 // Check whether Opcode allows signed 20-bit displacements.
1656 if (MCID.TSFlags & SystemZII::Has20BitOffset)
1659 // If a VR32/VR64 reg ended up in an FP register, use the FP opcode.
1660 if (MI && MI->getOperand(0).isReg()) {
1661 Register Reg = MI->getOperand(0).getReg();
1662 if (Reg.isPhysical() && SystemZMC::getFirstReg(Reg) < 16) {
1665 return SystemZ::LEY;
1666 case SystemZ::VST32:
1667 return SystemZ::STEY;
1669 return SystemZ::LDY;
1670 case SystemZ::VST64:
1671 return SystemZ::STDY;
1680 bool SystemZInstrInfo::hasDisplacementPairInsn(unsigned Opcode) const {
1681 const MCInstrDesc &MCID = get(Opcode);
1682 if (MCID.TSFlags & SystemZII::Has20BitOffset)
1683 return SystemZ::getDisp12Opcode(Opcode) >= 0;
1684 return SystemZ::getDisp20Opcode(Opcode) >= 0;
1687 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1689 case SystemZ::L: return SystemZ::LT;
1690 case SystemZ::LY: return SystemZ::LT;
1691 case SystemZ::LG: return SystemZ::LTG;
1692 case SystemZ::LGF: return SystemZ::LTGF;
1693 case SystemZ::LR: return SystemZ::LTR;
1694 case SystemZ::LGFR: return SystemZ::LTGFR;
1695 case SystemZ::LGR: return SystemZ::LTGR;
1696 case SystemZ::LER: return SystemZ::LTEBR;
1697 case SystemZ::LDR: return SystemZ::LTDBR;
1698 case SystemZ::LXR: return SystemZ::LTXBR;
1699 case SystemZ::LCDFR: return SystemZ::LCDBR;
1700 case SystemZ::LPDFR: return SystemZ::LPDBR;
1701 case SystemZ::LNDFR: return SystemZ::LNDBR;
1702 case SystemZ::LCDFR_32: return SystemZ::LCEBR;
1703 case SystemZ::LPDFR_32: return SystemZ::LPEBR;
1704 case SystemZ::LNDFR_32: return SystemZ::LNEBR;
1705 // On zEC12 we prefer to use RISBGN. But if there is a chance to
1706 // actually use the condition code, we may turn it back into RISGB.
1707 // Note that RISBG is not really a "load-and-test" instruction,
1708 // but sets the same condition code values, so is OK to use here.
1709 case SystemZ::RISBGN: return SystemZ::RISBG;
1714 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
1715 // have already been filtered out. Store the first set bit in LSB and
1716 // the number of set bits in Length if so.
1717 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1718 unsigned First = findFirstSet(Mask);
1719 uint64_t Top = (Mask >> First) + 1;
1720 if ((Top & -Top) == Top) {
1722 Length = findFirstSet(Top);
1728 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
1729 unsigned &Start, unsigned &End) const {
1730 // Reject trivial all-zero masks.
1731 Mask &= allOnes(BitSize);
1735 // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
1736 // the msb and End specifies the index of the lsb.
1737 unsigned LSB, Length;
1738 if (isStringOfOnes(Mask, LSB, Length)) {
1739 Start = 63 - (LSB + Length - 1);
1744 // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
1745 // of the low 1s and End specifies the lsb of the high 1s.
1746 if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
1747 assert(LSB > 0 && "Bottom bit must be set");
1748 assert(LSB + Length < BitSize && "Top bit must be set");
1749 Start = 63 - (LSB - 1);
1750 End = 63 - (LSB + Length);
1757 unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
1758 SystemZII::FusedCompareType Type,
1759 const MachineInstr *MI) const {
1763 if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
1767 case SystemZ::CLGFI:
1768 if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
1773 if (!STI.hasMiscellaneousExtensions())
1775 if (!(MI && MI->getOperand(3).getReg() == 0))
1780 case SystemZII::CompareAndBranch:
1783 return SystemZ::CRJ;
1785 return SystemZ::CGRJ;
1787 return SystemZ::CIJ;
1789 return SystemZ::CGIJ;
1791 return SystemZ::CLRJ;
1793 return SystemZ::CLGRJ;
1795 return SystemZ::CLIJ;
1796 case SystemZ::CLGFI:
1797 return SystemZ::CLGIJ;
1801 case SystemZII::CompareAndReturn:
1804 return SystemZ::CRBReturn;
1806 return SystemZ::CGRBReturn;
1808 return SystemZ::CIBReturn;
1810 return SystemZ::CGIBReturn;
1812 return SystemZ::CLRBReturn;
1814 return SystemZ::CLGRBReturn;
1816 return SystemZ::CLIBReturn;
1817 case SystemZ::CLGFI:
1818 return SystemZ::CLGIBReturn;
1822 case SystemZII::CompareAndSibcall:
1825 return SystemZ::CRBCall;
1827 return SystemZ::CGRBCall;
1829 return SystemZ::CIBCall;
1831 return SystemZ::CGIBCall;
1833 return SystemZ::CLRBCall;
1835 return SystemZ::CLGRBCall;
1837 return SystemZ::CLIBCall;
1838 case SystemZ::CLGFI:
1839 return SystemZ::CLGIBCall;
1843 case SystemZII::CompareAndTrap:
1846 return SystemZ::CRT;
1848 return SystemZ::CGRT;
1850 return SystemZ::CIT;
1852 return SystemZ::CGIT;
1854 return SystemZ::CLRT;
1856 return SystemZ::CLGRT;
1858 return SystemZ::CLFIT;
1859 case SystemZ::CLGFI:
1860 return SystemZ::CLGIT;
1862 return SystemZ::CLT;
1864 return SystemZ::CLGT;
1872 bool SystemZInstrInfo::
1873 prepareCompareSwapOperands(MachineBasicBlock::iterator const MBBI) const {
1874 assert(MBBI->isCompare() && MBBI->getOperand(0).isReg() &&
1875 MBBI->getOperand(1).isReg() && !MBBI->mayLoad() &&
1876 "Not a compare reg/reg.");
1878 MachineBasicBlock *MBB = MBBI->getParent();
1880 SmallVector<MachineInstr *, 4> CCUsers;
1881 for (MachineBasicBlock::iterator Itr = std::next(MBBI);
1882 Itr != MBB->end(); ++Itr) {
1883 if (Itr->readsRegister(SystemZ::CC)) {
1884 unsigned Flags = Itr->getDesc().TSFlags;
1885 if ((Flags & SystemZII::CCMaskFirst) || (Flags & SystemZII::CCMaskLast))
1886 CCUsers.push_back(&*Itr);
1890 if (Itr->definesRegister(SystemZ::CC)) {
1896 LivePhysRegs LiveRegs(*MBB->getParent()->getSubtarget().getRegisterInfo());
1897 LiveRegs.addLiveOuts(*MBB);
1898 if (LiveRegs.contains(SystemZ::CC))
1902 // Update all CC users.
1903 for (unsigned Idx = 0; Idx < CCUsers.size(); ++Idx) {
1904 unsigned Flags = CCUsers[Idx]->getDesc().TSFlags;
1905 unsigned FirstOpNum = ((Flags & SystemZII::CCMaskFirst) ?
1906 0 : CCUsers[Idx]->getNumExplicitOperands() - 2);
1907 MachineOperand &CCMaskMO = CCUsers[Idx]->getOperand(FirstOpNum + 1);
1908 unsigned NewCCMask = SystemZ::reverseCCMask(CCMaskMO.getImm());
1909 CCMaskMO.setImm(NewCCMask);
1915 unsigned SystemZ::reverseCCMask(unsigned CCMask) {
1916 return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1917 (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
1918 (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1919 (CCMask & SystemZ::CCMASK_CMP_UO));
1922 MachineBasicBlock *SystemZ::emitBlockAfter(MachineBasicBlock *MBB) {
1923 MachineFunction &MF = *MBB->getParent();
1924 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
1925 MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
1929 MachineBasicBlock *SystemZ::splitBlockAfter(MachineBasicBlock::iterator MI,
1930 MachineBasicBlock *MBB) {
1931 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
1932 NewMBB->splice(NewMBB->begin(), MBB,
1933 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1934 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
1938 MachineBasicBlock *SystemZ::splitBlockBefore(MachineBasicBlock::iterator MI,
1939 MachineBasicBlock *MBB) {
1940 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
1941 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
1942 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
1946 unsigned SystemZInstrInfo::getLoadAndTrap(unsigned Opcode) const {
1947 if (!STI.hasLoadAndTrap())
1952 return SystemZ::LAT;
1954 return SystemZ::LGAT;
1956 return SystemZ::LFHAT;
1958 return SystemZ::LLGFAT;
1960 return SystemZ::LLGTAT;
1965 void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
1966 MachineBasicBlock::iterator MBBI,
1967 unsigned Reg, uint64_t Value) const {
1968 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1969 unsigned Opcode = 0;
1970 if (isInt<16>(Value))
1971 Opcode = SystemZ::LGHI;
1972 else if (SystemZ::isImmLL(Value))
1973 Opcode = SystemZ::LLILL;
1974 else if (SystemZ::isImmLH(Value)) {
1975 Opcode = SystemZ::LLILH;
1978 else if (isInt<32>(Value))
1979 Opcode = SystemZ::LGFI;
1981 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
1985 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1986 assert (MRI.isSSA() && "Huge values only handled before reg-alloc .");
1987 Register Reg0 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
1988 Register Reg1 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
1989 BuildMI(MBB, MBBI, DL, get(SystemZ::IMPLICIT_DEF), Reg0);
1990 BuildMI(MBB, MBBI, DL, get(SystemZ::IIHF64), Reg1)
1991 .addReg(Reg0).addImm(Value >> 32);
1992 BuildMI(MBB, MBBI, DL, get(SystemZ::IILF64), Reg)
1993 .addReg(Reg1).addImm(Value & ((uint64_t(1) << 32) - 1));
1996 bool SystemZInstrInfo::verifyInstruction(const MachineInstr &MI,
1997 StringRef &ErrInfo) const {
1998 const MCInstrDesc &MCID = MI.getDesc();
1999 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
2000 if (I >= MCID.getNumOperands())
2002 const MachineOperand &Op = MI.getOperand(I);
2003 const MCOperandInfo &MCOI = MCID.OpInfo[I];
2004 // Addressing modes have register and immediate operands. Op should be a
2005 // register (or frame index) operand if MCOI.RegClass contains a valid
2006 // register class, or an immediate otherwise.
2007 if (MCOI.OperandType == MCOI::OPERAND_MEMORY &&
2008 ((MCOI.RegClass != -1 && !Op.isReg() && !Op.isFI()) ||
2009 (MCOI.RegClass == -1 && !Op.isImm()))) {
2010 ErrInfo = "Addressing mode operands corrupt!";
2018 bool SystemZInstrInfo::
2019 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
2020 const MachineInstr &MIb) const {
2022 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand())
2025 // If mem-operands show that the same address Value is used by both
2026 // instructions, check for non-overlapping offsets and widths. Not
2027 // sure if a register based analysis would be an improvement...
2029 MachineMemOperand *MMOa = *MIa.memoperands_begin();
2030 MachineMemOperand *MMOb = *MIb.memoperands_begin();
2031 const Value *VALa = MMOa->getValue();
2032 const Value *VALb = MMOb->getValue();
2033 bool SameVal = (VALa && VALb && (VALa == VALb));
2035 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
2036 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
2037 if (PSVa && PSVb && (PSVa == PSVb))
2041 int OffsetA = MMOa->getOffset(), OffsetB = MMOb->getOffset();
2042 int WidthA = MMOa->getSize(), WidthB = MMOb->getSize();
2043 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
2044 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
2045 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
2046 if (LowOffset + LowWidth <= HighOffset)