1 //===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 // The callseq_start node requires the hasSideEffects flag, even though these
14 // instructions are noops on SystemZ.
15 let hasNoSchedulingInfo = 1, hasSideEffects = 1 in {
16 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
17 [(callseq_start timm:$amt1, timm:$amt2)]>;
18 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
19 [(callseq_end timm:$amt1, timm:$amt2)]>;
22 // Takes as input the value of the stack pointer after a dynamic allocation
23 // has been made. Sets the output to the address of the dynamically-
24 // allocated area itself, skipping the outgoing arguments.
26 // This expands to an LA or LAY instruction. We restrict the offset
27 // to the range of LA and keep the LAY range in reserve for when
28 // the size of the outgoing arguments is added.
29 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
30 [(set GR64:$dst, dynalloc12only:$src)]>;
32 let Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1,
33 usesCustomInserter = 1 in
34 def PROBED_ALLOCA : Pseudo<(outs GR64:$dst),
35 (ins GR64:$oldSP, GR64:$space),
36 [(set GR64:$dst, (z_probed_alloca GR64:$oldSP, GR64:$space))]>;
38 let Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1,
40 def PROBED_STACKALLOC : Pseudo<(outs), (ins i64imm:$stacksize), []>;
42 //===----------------------------------------------------------------------===//
43 // Branch instructions
44 //===----------------------------------------------------------------------===//
46 // Conditional branches.
47 let isBranch = 1, isTerminator = 1, Uses = [CC] in {
48 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form
49 // with the condition-code mask being the first operand. It seems friendlier
50 // to use mnemonic forms like JE and JLH when writing out the assembly though.
51 let isCodeGenOnly = 1 in {
52 // An assembler extended mnemonic for BRC.
53 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>;
54 // An assembler extended mnemonic for BRCL. (The extension is "G"
55 // rather than "L" because "JL" is "Jump if Less".)
56 def BRCL : CondBranchRIL<"jg#", 0xC04>;
57 let isIndirectBranch = 1 in {
58 def BC : CondBranchRX<"b#", 0x47>;
59 def BCR : CondBranchRR<"b#r", 0x07>;
60 def BIC : CondBranchRXY<"bi#", 0xe347>,
61 Requires<[FeatureMiscellaneousExtensions2]>;
65 // Allow using the raw forms directly from the assembler (and occasional
66 // special code generation needs) as well.
67 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>;
68 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>;
69 let isIndirectBranch = 1 in {
70 def BCAsm : AsmCondBranchRX<"bc", 0x47>;
71 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>;
72 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>,
73 Requires<[FeatureMiscellaneousExtensions2]>;
76 // Define AsmParser extended mnemonics for each general condition-code mask
77 // (integer or floating-point)
78 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE",
79 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in {
80 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>;
81 def JGAsm#V : FixedCondBranchRIL<CV<V>, "jg#", 0xC04>;
82 let isIndirectBranch = 1 in {
83 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>;
84 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>;
85 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>,
86 Requires<[FeatureMiscellaneousExtensions2]>;
91 // Unconditional branches. These are in fact simply variants of the
92 // conditional branches with the condition mask set to "always".
93 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
94 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>;
95 def JG : FixedCondBranchRIL<CondAlways, "jg", 0xC04>;
96 let isIndirectBranch = 1 in {
97 def B : FixedCondBranchRX<CondAlways, "b", 0x47>;
98 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>;
99 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>,
100 Requires<[FeatureMiscellaneousExtensions2]>;
104 // NOPs. These are again variants of the conditional branches,
105 // with the condition mask set to "never".
106 def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>;
107 def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>;
109 // Fused compare-and-branch instructions.
111 // These instructions do not use or clobber the condition codes.
112 // We nevertheless pretend that the relative compare-and-branch
113 // instructions clobber CC, so that we can lower them to separate
114 // comparisons and BRCLs if the branch ends up being out of range.
115 let isBranch = 1, isTerminator = 1 in {
116 // As for normal branches, we handle these instructions internally in
117 // their raw CRJ-like form, but use assembly macros like CRJE when writing
118 // them out. Using the *Pair multiclasses, we also create the raw forms.
120 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>;
121 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>;
122 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>;
123 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>;
124 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>;
125 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>;
126 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>;
127 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>;
129 let isIndirectBranch = 1 in {
130 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>;
131 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>;
132 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>;
133 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>;
134 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>;
135 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>;
136 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>;
137 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>;
140 // Define AsmParser mnemonics for each integer condition-code mask.
141 foreach V = [ "E", "H", "L", "HE", "LE", "LH",
142 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in {
144 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>;
145 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>;
146 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32,
148 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64,
150 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>;
151 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>;
152 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32,
154 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64,
157 let isIndirectBranch = 1 in {
158 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>;
159 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>;
160 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32,
162 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64,
164 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>;
165 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>;
166 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32,
168 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64,
174 // Decrement a register and branch if it is nonzero. These don't clobber CC,
175 // but we might need to split long relative branches into sequences that do.
176 let isBranch = 1, isTerminator = 1 in {
178 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>;
179 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>;
181 // This doesn't need to clobber CC since we never need to split it.
182 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>,
183 Requires<[FeatureHighWord]>;
185 def BCT : BranchUnaryRX<"bct", 0x46,GR32>;
186 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>;
187 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>;
188 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>;
191 let isBranch = 1, isTerminator = 1 in {
193 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>;
194 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>;
195 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>;
196 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>;
198 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>;
199 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>;
200 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>;
201 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>;
204 //===----------------------------------------------------------------------===//
206 //===----------------------------------------------------------------------===//
208 // Unconditional trap.
209 let hasCtrlDep = 1, hasSideEffects = 1 in
210 def Trap : Alias<4, (outs), (ins), [(trap)]>;
213 let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in
214 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>;
216 // Fused compare-and-trap instructions.
217 let hasCtrlDep = 1, hasSideEffects = 1 in {
218 // These patterns work the same way as for compare-and-branch.
219 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>;
220 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>;
221 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>;
222 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>;
223 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>;
224 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>;
225 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>;
226 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>;
227 let Predicates = [FeatureMiscellaneousExtensions] in {
228 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>;
229 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>;
232 foreach V = [ "E", "H", "L", "HE", "LE", "LH",
233 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in {
234 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>;
235 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>;
236 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>;
237 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>;
238 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32,
240 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64,
242 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32,
244 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64,
246 let Predicates = [FeatureMiscellaneousExtensions] in {
247 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>;
248 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>;
253 //===----------------------------------------------------------------------===//
254 // Call and return instructions
255 //===----------------------------------------------------------------------===//
257 // Define the general form of the call instructions for the asm parser.
258 // These instructions don't hard-code %r14 as the return address register.
259 let isCall = 1, Defs = [CC] in {
260 def BRAS : CallRI <"bras", 0xA75>;
261 def BRASL : CallRIL<"brasl", 0xC05>;
262 def BAS : CallRX <"bas", 0x4D>;
263 def BASR : CallRR <"basr", 0x0D>;
267 let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in {
268 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops),
269 [(z_call pcrel32:$I2)]>;
270 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops),
271 [(z_call ADDR64:$R2)]>;
274 // TLS calls. These will be lowered into a call to __tls_get_offset,
275 // with an extra relocation specifying the TLS symbol.
276 let isCall = 1, Defs = [R14D, CC] in {
277 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops),
278 [(z_tls_gdcall tglobaltlsaddr:$I2)]>;
279 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops),
280 [(z_tls_ldcall tglobaltlsaddr:$I2)]>;
283 // Sibling calls. Indirect sibling calls must be via R1, since R2 upwards
284 // are argument registers and since branching to R0 is a no-op.
285 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
286 def CallJG : Alias<6, (outs), (ins pcrel32:$I2),
287 [(z_sibcall pcrel32:$I2)]>;
289 def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>;
292 // Conditional sibling calls.
293 let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in {
294 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1,
297 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>;
300 // Fused compare and conditional sibling calls.
301 let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in {
302 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
303 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
304 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>;
305 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>;
306 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
307 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
308 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>;
309 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>;
312 // A return instruction (br %r14).
313 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
314 def Return : Alias<2, (outs), (ins), [(z_retflag)]>;
316 // A conditional return instruction (bcr <cond>, %r14).
317 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in
318 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>;
320 // Fused compare and conditional returns.
321 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in {
322 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
323 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
324 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>;
325 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>;
326 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
327 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
328 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>;
329 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>;
332 //===----------------------------------------------------------------------===//
333 // Select instructions
334 //===----------------------------------------------------------------------===//
336 def Select32 : SelectWrapper<i32, GR32>,
337 Requires<[FeatureNoLoadStoreOnCond]>;
338 def Select64 : SelectWrapper<i64, GR64>,
339 Requires<[FeatureNoLoadStoreOnCond]>;
341 // We don't define 32-bit Mux stores if we don't have STOCFH, because the
342 // low-only STOC should then always be used if possible.
343 defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8,
344 nonvolatile_anyextloadi8, bdxaddr20only>,
345 Requires<[FeatureHighWord]>;
346 defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16,
347 nonvolatile_anyextloadi16, bdxaddr20only>,
348 Requires<[FeatureHighWord]>;
349 defm CondStore32Mux : CondStores<GRX32, simple_store,
350 simple_load, bdxaddr20only>,
351 Requires<[FeatureLoadStoreOnCond2]>;
352 defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8,
353 nonvolatile_anyextloadi8, bdxaddr20only>;
354 defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16,
355 nonvolatile_anyextloadi16, bdxaddr20only>;
356 defm CondStore32 : CondStores<GR32, simple_store,
357 simple_load, bdxaddr20only>;
359 defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8,
360 nonvolatile_anyextloadi8, bdxaddr20only>;
361 defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16,
362 nonvolatile_anyextloadi16, bdxaddr20only>;
363 defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32,
364 nonvolatile_anyextloadi32, bdxaddr20only>;
365 defm CondStore64 : CondStores<GR64, simple_store,
366 simple_load, bdxaddr20only>;
368 //===----------------------------------------------------------------------===//
370 //===----------------------------------------------------------------------===//
373 def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>;
374 def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>;
376 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
377 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>;
378 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>;
381 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
382 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>;
385 let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
386 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF,
387 // deopending on the choice of register.
388 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>,
389 Requires<[FeatureHighWord]>;
390 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>;
391 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
393 // Other 16-bit immediates.
394 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
395 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
396 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
397 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
399 // 32-bit immediates.
400 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>;
401 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
402 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
406 let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in {
407 // Expands to L, LY or LFH, depending on the choice of register.
408 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>,
409 Requires<[FeatureHighWord]>;
410 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
411 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>,
412 Requires<[FeatureHighWord]>;
413 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
415 // These instructions are split after register allocation, so we don't
416 // want a custom inserter.
417 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
418 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
419 [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
422 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
423 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>;
424 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>;
427 let canFoldAsLoad = 1 in {
428 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>;
429 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
432 // Load and zero rightmost byte.
433 let Predicates = [FeatureLoadAndZeroRightmostByte] in {
434 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>;
435 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>;
436 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00),
437 (LZRF bdxaddr20only:$src)>;
438 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00),
439 (LZRG bdxaddr20only:$src)>;
443 let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in {
444 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>;
445 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>;
446 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>;
450 let SimpleBDXStore = 1, mayStore = 1 in {
451 // Expands to ST, STY or STFH, depending on the choice of register.
452 def STMux : StoreRXYPseudo<store, GRX32, 4>,
453 Requires<[FeatureHighWord]>;
454 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
455 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>,
456 Requires<[FeatureHighWord]>;
457 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
459 // These instructions are split after register allocation, so we don't
460 // want a custom inserter.
461 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
462 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
463 [(store GR128:$src, bdxaddr20only128:$dst)]>;
466 def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
467 def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
469 // 8-bit immediate stores to 8-bit fields.
470 defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
472 // 16-bit immediate stores to 16-, 32- or 64-bit fields.
473 def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
474 def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>;
475 def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>;
477 // Memory-to-memory moves.
478 let mayLoad = 1, mayStore = 1 in
479 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>;
480 let mayLoad = 1, mayStore = 1, Defs = [CC] in {
481 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>;
482 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>;
483 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>;
487 let Predicates = [FeatureMiscellaneousExtensions3],
488 mayLoad = 1, mayStore = 1, Uses = [R0L] in
489 def MVCRL : SideEffectBinarySSE<"mvcrl", 0xE50A>;
492 let mayLoad = 1, mayStore = 1, Defs = [CC] in
493 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>;
495 //===----------------------------------------------------------------------===//
496 // Conditional move instructions
497 //===----------------------------------------------------------------------===//
499 let Predicates = [FeatureMiscellaneousExtensions3], Uses = [CC] in {
501 let isCommutable = 1 in {
502 // Expands to SELR or SELFHR or a branch-and-move sequence,
503 // depending on the choice of registers.
504 def SELRMux : CondBinaryRRFaPseudo<"MUXselr", GRX32, GRX32, GRX32>;
505 defm SELFHR : CondBinaryRRFaPair<"selfhr", 0xB9C0, GRH32, GRH32, GRH32>;
506 defm SELR : CondBinaryRRFaPair<"selr", 0xB9F0, GR32, GR32, GR32>;
507 defm SELGR : CondBinaryRRFaPair<"selgr", 0xB9E3, GR64, GR64, GR64>;
510 // Define AsmParser extended mnemonics for each general condition-code mask.
511 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE",
512 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in {
513 def SELRAsm#V : FixedCondBinaryRRFa<CV<V>, "selr", 0xB9F0,
515 def SELFHRAsm#V : FixedCondBinaryRRFa<CV<V>, "selfhr", 0xB9C0,
516 GRH32, GRH32, GRH32>;
517 def SELGRAsm#V : FixedCondBinaryRRFa<CV<V>, "selgr", 0xB9E3,
522 let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in {
523 // Load immediate on condition. Matched via DAG pattern and created
524 // by the PeepholeOptimizer via FoldImmediate.
526 // Expands to LOCHI or LOCHHI, depending on the choice of register.
527 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>;
528 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>;
529 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>;
530 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>;
532 // Move register on condition. Matched via DAG pattern and
533 // created by early if-conversion.
534 let isCommutable = 1 in {
535 // Expands to LOCR or LOCFHR or a branch-and-move sequence,
536 // depending on the choice of registers.
537 def LOCRMux : CondBinaryRRFPseudo<"MUXlocr", GRX32, GRX32>;
538 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>;
541 // Load on condition. Matched via DAG pattern.
542 // Expands to LOC or LOCFH, depending on the choice of register.
543 defm LOCMux : CondUnaryRSYPseudoAndMemFold<"MUXloc", simple_load, GRX32, 4>;
544 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, simple_load, GRH32, 4>;
546 // Store on condition. Expanded from CondStore* pseudos.
547 // Expands to STOC or STOCFH, depending on the choice of register.
548 def STOCMux : CondStoreRSYPseudo<GRX32, 4>;
549 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>;
551 // Define AsmParser extended mnemonics for each general condition-code mask.
552 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE",
553 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in {
554 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32,
556 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64,
558 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32,
560 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>;
561 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>;
562 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>;
566 let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in {
567 // Move register on condition. Matched via DAG pattern and
568 // created by early if-conversion.
569 let isCommutable = 1 in {
570 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>;
571 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>;
574 // Load on condition. Matched via DAG pattern.
575 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, simple_load, GR32, 4>;
576 defm LOCG : CondUnaryRSYPairAndMemFold<"locg", 0xEBE2, simple_load, GR64, 8>;
578 // Store on condition. Expanded from CondStore* pseudos.
579 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>;
580 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>;
582 // Define AsmParser extended mnemonics for each general condition-code mask.
583 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE",
584 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in {
585 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>;
586 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>;
587 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>;
588 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>;
589 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>;
590 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>;
593 //===----------------------------------------------------------------------===//
595 //===----------------------------------------------------------------------===//
597 // Note that putting these before zero extensions mean that we will prefer
598 // them for anyextload*. There's not really much to choose between the two
599 // either way, but signed-extending loads have a short LH and a long LHY,
600 // while zero-extending loads have only the long LLH.
602 //===----------------------------------------------------------------------===//
604 // 32-bit extensions from registers.
605 def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>;
606 def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>;
608 // 64-bit extensions from registers.
609 def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>;
610 def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>;
611 def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>;
613 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
614 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>;
616 // Match 32-to-64-bit sign extensions in which the source is already
617 // in a 64-bit register.
618 def : Pat<(sext_inreg GR64:$src, i32),
619 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
621 // 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH,
622 // depending on the choice of register.
623 def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>,
624 Requires<[FeatureHighWord]>;
625 def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>;
626 def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>,
627 Requires<[FeatureHighWord]>;
629 // 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH,
630 // depending on the choice of register.
631 def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>,
632 Requires<[FeatureHighWord]>;
633 defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>;
634 def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>,
635 Requires<[FeatureHighWord]>;
636 def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>;
638 // 64-bit extensions from memory.
639 def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>;
640 def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>;
641 def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>;
642 def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>;
643 def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>;
644 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
645 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>;
647 //===----------------------------------------------------------------------===//
649 //===----------------------------------------------------------------------===//
651 // 32-bit extensions from registers.
653 // Expands to LLCR or RISB[LH]G, depending on the choice of registers.
654 def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>,
655 Requires<[FeatureHighWord]>;
656 def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>;
657 // Expands to LLHR or RISB[LH]G, depending on the choice of registers.
658 def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>,
659 Requires<[FeatureHighWord]>;
660 def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>;
662 // 64-bit extensions from registers.
663 def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>;
664 def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>;
665 def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>;
667 // Match 32-to-64-bit zero extensions in which the source is already
668 // in a 64-bit register.
669 def : Pat<(and GR64:$src, 0xffffffff),
670 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
672 // 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH,
673 // depending on the choice of register.
674 def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>,
675 Requires<[FeatureHighWord]>;
676 def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>;
677 def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>,
678 Requires<[FeatureHighWord]>;
680 // 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH,
681 // depending on the choice of register.
682 def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>,
683 Requires<[FeatureHighWord]>;
684 def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>;
685 def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>,
686 Requires<[FeatureHighWord]>;
687 def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>;
689 // 64-bit extensions from memory.
690 def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>;
691 def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>;
692 def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>;
693 def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>;
694 def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>;
696 // 31-to-64-bit zero extensions.
697 def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>;
698 def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>;
699 def : Pat<(and GR64:$src, 0x7fffffff),
701 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff),
702 (LLGT bdxaddr20only:$src)>;
704 // Load and zero rightmost byte.
705 let Predicates = [FeatureLoadAndZeroRightmostByte] in {
706 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>;
707 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00),
708 (LLZRGF bdxaddr20only:$src)>;
712 let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in {
713 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>;
714 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>;
717 // Extend GR64s to GR128s.
718 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
719 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
721 //===----------------------------------------------------------------------===//
723 //===----------------------------------------------------------------------===//
725 // Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
726 def : Pat<(i64 (anyext GR32:$src)),
727 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>;
729 // Extend GR64s to GR128s.
730 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
731 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
733 //===----------------------------------------------------------------------===//
735 //===----------------------------------------------------------------------===//
737 // Truncations of 64-bit registers to 32-bit registers.
738 def : Pat<(i32 (trunc GR64:$src)),
739 (EXTRACT_SUBREG GR64:$src, subreg_l32)>;
741 // Truncations of 32-bit registers to 8-bit memory. STCMux expands to
742 // STC, STCY or STCH, depending on the choice of register.
743 def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>,
744 Requires<[FeatureHighWord]>;
745 defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>;
746 def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>,
747 Requires<[FeatureHighWord]>;
749 // Truncations of 32-bit registers to 16-bit memory. STHMux expands to
750 // STH, STHY or STHH, depending on the choice of register.
751 def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>,
752 Requires<[FeatureHighWord]>;
753 defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
754 def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>,
755 Requires<[FeatureHighWord]>;
756 def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
758 // Truncations of 64-bit registers to memory.
759 defm : StoreGR64Pair<STC, STCY, truncstorei8>;
760 defm : StoreGR64Pair<STH, STHY, truncstorei16>;
761 def : StoreGR64PC<STHRL, aligned_truncstorei16>;
762 defm : StoreGR64Pair<ST, STY, truncstorei32>;
763 def : StoreGR64PC<STRL, aligned_truncstorei32>;
765 // Store characters under mask -- not (yet) used for codegen.
766 defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>;
767 def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>;
769 //===----------------------------------------------------------------------===//
770 // Multi-register moves
771 //===----------------------------------------------------------------------===//
773 // Multi-register loads.
774 defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>;
775 def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
776 def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>;
777 def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>;
779 // Multi-register stores.
780 defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>;
781 def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
782 def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>;
784 //===----------------------------------------------------------------------===//
786 //===----------------------------------------------------------------------===//
788 // Byte-swapping register moves.
789 def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>;
790 def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>;
792 // Byte-swapping loads.
793 def LRVH : UnaryRXY<"lrvh", 0xE31F, z_loadbswap16, GR32, 2>;
794 def LRV : UnaryRXY<"lrv", 0xE31E, z_loadbswap32, GR32, 4>;
795 def LRVG : UnaryRXY<"lrvg", 0xE30F, z_loadbswap64, GR64, 8>;
797 // Byte-swapping stores.
798 def STRVH : StoreRXY<"strvh", 0xE33F, z_storebswap16, GR32, 2>;
799 def STRV : StoreRXY<"strv", 0xE33E, z_storebswap32, GR32, 4>;
800 def STRVG : StoreRXY<"strvg", 0xE32F, z_storebswap64, GR64, 8>;
802 // Byte-swapping memory-to-memory moves.
803 let mayLoad = 1, mayStore = 1 in
804 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>;
806 //===----------------------------------------------------------------------===//
807 // Load address instructions
808 //===----------------------------------------------------------------------===//
810 // Load BDX-style addresses.
811 let isAsCheapAsAMove = 1, isReMaterializable = 1 in
812 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>;
814 // Load a PC-relative address. There's no version of this instruction
815 // with a 16-bit offset, so there's no relaxation.
816 let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in
817 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>;
819 // Load the Global Offset Table address. This will be lowered into a
820 // larl $R1, _GLOBAL_OFFSET_TABLE_
822 def GOT : Alias<6, (outs GR64:$R1), (ins),
823 [(set GR64:$R1, (global_offset_table))]>;
825 //===----------------------------------------------------------------------===//
826 // Absolute and Negation
827 //===----------------------------------------------------------------------===//
830 let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
831 def LPR : UnaryRR <"lpr", 0x10, z_iabs, GR32, GR32>;
832 def LPGR : UnaryRRE<"lpgr", 0xB900, z_iabs, GR64, GR64>;
834 let CCValues = 0xE, CompareZeroCCMask = 0xE in
835 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>;
837 def : Pat<(z_iabs32 GR32:$src), (LPR GR32:$src)>;
838 def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>;
839 defm : SXU<z_iabs, LPGFR>;
840 defm : SXU<z_iabs64, LPGFR>;
843 let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
844 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>;
845 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>;
847 let CCValues = 0xE, CompareZeroCCMask = 0xE in
848 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>;
850 def : Pat<(z_inegabs32 GR32:$src), (LNR GR32:$src)>;
851 def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>;
852 defm : SXU<z_inegabs, LNGFR>;
853 defm : SXU<z_inegabs64, LNGFR>;
856 let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
857 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>;
858 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>;
860 let CCValues = 0xE, CompareZeroCCMask = 0xE in
861 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>;
863 defm : SXU<ineg, LCGFR>;
865 //===----------------------------------------------------------------------===//
867 //===----------------------------------------------------------------------===//
869 let isCodeGenOnly = 1 in
870 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>;
871 defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>;
873 defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>;
874 defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>;
876 defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>;
877 defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>;
879 // Insert characters under mask -- not (yet) used for codegen.
881 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>;
882 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>;
885 // Insertions of a 16-bit immediate, leaving other bits unaffected.
886 // We don't have or_as_insert equivalents of these operations because
887 // OI is available instead.
889 // IIxMux expands to II[LH]x, depending on the choice of register.
890 def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>,
891 Requires<[FeatureHighWord]>;
892 def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>,
893 Requires<[FeatureHighWord]>;
894 def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
895 def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
896 def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>;
897 def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>;
898 def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>;
899 def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>;
900 def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>;
901 def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>;
903 // ...likewise for 32-bit immediates. For GR32s this is a general
904 // full-width move. (We use IILF rather than something like LLILF
905 // for 32-bit moves because IILF leaves the upper 32 bits of the
907 let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
908 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>,
909 Requires<[FeatureHighWord]>;
910 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
911 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>;
913 def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>;
914 def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>;
916 // An alternative model of inserthf, with the first operand being
917 // a zero-extended value.
918 def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
919 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
922 //===----------------------------------------------------------------------===//
924 //===----------------------------------------------------------------------===//
926 // Addition producing a signed overflow flag.
927 let Defs = [CC], CCValues = 0xF, CCIfNoSignedWrap = 1 in {
928 // Addition of a register.
929 let isCommutable = 1 in {
930 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>;
931 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>;
933 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>;
935 // Addition to a high register.
936 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>,
937 Requires<[FeatureHighWord]>;
938 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>,
939 Requires<[FeatureHighWord]>;
941 // Addition of signed 16-bit immediates.
942 defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>;
943 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>;
944 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>;
946 // Addition of signed 32-bit immediates.
947 def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>,
948 Requires<[FeatureHighWord]>;
949 def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>;
950 def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>,
951 Requires<[FeatureHighWord]>;
952 def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>;
954 // Addition of memory.
955 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, asextloadi16, 2>;
956 defm A : BinaryRXPairAndPseudo<"a", 0x5A, 0xE35A, z_sadd, GR32, load, 4>;
957 def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, asextloadi16, 2>,
958 Requires<[FeatureMiscellaneousExtensions2]>;
959 def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, asextloadi32, 4>;
960 defm AG : BinaryRXYAndPseudo<"ag", 0xE308, z_sadd, GR64, load, 8>;
962 // Addition to memory.
963 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>;
964 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
966 defm : SXB<z_sadd, GR64, AGFR>;
968 // Addition producing a carry.
969 let Defs = [CC], CCValues = 0xF, IsLogical = 1 in {
970 // Addition of a register.
971 let isCommutable = 1 in {
972 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>;
973 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>;
975 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>;
977 // Addition to a high register.
978 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>,
979 Requires<[FeatureHighWord]>;
980 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>,
981 Requires<[FeatureHighWord]>;
983 // Addition of signed 16-bit immediates.
984 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, z_uadd, GR32, imm32sx16>,
985 Requires<[FeatureDistinctOps]>;
986 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, z_uadd, GR64, imm64sx16>,
987 Requires<[FeatureDistinctOps]>;
989 // Addition of unsigned 32-bit immediates.
990 def ALFI : BinaryRIL<"alfi", 0xC2B, z_uadd, GR32, uimm32>;
991 def ALGFI : BinaryRIL<"algfi", 0xC2A, z_uadd, GR64, imm64zx32>;
993 // Addition of signed 32-bit immediates.
994 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>,
995 Requires<[FeatureHighWord]>;
997 // Addition of memory.
998 defm AL : BinaryRXPairAndPseudo<"al", 0x5E, 0xE35E, z_uadd, GR32, load, 4>;
999 def ALGF : BinaryRXY<"algf", 0xE31A, z_uadd, GR64, azextloadi32, 4>;
1000 defm ALG : BinaryRXYAndPseudo<"alg", 0xE30A, z_uadd, GR64, load, 8>;
1002 // Addition to memory.
1003 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>;
1004 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>;
1006 defm : ZXB<z_uadd, GR64, ALGFR>;
1008 // Addition producing and using a carry.
1009 let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in {
1010 // Addition of a register.
1011 def ALCR : BinaryRRE<"alcr", 0xB998, z_addcarry, GR32, GR32>;
1012 def ALCGR : BinaryRRE<"alcgr", 0xB988, z_addcarry, GR64, GR64>;
1014 // Addition of memory.
1015 def ALC : BinaryRXY<"alc", 0xE398, z_addcarry, GR32, load, 4>;
1016 def ALCG : BinaryRXY<"alcg", 0xE388, z_addcarry, GR64, load, 8>;
1019 // Addition that does not modify the condition code.
1020 def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>,
1021 Requires<[FeatureHighWord]>;
1024 //===----------------------------------------------------------------------===//
1026 //===----------------------------------------------------------------------===//
1028 // Subtraction producing a signed overflow flag.
1029 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8,
1030 CCIfNoSignedWrap = 1 in {
1031 // Subtraction of a register.
1032 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, z_ssub, GR32, GR32>;
1033 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>;
1034 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, z_ssub, GR64, GR64>;
1036 // Subtraction from a high register.
1037 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>,
1038 Requires<[FeatureHighWord]>;
1039 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>,
1040 Requires<[FeatureHighWord]>;
1042 // Subtraction of memory.
1043 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, z_ssub, GR32, asextloadi16, 2>;
1044 defm S : BinaryRXPairAndPseudo<"s", 0x5B, 0xE35B, z_ssub, GR32, load, 4>;
1045 def SGH : BinaryRXY<"sgh", 0xE339, z_ssub, GR64, asextloadi16, 2>,
1046 Requires<[FeatureMiscellaneousExtensions2]>;
1047 def SGF : BinaryRXY<"sgf", 0xE319, z_ssub, GR64, asextloadi32, 4>;
1048 defm SG : BinaryRXYAndPseudo<"sg", 0xE309, z_ssub, GR64, load, 8>;
1050 defm : SXB<z_ssub, GR64, SGFR>;
1052 // Subtracting an immediate is the same as adding the negated immediate.
1053 let AddedComplexity = 1 in {
1054 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2),
1055 (AHIMux GR32:$src1, imm32sx16n:$src2)>,
1056 Requires<[FeatureHighWord]>;
1057 def : Pat<(z_ssub GR32:$src1, simm32n:$src2),
1058 (AFIMux GR32:$src1, simm32n:$src2)>,
1059 Requires<[FeatureHighWord]>;
1060 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2),
1061 (AHI GR32:$src1, imm32sx16n:$src2)>;
1062 def : Pat<(z_ssub GR32:$src1, simm32n:$src2),
1063 (AFI GR32:$src1, simm32n:$src2)>;
1064 def : Pat<(z_ssub GR64:$src1, imm64sx16n:$src2),
1065 (AGHI GR64:$src1, imm64sx16n:$src2)>;
1066 def : Pat<(z_ssub GR64:$src1, imm64sx32n:$src2),
1067 (AGFI GR64:$src1, imm64sx32n:$src2)>;
1070 // And vice versa in one special case, where we need to load a
1071 // constant into a register in any case, but the negated constant
1072 // requires fewer instructions to load.
1073 def : Pat<(z_saddo GR64:$src1, imm64lh16n:$src2),
1074 (SGR GR64:$src1, (LLILH imm64lh16n:$src2))>;
1075 def : Pat<(z_saddo GR64:$src1, imm64lf32n:$src2),
1076 (SGR GR64:$src1, (LLILF imm64lf32n:$src2))>;
1078 // Subtraction producing a carry.
1079 let Defs = [CC], CCValues = 0x7, IsLogical = 1 in {
1080 // Subtraction of a register.
1081 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, z_usub, GR32, GR32>;
1082 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>;
1083 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, z_usub, GR64, GR64>;
1085 // Subtraction from a high register.
1086 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>,
1087 Requires<[FeatureHighWord]>;
1088 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>,
1089 Requires<[FeatureHighWord]>;
1091 // Subtraction of unsigned 32-bit immediates.
1092 def SLFI : BinaryRIL<"slfi", 0xC25, z_usub, GR32, uimm32>;
1093 def SLGFI : BinaryRIL<"slgfi", 0xC24, z_usub, GR64, imm64zx32>;
1095 // Subtraction of memory.
1096 defm SL : BinaryRXPairAndPseudo<"sl", 0x5F, 0xE35F, z_usub, GR32, load, 4>;
1097 def SLGF : BinaryRXY<"slgf", 0xE31B, z_usub, GR64, azextloadi32, 4>;
1098 defm SLG : BinaryRXYAndPseudo<"slg", 0xE30B, z_usub, GR64, load, 8>;
1100 defm : ZXB<z_usub, GR64, SLGFR>;
1102 // Subtracting an immediate is the same as adding the negated immediate.
1103 let AddedComplexity = 1 in {
1104 def : Pat<(z_usub GR32:$src1, imm32sx16n:$src2),
1105 (ALHSIK GR32:$src1, imm32sx16n:$src2)>,
1106 Requires<[FeatureDistinctOps]>;
1107 def : Pat<(z_usub GR64:$src1, imm64sx16n:$src2),
1108 (ALGHSIK GR64:$src1, imm64sx16n:$src2)>,
1109 Requires<[FeatureDistinctOps]>;
1112 // And vice versa in one special case (but we prefer addition).
1113 def : Pat<(add GR64:$src1, imm64zx32n:$src2),
1114 (SLGFI GR64:$src1, imm64zx32n:$src2)>;
1116 // Subtraction producing and using a carry.
1117 let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in {
1118 // Subtraction of a register.
1119 def SLBR : BinaryRRE<"slbr", 0xB999, z_subcarry, GR32, GR32>;
1120 def SLBGR : BinaryRRE<"slbgr", 0xB989, z_subcarry, GR64, GR64>;
1122 // Subtraction of memory.
1123 def SLB : BinaryRXY<"slb", 0xE399, z_subcarry, GR32, load, 4>;
1124 def SLBG : BinaryRXY<"slbg", 0xE389, z_subcarry, GR64, load, 8>;
1128 //===----------------------------------------------------------------------===//
1130 //===----------------------------------------------------------------------===//
1132 let Defs = [CC] in {
1133 // ANDs of a register.
1134 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1135 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>;
1136 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>;
1139 let isConvertibleToThreeAddress = 1 in {
1140 // ANDs of a 16-bit immediate, leaving other bits unaffected.
1141 // The CC result only reflects the 16-bit field, not the full register.
1143 // NIxMux expands to NI[LH]x, depending on the choice of register.
1144 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>,
1145 Requires<[FeatureHighWord]>;
1146 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>,
1147 Requires<[FeatureHighWord]>;
1148 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
1149 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
1150 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>;
1151 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>;
1152 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>;
1153 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>;
1154 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>;
1155 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>;
1157 // ANDs of a 32-bit immediate, leaving other bits unaffected.
1158 // The CC result only reflects the 32-bit field, which means we can
1159 // use it as a zero indicator for i32 operations but not otherwise.
1160 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1161 // Expands to NILF or NIHF, depending on the choice of register.
1162 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>,
1163 Requires<[FeatureHighWord]>;
1164 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
1165 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>;
1167 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>;
1168 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>;
1172 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1173 defm N : BinaryRXPairAndPseudo<"n", 0x54, 0xE354, and, GR32, load, 4>;
1174 defm NG : BinaryRXYAndPseudo<"ng", 0xE380, and, GR64, load, 8>;
1178 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>;
1181 let mayLoad = 1, mayStore = 1 in
1182 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>;
1184 defm : RMWIByte<and, bdaddr12pair, NI>;
1185 defm : RMWIByte<and, bdaddr20pair, NIY>;
1187 //===----------------------------------------------------------------------===//
1189 //===----------------------------------------------------------------------===//
1191 let Defs = [CC] in {
1192 // ORs of a register.
1193 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1194 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>;
1195 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>;
1198 // ORs of a 16-bit immediate, leaving other bits unaffected.
1199 // The CC result only reflects the 16-bit field, not the full register.
1201 // OIxMux expands to OI[LH]x, depending on the choice of register.
1202 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>,
1203 Requires<[FeatureHighWord]>;
1204 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>,
1205 Requires<[FeatureHighWord]>;
1206 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
1207 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
1208 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>;
1209 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>;
1210 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>;
1211 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>;
1212 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>;
1213 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>;
1215 // ORs of a 32-bit immediate, leaving other bits unaffected.
1216 // The CC result only reflects the 32-bit field, which means we can
1217 // use it as a zero indicator for i32 operations but not otherwise.
1218 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1219 // Expands to OILF or OIHF, depending on the choice of register.
1220 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>,
1221 Requires<[FeatureHighWord]>;
1222 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
1223 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>;
1225 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>;
1226 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>;
1229 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1230 defm O : BinaryRXPairAndPseudo<"o", 0x56, 0xE356, or, GR32, load, 4>;
1231 defm OG : BinaryRXYAndPseudo<"og", 0xE381, or, GR64, load, 8>;
1235 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>;
1238 let mayLoad = 1, mayStore = 1 in
1239 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>;
1241 defm : RMWIByte<or, bdaddr12pair, OI>;
1242 defm : RMWIByte<or, bdaddr20pair, OIY>;
1244 //===----------------------------------------------------------------------===//
1246 //===----------------------------------------------------------------------===//
1248 let Defs = [CC] in {
1249 // XORs of a register.
1250 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1251 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>;
1252 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>;
1255 // XORs of a 32-bit immediate, leaving other bits unaffected.
1256 // The CC result only reflects the 32-bit field, which means we can
1257 // use it as a zero indicator for i32 operations but not otherwise.
1258 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1259 // Expands to XILF or XIHF, depending on the choice of register.
1260 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>,
1261 Requires<[FeatureHighWord]>;
1262 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
1263 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>;
1265 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>;
1266 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>;
1269 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1270 defm X : BinaryRXPairAndPseudo<"x",0x57, 0xE357, xor, GR32, load, 4>;
1271 defm XG : BinaryRXYAndPseudo<"xg", 0xE382, xor, GR64, load, 8>;
1275 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>;
1278 let mayLoad = 1, mayStore = 1 in
1279 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>;
1281 defm : RMWIByte<xor, bdaddr12pair, XI>;
1282 defm : RMWIByte<xor, bdaddr20pair, XIY>;
1284 //===----------------------------------------------------------------------===//
1285 // Combined logical operations
1286 //===----------------------------------------------------------------------===//
1288 let Predicates = [FeatureMiscellaneousExtensions3],
1290 // AND with complement.
1291 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1292 def NCRK : BinaryRRFa<"ncrk", 0xB9F5, andc, GR32, GR32, GR32>;
1293 def NCGRK : BinaryRRFa<"ncgrk", 0xB9E5, andc, GR64, GR64, GR64>;
1296 // OR with complement.
1297 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1298 def OCRK : BinaryRRFa<"ocrk", 0xB975, orc, GR32, GR32, GR32>;
1299 def OCGRK : BinaryRRFa<"ocgrk", 0xB965, orc, GR64, GR64, GR64>;
1303 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1304 def NNRK : BinaryRRFa<"nnrk", 0xB974, nand, GR32, GR32, GR32>;
1305 def NNGRK : BinaryRRFa<"nngrk", 0xB964, nand, GR64, GR64, GR64>;
1309 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1310 def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>;
1311 def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>;
1315 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1316 def NXRK : BinaryRRFa<"nxrk", 0xB977, nxor, GR32, GR32, GR32>;
1317 def NXGRK : BinaryRRFa<"nxgrk", 0xB967, nxor, GR64, GR64, GR64>;
1321 //===----------------------------------------------------------------------===//
1323 //===----------------------------------------------------------------------===//
1325 // Multiplication of a register, setting the condition code. We prefer these
1326 // over MS(G)R if available, even though we cannot use the condition code,
1327 // since they are three-operand instructions.
1328 let Predicates = [FeatureMiscellaneousExtensions2],
1329 Defs = [CC], isCommutable = 1 in {
1330 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>;
1331 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>;
1334 // Multiplication of a register.
1335 let isCommutable = 1 in {
1336 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>;
1337 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>;
1339 def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>;
1340 defm : SXB<mul, GR64, MSGFR>;
1342 // Multiplication of a signed 16-bit immediate.
1343 def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>;
1344 def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;
1346 // Multiplication of a signed 32-bit immediate.
1347 def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>;
1348 def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
1350 // Multiplication of memory.
1351 defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>;
1352 defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>;
1353 def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>,
1354 Requires<[FeatureMiscellaneousExtensions2]>;
1355 def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>;
1356 def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>;
1358 // Multiplication of memory, setting the condition code.
1359 let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in {
1360 defm MSC : BinaryRXYAndPseudo<"msc", 0xE353, null_frag, GR32, load, 4>;
1361 defm MSGC : BinaryRXYAndPseudo<"msgc", 0xE383, null_frag, GR64, load, 8>;
1364 // Multiplication of a register, producing two results.
1365 def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>;
1366 def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>,
1367 Requires<[FeatureMiscellaneousExtensions2]>;
1368 def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>;
1369 def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>;
1371 def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2),
1372 (MGRK GR64:$src1, GR64:$src2)>;
1373 def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2),
1374 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>;
1376 // Multiplication of memory, producing two results.
1377 def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>;
1378 def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>;
1379 def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>,
1380 Requires<[FeatureMiscellaneousExtensions2]>;
1381 def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>;
1382 def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>;
1384 def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))),
1385 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>;
1386 def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))),
1387 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>;
1389 //===----------------------------------------------------------------------===//
1390 // Division and remainder
1391 //===----------------------------------------------------------------------===//
1393 let hasSideEffects = 1 in { // Do not speculatively execute.
1394 // Division and remainder, from registers.
1395 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>;
1396 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>;
1397 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>;
1398 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>;
1399 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>;
1401 // Division and remainder, from memory.
1402 def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>;
1403 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>;
1404 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>;
1405 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>;
1406 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>;
1408 def : Pat<(z_sdivrem GR64:$src1, GR32:$src2),
1409 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>;
1410 def : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))),
1411 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>;
1412 def : Pat<(z_sdivrem GR64:$src1, GR64:$src2),
1413 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>;
1414 def : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))),
1415 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>;
1417 def : Pat<(z_udivrem GR32:$src1, GR32:$src2),
1418 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1,
1419 subreg_l32)), GR32:$src2)>;
1420 def : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))),
1421 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1,
1422 subreg_l32)), bdxaddr20only:$src2)>;
1423 def : Pat<(z_udivrem GR64:$src1, GR64:$src2),
1424 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>;
1425 def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))),
1426 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>;
1428 //===----------------------------------------------------------------------===//
1430 //===----------------------------------------------------------------------===//
1432 // Logical shift left.
1433 defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shiftop<shl>, GR32>;
1434 def SLLG : BinaryRSY<"sllg", 0xEB0D, shiftop<shl>, GR64>;
1435 def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>;
1437 // Arithmetic shift left.
1438 let Defs = [CC] in {
1439 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>;
1440 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>;
1441 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>;
1444 // Logical shift right.
1445 defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, shiftop<srl>, GR32>;
1446 def SRLG : BinaryRSY<"srlg", 0xEB0C, shiftop<srl>, GR64>;
1447 def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>;
1449 // Arithmetic shift right.
1450 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
1451 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>;
1452 def SRAG : BinaryRSY<"srag", 0xEB0A, shiftop<sra>, GR64>;
1453 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>;
1457 def RLL : BinaryRSY<"rll", 0xEB1D, shiftop<rotl>, GR32>;
1458 def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>;
1460 // Rotate second operand left and inserted selected bits into first operand.
1461 // These can act like 32-bit operands provided that the constant start and
1462 // end bits (operands 2 and 3) are in the range [32, 64).
1463 let Defs = [CC] in {
1464 let isCodeGenOnly = 1 in
1465 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
1466 let CCValues = 0xE, CompareZeroCCMask = 0xE in
1467 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
1470 // On zEC12 we have a variant of RISBG that does not set CC.
1471 let Predicates = [FeatureMiscellaneousExtensions] in
1472 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>;
1474 // Forms of RISBG that only affect one word of the destination register.
1475 // They do not set CC.
1476 let Predicates = [FeatureHighWord] in {
1477 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>;
1478 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>;
1479 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>;
1480 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>;
1481 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>;
1482 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>;
1483 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>;
1486 // Rotate second operand left and perform a logical operation with selected
1487 // bits of the first operand. The CC result only describes the selected bits,
1488 // so isn't useful for a full comparison against zero.
1489 let Defs = [CC] in {
1490 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
1491 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
1492 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
1495 //===----------------------------------------------------------------------===//
1497 //===----------------------------------------------------------------------===//
1499 // Signed comparisons. We put these before the unsigned comparisons because
1500 // some of the signed forms have COMPARE AND BRANCH equivalents whereas none
1501 // of the unsigned forms do.
1502 let Defs = [CC], CCValues = 0xE in {
1503 // Comparison with a register.
1504 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>;
1505 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>;
1506 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>;
1508 // Comparison with a high register.
1509 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>,
1510 Requires<[FeatureHighWord]>;
1511 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>,
1512 Requires<[FeatureHighWord]>;
1514 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH,
1515 // depending on the choice of register.
1516 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>,
1517 Requires<[FeatureHighWord]>;
1518 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>;
1519 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>;
1521 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH,
1522 // depending on the choice of register.
1523 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>,
1524 Requires<[FeatureHighWord]>;
1525 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>;
1526 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>,
1527 Requires<[FeatureHighWord]>;
1528 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>;
1530 // Comparison with memory.
1531 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>;
1532 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>,
1533 Requires<[FeatureHighWord]>;
1534 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>;
1535 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>,
1536 Requires<[FeatureHighWord]>;
1537 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>;
1538 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>;
1539 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>;
1540 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>;
1541 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>;
1542 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>;
1543 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>;
1544 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>;
1546 // Comparison between memory and a signed 16-bit immediate.
1547 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>;
1548 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>;
1549 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>;
1551 defm : SXB<z_scmp, GR64, CGFR>;
1553 // Unsigned comparisons.
1554 let Defs = [CC], CCValues = 0xE, IsLogical = 1 in {
1555 // Comparison with a register.
1556 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>;
1557 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>;
1558 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>;
1560 // Comparison with a high register.
1561 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>,
1562 Requires<[FeatureHighWord]>;
1563 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>,
1564 Requires<[FeatureHighWord]>;
1566 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI
1567 // or CLIH, depending on the choice of register.
1568 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>,
1569 Requires<[FeatureHighWord]>;
1570 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>;
1571 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>,
1572 Requires<[FeatureHighWord]>;
1573 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
1575 // Comparison with memory.
1576 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>,
1577 Requires<[FeatureHighWord]>;
1578 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>;
1579 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>,
1580 Requires<[FeatureHighWord]>;
1581 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>;
1582 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>;
1583 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32,
1584 aligned_azextloadi16>;
1585 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32,
1587 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,
1588 aligned_azextloadi16>;
1589 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,
1590 aligned_azextloadi32>;
1591 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64,
1594 // Comparison between memory and an unsigned 8-bit immediate.
1595 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>;
1597 // Comparison between memory and an unsigned 16-bit immediate.
1598 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>;
1599 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>;
1600 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>;
1602 defm : ZXB<z_ucmp, GR64, CLGFR>;
1604 // Memory-to-memory comparison.
1605 let mayLoad = 1, Defs = [CC] in {
1606 defm CLC : CompareMemorySS<"clc", 0xD5, z_clc, z_clc_loop>;
1607 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>;
1608 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>;
1609 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>;
1612 // String comparison.
1613 let mayLoad = 1, Defs = [CC] in
1614 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>;
1617 let Defs = [CC] in {
1618 // TMxMux expands to TM[LH]x, depending on the choice of register.
1619 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>,
1620 Requires<[FeatureHighWord]>;
1621 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>,
1622 Requires<[FeatureHighWord]>;
1623 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>;
1624 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>;
1625 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>;
1626 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>;
1628 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>;
1629 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>;
1630 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>;
1631 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>;
1633 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>;
1636 def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>;
1637 def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>;
1639 // Compare logical characters under mask -- not (yet) used for codegen.
1640 let Defs = [CC] in {
1641 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>;
1642 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>;
1645 //===----------------------------------------------------------------------===//
1646 // Prefetch and execution hint
1647 //===----------------------------------------------------------------------===//
1649 let mayLoad = 1, mayStore = 1 in {
1650 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>;
1651 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>;
1654 let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in {
1655 // Branch Prediction Preload
1656 def BPP : BranchPreloadSMI<"bpp", 0xC7>;
1657 def BPRP : BranchPreloadMII<"bprp", 0xC5>;
1659 // Next Instruction Access Intent
1660 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>;
1663 //===----------------------------------------------------------------------===//
1664 // Atomic operations
1665 //===----------------------------------------------------------------------===//
1667 // A serialization instruction that acts as a barrier for all memory
1668 // accesses, which expands to "bcr 14, 0".
1669 let hasSideEffects = 1 in
1670 def Serialize : Alias<2, (outs), (ins), []>;
1672 // A pseudo instruction that serves as a compiler barrier.
1673 let hasSideEffects = 1, hasNoSchedulingInfo = 1 in
1674 def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>;
1676 let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {
1677 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>;
1678 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>;
1679 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>;
1680 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>;
1681 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>;
1682 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>;
1683 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>;
1684 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>;
1685 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>;
1686 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>;
1689 def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>;
1690 def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>;
1691 def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>;
1693 def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>;
1694 def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;
1695 let Predicates = [FeatureNoInterlockedAccess1] in {
1696 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>;
1697 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>;
1698 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>;
1699 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>;
1700 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>;
1701 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>;
1704 def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;
1705 def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>;
1706 def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>;
1708 def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>;
1709 def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;
1710 let Predicates = [FeatureNoInterlockedAccess1] in {
1711 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>;
1712 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32,
1714 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32,
1716 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
1717 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>;
1718 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1720 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1722 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1724 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1726 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1728 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1732 def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
1733 def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
1734 let Predicates = [FeatureNoInterlockedAccess1] in {
1735 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>;
1736 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>;
1737 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>;
1738 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>;
1739 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>;
1740 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>;
1741 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>;
1742 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>;
1743 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>;
1744 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>;
1745 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>;
1748 def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;
1749 def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;
1750 let Predicates = [FeatureNoInterlockedAccess1] in {
1751 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>;
1752 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
1753 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>;
1754 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
1755 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
1758 def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
1759 def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand,
1761 def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>;
1762 def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32,
1764 def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32,
1766 def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>;
1767 def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>;
1768 def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1770 def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1772 def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1774 def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1776 def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1778 def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1781 def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
1782 def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>;
1783 def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>;
1785 def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>;
1786 def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>;
1787 def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>;
1789 def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;
1790 def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>;
1791 def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>;
1793 def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;
1794 def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>;
1795 def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>;
1797 def ATOMIC_CMP_SWAPW
1798 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1799 ADDR32:$bitshift, ADDR32:$negbitshift,
1802 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1803 ADDR32:$bitshift, ADDR32:$negbitshift,
1804 uimm32:$bitsize))]> {
1808 let usesCustomInserter = 1;
1809 let hasNoSchedulingInfo = 1;
1813 let mayLoad = 1, Defs = [CC] in
1814 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>;
1816 // Compare and swap.
1817 let Defs = [CC] in {
1818 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>;
1819 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>;
1822 // Compare double and swap.
1823 let Defs = [CC] in {
1824 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>;
1825 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>;
1828 // Compare and swap and store.
1829 let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in
1830 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>;
1832 // Perform locked operation.
1833 let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in
1834 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>;
1836 // Load/store pair from/to quadword.
1837 def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>;
1838 def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>;
1840 // Load pair disjoint.
1841 let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {
1842 def LPD : BinarySSF<"lpd", 0xC84, GR128>;
1843 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>;
1846 //===----------------------------------------------------------------------===//
1847 // Translate and convert
1848 //===----------------------------------------------------------------------===//
1850 let mayLoad = 1, mayStore = 1 in
1851 def TR : SideEffectBinarySSa<"tr", 0xDC>;
1853 let mayLoad = 1, Defs = [CC, R0L, R1D] in {
1854 def TRT : SideEffectBinarySSa<"trt", 0xDD>;
1855 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>;
1858 let mayLoad = 1, mayStore = 1, Uses = [R0L] in
1859 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>;
1861 let mayLoad = 1, Uses = [R1D], Defs = [CC] in {
1862 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>;
1863 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>;
1866 let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in {
1867 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>;
1868 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>;
1869 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>;
1870 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>;
1873 let mayLoad = 1, mayStore = 1, Defs = [CC] in {
1874 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>;
1875 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>;
1876 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>;
1877 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>;
1878 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>;
1879 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>;
1881 let isAsmParserOnly = 1 in {
1882 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>;
1883 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>;
1887 //===----------------------------------------------------------------------===//
1888 // Message-security assist
1889 //===----------------------------------------------------------------------===//
1891 let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in {
1892 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>;
1893 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>;
1895 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>;
1896 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>;
1897 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>;
1899 let Predicates = [FeatureMessageSecurityAssist4] in {
1900 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>;
1901 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>;
1902 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D,
1903 GR128, GR128, GR128>;
1904 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>;
1907 let Predicates = [FeatureMessageSecurityAssist5] in
1908 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>;
1909 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in
1910 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>;
1912 let Predicates = [FeatureMessageSecurityAssist8] in
1913 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929,
1914 GR128, GR128, GR128>;
1916 let Predicates = [FeatureMessageSecurityAssist9] in
1917 def KDSA : SideEffectBinaryMemRRE<"kdsa", 0xB93A, GR64, GR128>;
1920 //===----------------------------------------------------------------------===//
1922 //===----------------------------------------------------------------------===//
1924 // These instructions use and/or modify the guarded storage control
1925 // registers, which we do not otherwise model, so they should have
1927 let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in {
1928 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>;
1929 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>;
1932 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>;
1934 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>;
1937 //===----------------------------------------------------------------------===//
1938 // Decimal arithmetic
1939 //===----------------------------------------------------------------------===//
1941 defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>;
1942 def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>;
1944 defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>;
1945 def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>;
1947 let mayLoad = 1, mayStore = 1 in {
1948 def MVN : SideEffectBinarySSa<"mvn", 0xD1>;
1949 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>;
1950 def MVO : SideEffectBinarySSb<"mvo", 0xF1>;
1952 def PACK : SideEffectBinarySSb<"pack", 0xF2>;
1953 def PKA : SideEffectBinarySSf<"pka", 0xE9>;
1954 def PKU : SideEffectBinarySSf<"pku", 0xE1>;
1955 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>;
1956 let Defs = [CC] in {
1957 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>;
1958 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>;
1962 let mayLoad = 1, mayStore = 1 in {
1963 let Defs = [CC] in {
1964 def AP : SideEffectBinarySSb<"ap", 0xFA>;
1965 def SP : SideEffectBinarySSb<"sp", 0xFB>;
1966 def ZAP : SideEffectBinarySSb<"zap", 0xF8>;
1967 def SRP : SideEffectTernarySSc<"srp", 0xF0>;
1969 def MP : SideEffectBinarySSb<"mp", 0xFC>;
1970 def DP : SideEffectBinarySSb<"dp", 0xFD>;
1971 let Defs = [CC] in {
1972 def ED : SideEffectBinarySSa<"ed", 0xDE>;
1973 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>;
1977 let Defs = [CC] in {
1978 def CP : CompareSSb<"cp", 0xF9>;
1979 def TP : TestRSL<"tp", 0xEBC0>;
1982 //===----------------------------------------------------------------------===//
1984 //===----------------------------------------------------------------------===//
1986 // Read a 32-bit access register into a GR32. As with all GR32 operations,
1987 // the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
1988 // when a 64-bit address is stored in a pair of access registers.
1989 def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>;
1991 // Set access register.
1992 def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>;
1994 // Copy access register.
1995 def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>;
1997 // Load address extended.
1998 defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>;
2000 // Load access multiple.
2001 defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>;
2003 // Store access multiple.
2004 defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>;
2006 //===----------------------------------------------------------------------===//
2007 // Program mask and addressing mode
2008 //===----------------------------------------------------------------------===//
2010 // Extract CC and program mask into a register. CC ends up in bits 29 and 28.
2012 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>;
2014 // Set CC and program mask from a register.
2015 let hasSideEffects = 1, Defs = [CC] in
2016 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>;
2018 // Branch and link - like BAS, but also extracts CC and program mask.
2019 let isCall = 1, Uses = [CC], Defs = [CC] in {
2020 def BAL : CallRX<"bal", 0x45>;
2021 def BALR : CallRR<"balr", 0x05>;
2024 // Test addressing mode.
2026 def TAM : SideEffectInherentE<"tam", 0x010B>;
2028 // Set addressing mode.
2029 let hasSideEffects = 1 in {
2030 def SAM24 : SideEffectInherentE<"sam24", 0x010C>;
2031 def SAM31 : SideEffectInherentE<"sam31", 0x010D>;
2032 def SAM64 : SideEffectInherentE<"sam64", 0x010E>;
2035 // Branch and set mode. Not really a call, but also sets an output register.
2036 let isBranch = 1, isTerminator = 1, isBarrier = 1 in
2037 def BSM : CallRR<"bsm", 0x0B>;
2039 // Branch and save and set mode.
2040 let isCall = 1, Defs = [CC] in
2041 def BASSM : CallRR<"bassm", 0x0C>;
2043 //===----------------------------------------------------------------------===//
2044 // Transactional execution
2045 //===----------------------------------------------------------------------===//
2047 let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in {
2048 // Transaction Begin
2049 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in {
2050 def TBEGIN : TestBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>;
2051 let hasNoSchedulingInfo = 1 in
2052 def TBEGIN_nofloat : TestBinarySILPseudo<z_tbegin_nofloat, imm32zx16>;
2053 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561,
2054 int_s390_tbeginc, imm32zx16>;
2059 def TEND : TestInherentS<"tend", 0xB2F8, z_tend>;
2061 // Transaction Abort
2062 let isTerminator = 1, isBarrier = 1, mayStore = 1,
2063 hasSideEffects = 1 in
2064 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>;
2066 // Nontransactional Store
2067 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>;
2069 // Extract Transaction Nesting Depth
2070 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>;
2073 //===----------------------------------------------------------------------===//
2075 //===----------------------------------------------------------------------===//
2077 let Predicates = [FeatureProcessorAssist] in {
2078 let hasSideEffects = 1 in
2079 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>;
2080 def : Pat<(int_s390_ppa_txassist GR32:$src),
2081 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
2085 //===----------------------------------------------------------------------===//
2086 // Miscellaneous Instructions.
2087 //===----------------------------------------------------------------------===//
2089 // Find leftmost one, AKA count leading zeros. The instruction actually
2090 // returns a pair of GR64s, the first giving the number of leading zeros
2091 // and the second giving a copy of the source with the leftmost one bit
2092 // cleared. We only use the first result here.
2094 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>;
2095 def : Pat<(i64 (ctlz GR64:$src)),
2096 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>;
2098 // Population count. Counts bits set per byte or doubleword.
2099 let Predicates = [FeatureMiscellaneousExtensions3] in {
2101 def POPCNTOpt : BinaryRRFc<"popcnt", 0xB9E1, GR64, GR64>;
2102 def : Pat<(ctpop GR64:$src), (POPCNTOpt GR64:$src, 8)>;
2104 let Predicates = [FeaturePopulationCount], Defs = [CC] in
2105 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>;
2107 // Search a block of memory for a character.
2108 let mayLoad = 1, Defs = [CC] in
2109 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>;
2110 let mayLoad = 1, Defs = [CC], Uses = [R0L] in
2111 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>;
2113 // Compare until substring equal.
2114 let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in
2115 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>;
2117 // Compare and form codeword.
2118 let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in
2119 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>;
2122 let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D],
2123 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in
2124 def UPT : SideEffectInherentE<"upt", 0x0102>;
2127 let mayLoad = 1, Defs = [CC] in
2128 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>;
2130 // Compression call.
2131 let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in
2132 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>;
2135 let Predicates = [FeatureEnhancedSort],
2136 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in
2137 def SORTL : SideEffectBinaryMemMemRRE<"sortl", 0xB938, GR128, GR128>;
2139 // Deflate conversion call.
2140 let Predicates = [FeatureDeflateConversion],
2141 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in
2142 def DFLTCC : SideEffectTernaryMemMemRRFa<"dfltcc", 0xB939,
2143 GR128, GR128, GR64>;
2146 let hasSideEffects = 1 in {
2147 def EX : SideEffectBinaryRX<"ex", 0x44, GR64>;
2148 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>;
2151 //===----------------------------------------------------------------------===//
2152 // .insn directive instructions
2153 //===----------------------------------------------------------------------===//
2155 let isCodeGenOnly = 1, hasSideEffects = 1 in {
2156 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>;
2157 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1,
2159 ".insn ri,$enc,$R1,$I2", []>;
2160 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
2161 AnyReg:$R3, brtarget16:$I2),
2162 ".insn rie,$enc,$R1,$R3,$I2", []>;
2163 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
2165 ".insn ril,$enc,$R1,$I2", []>;
2166 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
2168 ".insn rilu,$enc,$R1,$I2", []>;
2169 def InsnRIS : DirectiveInsnRIS<(outs),
2170 (ins imm64zx48:$enc, AnyReg:$R1,
2171 imm32sx8:$I2, imm32zx4:$M3,
2173 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>;
2174 def InsnRR : DirectiveInsnRR<(outs),
2175 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2),
2176 ".insn rr,$enc,$R1,$R2", []>;
2177 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc,
2178 AnyReg:$R1, AnyReg:$R2),
2179 ".insn rre,$enc,$R1,$R2", []>;
2180 def InsnRRF : DirectiveInsnRRF<(outs),
2181 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
2182 AnyReg:$R3, imm32zx4:$M4),
2183 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>;
2184 def InsnRRS : DirectiveInsnRRS<(outs),
2185 (ins imm64zx48:$enc, AnyReg:$R1,
2186 AnyReg:$R2, imm32zx4:$M3,
2188 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>;
2189 def InsnRS : DirectiveInsnRS<(outs),
2190 (ins imm64zx32:$enc, AnyReg:$R1,
2191 AnyReg:$R3, bdaddr12only:$BD2),
2192 ".insn rs,$enc,$R1,$R3,$BD2", []>;
2193 def InsnRSE : DirectiveInsnRSE<(outs),
2194 (ins imm64zx48:$enc, AnyReg:$R1,
2195 AnyReg:$R3, bdaddr12only:$BD2),
2196 ".insn rse,$enc,$R1,$R3,$BD2", []>;
2197 def InsnRSI : DirectiveInsnRSI<(outs),
2198 (ins imm64zx48:$enc, AnyReg:$R1,
2199 AnyReg:$R3, brtarget16:$RI2),
2200 ".insn rsi,$enc,$R1,$R3,$RI2", []>;
2201 def InsnRSY : DirectiveInsnRSY<(outs),
2202 (ins imm64zx48:$enc, AnyReg:$R1,
2203 AnyReg:$R3, bdaddr20only:$BD2),
2204 ".insn rsy,$enc,$R1,$R3,$BD2", []>;
2205 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1,
2206 bdxaddr12only:$XBD2),
2207 ".insn rx,$enc,$R1,$XBD2", []>;
2208 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
2209 bdxaddr12only:$XBD2),
2210 ".insn rxe,$enc,$R1,$XBD2", []>;
2211 def InsnRXF : DirectiveInsnRXF<(outs),
2212 (ins imm64zx48:$enc, AnyReg:$R1,
2213 AnyReg:$R3, bdxaddr12only:$XBD2),
2214 ".insn rxf,$enc,$R1,$R3,$XBD2", []>;
2215 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
2216 bdxaddr20only:$XBD2),
2217 ".insn rxy,$enc,$R1,$XBD2", []>;
2218 def InsnS : DirectiveInsnS<(outs),
2219 (ins imm64zx32:$enc, bdaddr12only:$BD2),
2220 ".insn s,$enc,$BD2", []>;
2221 def InsnSI : DirectiveInsnSI<(outs),
2222 (ins imm64zx32:$enc, bdaddr12only:$BD1,
2224 ".insn si,$enc,$BD1,$I2", []>;
2225 def InsnSIY : DirectiveInsnSIY<(outs),
2226 (ins imm64zx48:$enc,
2227 bdaddr20only:$BD1, imm32zx8:$I2),
2228 ".insn siy,$enc,$BD1,$I2", []>;
2229 def InsnSIL : DirectiveInsnSIL<(outs),
2230 (ins imm64zx48:$enc, bdaddr12only:$BD1,
2232 ".insn sil,$enc,$BD1,$I2", []>;
2233 def InsnSS : DirectiveInsnSS<(outs),
2234 (ins imm64zx48:$enc, bdraddr12only:$RBD1,
2235 bdaddr12only:$BD2, AnyReg:$R3),
2236 ".insn ss,$enc,$RBD1,$BD2,$R3", []>;
2237 def InsnSSE : DirectiveInsnSSE<(outs),
2238 (ins imm64zx48:$enc,
2239 bdaddr12only:$BD1,bdaddr12only:$BD2),
2240 ".insn sse,$enc,$BD1,$BD2", []>;
2241 def InsnSSF : DirectiveInsnSSF<(outs),
2242 (ins imm64zx48:$enc, bdaddr12only:$BD1,
2243 bdaddr12only:$BD2, AnyReg:$R3),
2244 ".insn ssf,$enc,$BD1,$BD2,$R3", []>;
2247 //===----------------------------------------------------------------------===//
2249 //===----------------------------------------------------------------------===//
2251 // Avoid generating 2 XOR instructions. (xor (and x, y), y) is
2252 // equivalent to (and (xor x, -1), y)
2253 def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y),
2254 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>;
2256 // Shift/rotate instructions only use the last 6 bits of the second operand
2257 // register, so we can safely use NILL (16 fewer bits than NILF) to only AND the
2259 // Complexity is added so that we match this before we match NILF on the AND
2261 let AddedComplexity = 4 in {
2262 def : Pat<(shl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)),
2263 (SLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;
2265 def : Pat<(sra GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)),
2266 (SRA GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;
2268 def : Pat<(srl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)),
2269 (SRL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;
2271 def : Pat<(shl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)),
2272 (SLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;
2274 def : Pat<(sra GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)),
2275 (SRAG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;
2277 def : Pat<(srl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)),
2278 (SRLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;
2280 def : Pat<(rotl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)),
2281 (RLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;
2283 def : Pat<(rotl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)),
2284 (RLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;
2287 // Substitute (x*64-s) with (-s), since shift/rotate instructions only
2288 // use the last 6 bits of the second operand register (making it modulo 64).
2289 let AddedComplexity = 4 in {
2290 def : Pat<(shl GR64:$val, (sub imm32mod64, GR32:$shift)),
2291 (SLLG GR64:$val, (LCR GR32:$shift), 0)>;
2293 def : Pat<(sra GR64:$val, (sub imm32mod64, GR32:$shift)),
2294 (SRAG GR64:$val, (LCR GR32:$shift), 0)>;
2296 def : Pat<(srl GR64:$val, (sub imm32mod64, GR32:$shift)),
2297 (SRLG GR64:$val, (LCR GR32:$shift), 0)>;
2299 def : Pat<(rotl GR64:$val, (sub imm32mod64, GR32:$shift)),
2300 (RLLG GR64:$val, (LCR GR32:$shift), 0)>;
2303 // Peepholes for turning scalar operations into block operations.
2304 defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence,
2306 defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence,
2308 defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence,
2310 defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence,
2311 OCSequence, XCSequence, 1>;
2312 defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence,
2314 defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence,
2316 defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence,