1 //===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 #include "SystemZRegisterInfo.h"
10 #include "SystemZInstrInfo.h"
11 #include "SystemZSubtarget.h"
12 #include "llvm/CodeGen/LiveIntervals.h"
13 #include "llvm/ADT/SmallSet.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/CodeGen/TargetFrameLowering.h"
17 #include "llvm/CodeGen/VirtRegMap.h"
21 #define GET_REGINFO_TARGET_DESC
22 #include "SystemZGenRegisterInfo.inc"
24 SystemZRegisterInfo::SystemZRegisterInfo()
25 : SystemZGenRegisterInfo(SystemZ::R14D) {}
27 // Given that MO is a GRX32 operand, return either GR32 or GRH32 if MO
28 // somehow belongs in it. Otherwise, return GRX32.
29 static const TargetRegisterClass *getRC32(MachineOperand &MO,
30 const VirtRegMap *VRM,
31 const MachineRegisterInfo *MRI) {
32 const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
34 if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
35 MO.getSubReg() == SystemZ::subreg_l32 ||
36 MO.getSubReg() == SystemZ::subreg_hl32)
37 return &SystemZ::GR32BitRegClass;
38 if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
39 MO.getSubReg() == SystemZ::subreg_h32 ||
40 MO.getSubReg() == SystemZ::subreg_hh32)
41 return &SystemZ::GRH32BitRegClass;
43 if (VRM && VRM->hasPhys(MO.getReg())) {
44 Register PhysReg = VRM->getPhys(MO.getReg());
45 if (SystemZ::GR32BitRegClass.contains(PhysReg))
46 return &SystemZ::GR32BitRegClass;
47 assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
48 "Phys reg not in GR32 or GRH32?");
49 return &SystemZ::GRH32BitRegClass;
52 assert (RC == &SystemZ::GRX32BitRegClass);
56 // Pass the registers of RC as hints while making sure that if any of these
57 // registers are copy hints (and therefore already in Hints), hint them
59 static void addHints(ArrayRef<MCPhysReg> Order,
60 SmallVectorImpl<MCPhysReg> &Hints,
61 const TargetRegisterClass *RC,
62 const MachineRegisterInfo *MRI) {
63 SmallSet<unsigned, 4> CopyHints;
64 CopyHints.insert(Hints.begin(), Hints.end());
66 for (MCPhysReg Reg : Order)
67 if (CopyHints.count(Reg) &&
68 RC->contains(Reg) && !MRI->isReserved(Reg))
70 for (MCPhysReg Reg : Order)
71 if (!CopyHints.count(Reg) &&
72 RC->contains(Reg) && !MRI->isReserved(Reg))
76 bool SystemZRegisterInfo::getRegAllocationHints(
77 Register VirtReg, ArrayRef<MCPhysReg> Order,
78 SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
79 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
80 const MachineRegisterInfo *MRI = &MF.getRegInfo();
81 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
82 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
84 bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
85 VirtReg, Order, Hints, MF, VRM, Matrix);
88 // Add any two address hints after any copy hints.
89 SmallSet<unsigned, 4> TwoAddrHints;
90 for (auto &Use : MRI->reg_nodbg_instructions(VirtReg))
91 if (SystemZ::getTwoOperandOpcode(Use.getOpcode()) != -1) {
92 const MachineOperand *VRRegMO = nullptr;
93 const MachineOperand *OtherMO = nullptr;
94 const MachineOperand *CommuMO = nullptr;
95 if (VirtReg == Use.getOperand(0).getReg()) {
96 VRRegMO = &Use.getOperand(0);
97 OtherMO = &Use.getOperand(1);
98 if (Use.isCommutable())
99 CommuMO = &Use.getOperand(2);
100 } else if (VirtReg == Use.getOperand(1).getReg()) {
101 VRRegMO = &Use.getOperand(1);
102 OtherMO = &Use.getOperand(0);
103 } else if (VirtReg == Use.getOperand(2).getReg() &&
104 Use.isCommutable()) {
105 VRRegMO = &Use.getOperand(2);
106 OtherMO = &Use.getOperand(0);
110 auto tryAddHint = [&](const MachineOperand *MO) -> void {
111 Register Reg = MO->getReg();
113 Register::isPhysicalRegister(Reg) ? Reg : VRM->getPhys(Reg);
116 PhysReg = getSubReg(PhysReg, MO->getSubReg());
117 if (VRRegMO->getSubReg())
118 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(),
119 MRI->getRegClass(VirtReg));
120 if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
121 TwoAddrHints.insert(PhysReg);
128 for (MCPhysReg OrderReg : Order)
129 if (TwoAddrHints.count(OrderReg))
130 Hints.push_back(OrderReg);
133 if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
134 SmallVector<Register, 8> Worklist;
135 SmallSet<Register, 4> DoneRegs;
136 Worklist.push_back(VirtReg);
137 while (Worklist.size()) {
138 Register Reg = Worklist.pop_back_val();
139 if (!DoneRegs.insert(Reg).second)
142 for (auto &Use : MRI->reg_instructions(Reg)) {
143 // For LOCRMux, see if the other operand is already a high or low
144 // register, and in that case give the corresponding hints for
145 // VirtReg. LOCR instructions need both operands in either high or
146 // low parts. Same handling for SELRMux.
147 if (Use.getOpcode() == SystemZ::LOCRMux ||
148 Use.getOpcode() == SystemZ::SELRMux) {
149 MachineOperand &TrueMO = Use.getOperand(1);
150 MachineOperand &FalseMO = Use.getOperand(2);
151 const TargetRegisterClass *RC =
152 TRI->getCommonSubClass(getRC32(FalseMO, VRM, MRI),
153 getRC32(TrueMO, VRM, MRI));
154 if (Use.getOpcode() == SystemZ::SELRMux)
155 RC = TRI->getCommonSubClass(RC,
156 getRC32(Use.getOperand(0), VRM, MRI));
157 if (RC && RC != &SystemZ::GRX32BitRegClass) {
158 addHints(Order, Hints, RC, MRI);
159 // Return true to make these hints the only regs available to
160 // RA. This may mean extra spilling but since the alternative is
161 // a jump sequence expansion of the LOCRMux, it is preferred.
165 // Add the other operand of the LOCRMux to the worklist.
167 (TrueMO.getReg() == Reg ? FalseMO.getReg() : TrueMO.getReg());
168 if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)
169 Worklist.push_back(OtherReg);
171 else if (Use.getOpcode() == SystemZ::CHIMux ||
172 Use.getOpcode() == SystemZ::CFIMux) {
173 if (Use.getOperand(1).getImm() == 0) {
174 bool OnlyLMuxes = true;
175 for (MachineInstr &DefMI : MRI->def_instructions(VirtReg))
176 if (DefMI.getOpcode() != SystemZ::LMux)
179 addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI);
180 // Return false to make these hints preferred but not obligatory.
184 } // end CHIMux / CFIMux
189 return BaseImplRetVal;
193 SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
194 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
195 if (MF->getFunction().getCallingConv() == CallingConv::GHC)
196 return CSR_SystemZ_NoRegs_SaveList;
197 if (MF->getFunction().getCallingConv() == CallingConv::AnyReg)
198 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList
199 : CSR_SystemZ_AllRegs_SaveList;
200 if (MF->getSubtarget().getTargetLowering()->supportSwiftError() &&
201 MF->getFunction().getAttributes().hasAttrSomewhere(
202 Attribute::SwiftError))
203 return CSR_SystemZ_SwiftError_SaveList;
204 return CSR_SystemZ_SaveList;
208 SystemZRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
209 CallingConv::ID CC) const {
210 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
211 if (CC == CallingConv::GHC)
212 return CSR_SystemZ_NoRegs_RegMask;
213 if (CC == CallingConv::AnyReg)
214 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask
215 : CSR_SystemZ_AllRegs_RegMask;
216 if (MF.getSubtarget().getTargetLowering()->supportSwiftError() &&
217 MF.getFunction().getAttributes().hasAttrSomewhere(
218 Attribute::SwiftError))
219 return CSR_SystemZ_SwiftError_RegMask;
220 return CSR_SystemZ_RegMask;
224 SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
225 BitVector Reserved(getNumRegs());
226 const SystemZFrameLowering *TFI = getFrameLowering(MF);
228 if (TFI->hasFP(MF)) {
229 // R11D is the frame pointer. Reserve all aliases.
230 Reserved.set(SystemZ::R11D);
231 Reserved.set(SystemZ::R11L);
232 Reserved.set(SystemZ::R11H);
233 Reserved.set(SystemZ::R10Q);
236 // R15D is the stack pointer. Reserve all aliases.
237 Reserved.set(SystemZ::R15D);
238 Reserved.set(SystemZ::R15L);
239 Reserved.set(SystemZ::R15H);
240 Reserved.set(SystemZ::R14Q);
242 // A0 and A1 hold the thread pointer.
243 Reserved.set(SystemZ::A0);
244 Reserved.set(SystemZ::A1);
246 // FPC is the floating-point control register.
247 Reserved.set(SystemZ::FPC);
253 SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
254 int SPAdj, unsigned FIOperandNum,
255 RegScavenger *RS) const {
256 assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
258 MachineBasicBlock &MBB = *MI->getParent();
259 MachineFunction &MF = *MBB.getParent();
261 static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
262 const SystemZFrameLowering *TFI = getFrameLowering(MF);
263 DebugLoc DL = MI->getDebugLoc();
265 // Decompose the frame index into a base and offset.
266 int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
268 int64_t Offset = (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr) +
269 MI->getOperand(FIOperandNum + 1).getImm());
271 // Special handling of dbg_value instructions.
272 if (MI->isDebugValue()) {
273 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
274 MI->getDebugOffset().ChangeToImmediate(Offset);
278 // See if the offset is in range, or if an equivalent instruction that
279 // accepts the offset exists.
280 unsigned Opcode = MI->getOpcode();
281 unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
282 if (OpcodeForOffset) {
283 if (OpcodeForOffset == SystemZ::LE &&
284 MF.getSubtarget<SystemZSubtarget>().hasVector()) {
285 // If LE is ok for offset, use LDE instead on z13.
286 OpcodeForOffset = SystemZ::LDE32;
288 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
291 // Create an anchor point that is in range. Start at 0xffff so that
292 // can use LLILH to load the immediate.
293 int64_t OldOffset = Offset;
294 int64_t Mask = 0xffff;
296 Offset = OldOffset & Mask;
297 OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
299 assert(Mask && "One offset must be OK");
300 } while (!OpcodeForOffset);
302 Register ScratchReg =
303 MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
304 int64_t HighOffset = OldOffset - Offset;
306 if (MI->getDesc().TSFlags & SystemZII::HasIndex
307 && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
308 // Load the offset into the scratch register and use it as an index.
309 // The scratch register then dies here.
310 TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
311 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
312 MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
315 // Load the anchor address into a scratch register.
316 unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
318 BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
319 .addReg(BasePtr).addImm(HighOffset).addReg(0);
321 // Load the high offset into the scratch register and use it as
323 TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
324 BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
325 .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
328 // Use the scratch register as the base. It then dies here.
329 MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
333 MI->setDesc(TII->get(OpcodeForOffset));
334 MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
337 bool SystemZRegisterInfo::shouldCoalesce(MachineInstr *MI,
338 const TargetRegisterClass *SrcRC,
340 const TargetRegisterClass *DstRC,
342 const TargetRegisterClass *NewRC,
343 LiveIntervals &LIS) const {
344 assert (MI->isCopy() && "Only expecting COPY instructions");
346 // Coalesce anything which is not a COPY involving a subreg to/from GR128.
347 if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
348 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
351 // Allow coalescing of a GR128 subreg COPY only if the live ranges are small
352 // and local to one MBB with not too much interferring registers. Otherwise
353 // regalloc may run out of registers.
355 unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
356 Register GR128Reg = MI->getOperand(WideOpNo).getReg();
357 Register GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
358 LiveInterval &IntGR128 = LIS.getInterval(GR128Reg);
359 LiveInterval &IntGRNar = LIS.getInterval(GRNarReg);
361 // Check that the two virtual registers are local to MBB.
362 MachineBasicBlock *MBB = MI->getParent();
363 MachineInstr *FirstMI_GR128 =
364 LIS.getInstructionFromIndex(IntGR128.beginIndex());
365 MachineInstr *FirstMI_GRNar =
366 LIS.getInstructionFromIndex(IntGRNar.beginIndex());
367 MachineInstr *LastMI_GR128 = LIS.getInstructionFromIndex(IntGR128.endIndex());
368 MachineInstr *LastMI_GRNar = LIS.getInstructionFromIndex(IntGRNar.endIndex());
369 if ((!FirstMI_GR128 || FirstMI_GR128->getParent() != MBB) ||
370 (!FirstMI_GRNar || FirstMI_GRNar->getParent() != MBB) ||
371 (!LastMI_GR128 || LastMI_GR128->getParent() != MBB) ||
372 (!LastMI_GRNar || LastMI_GRNar->getParent() != MBB))
375 MachineBasicBlock::iterator MII = nullptr, MEE = nullptr;
384 // Check if coalescing seems safe by finding the set of clobbered physreg
385 // pairs in the region.
386 BitVector PhysClobbered(getNumRegs());
388 for (; MII != MEE; ++MII) {
389 for (const MachineOperand &MO : MII->operands())
390 if (MO.isReg() && Register::isPhysicalRegister(MO.getReg())) {
391 for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
393 if (NewRC->contains(*SI)) {
394 PhysClobbered.set(*SI);
400 // Demand an arbitrary margin of free regs.
401 unsigned const DemandedFreeGR128 = 3;
402 if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
409 SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
410 const SystemZFrameLowering *TFI = getFrameLowering(MF);
411 return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D;
414 const TargetRegisterClass *
415 SystemZRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
416 if (RC == &SystemZ::CCRRegClass)
417 return &SystemZ::GR32BitRegClass;