1 //===-- SystemZShortenInst.cpp - Instruction-shortening pass --------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This pass tries to replace instructions with shorter forms. For example,
10 // IILF can be replaced with LLILL or LLILH if the constant fits and if the
11 // other 32 bits of the GR64 destination are not live.
13 //===----------------------------------------------------------------------===//
15 #include "SystemZTargetMachine.h"
16 #include "llvm/CodeGen/LivePhysRegs.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/TargetRegisterInfo.h"
23 #define DEBUG_TYPE "systemz-shorten-inst"
26 class SystemZShortenInst : public MachineFunctionPass {
29 SystemZShortenInst(const SystemZTargetMachine &tm);
31 StringRef getPassName() const override {
32 return "SystemZ Instruction Shortening";
35 bool processBlock(MachineBasicBlock &MBB);
36 bool runOnMachineFunction(MachineFunction &F) override;
37 MachineFunctionProperties getRequiredProperties() const override {
38 return MachineFunctionProperties().set(
39 MachineFunctionProperties::Property::NoVRegs);
43 bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
44 bool shortenOn0(MachineInstr &MI, unsigned Opcode);
45 bool shortenOn01(MachineInstr &MI, unsigned Opcode);
46 bool shortenOn001(MachineInstr &MI, unsigned Opcode);
47 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
48 bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
49 bool shortenSelect(MachineInstr &MI, unsigned Opcode);
51 const SystemZInstrInfo *TII;
52 const TargetRegisterInfo *TRI;
53 LivePhysRegs LiveRegs;
56 char SystemZShortenInst::ID = 0;
57 } // end anonymous namespace
59 FunctionPass *llvm::createSystemZShortenInstPass(SystemZTargetMachine &TM) {
60 return new SystemZShortenInst(TM);
63 SystemZShortenInst::SystemZShortenInst(const SystemZTargetMachine &tm)
64 : MachineFunctionPass(ID), TII(nullptr) {}
66 // Tie operands if MI has become a two-address instruction.
67 static void tieOpsIfNeeded(MachineInstr &MI) {
68 if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
69 !MI.getOperand(0).isTied())
73 // MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH
74 // are the halfword immediate loads for the same word. Try to use one of them
76 bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned LLIxL,
78 unsigned Reg = MI.getOperand(0).getReg();
79 // The new opcode will clear the other half of the GR64 reg, so
80 // cancel if that is live.
81 unsigned thisSubRegIdx =
82 (SystemZ::GRH32BitRegClass.contains(Reg) ? SystemZ::subreg_h32
83 : SystemZ::subreg_l32);
84 unsigned otherSubRegIdx =
85 (thisSubRegIdx == SystemZ::subreg_l32 ? SystemZ::subreg_h32
86 : SystemZ::subreg_l32);
88 TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass);
89 unsigned OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx);
90 if (LiveRegs.contains(OtherReg))
93 uint64_t Imm = MI.getOperand(1).getImm();
94 if (SystemZ::isImmLL(Imm)) {
95 MI.setDesc(TII->get(LLIxL));
96 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
99 if (SystemZ::isImmLH(Imm)) {
100 MI.setDesc(TII->get(LLIxH));
101 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
102 MI.getOperand(1).setImm(Imm >> 16);
108 // Change MI's opcode to Opcode if register operand 0 has a 4-bit encoding.
109 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) {
110 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) {
111 MI.setDesc(TII->get(Opcode));
117 // Change MI's opcode to Opcode if register operands 0 and 1 have a
119 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) {
120 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
121 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
122 MI.setDesc(TII->get(Opcode));
128 // Change MI's opcode to Opcode if register operands 0, 1 and 2 have a
129 // 4-bit encoding and if operands 0 and 1 are tied. Also ties op 0
130 // with op 1, if MI becomes 2-address.
131 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) {
132 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
133 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
134 SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) {
135 MI.setDesc(TII->get(Opcode));
142 // Calls shortenOn001 if CCLive is false. CC def operand is added in
144 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) {
145 if (!LiveRegs.contains(SystemZ::CC) && shortenOn001(MI, Opcode)) {
146 MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
147 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
153 // MI is a vector-style conversion instruction with the operand order:
154 // destination, source, exact-suppress, rounding-mode. If both registers
155 // have a 4-bit encoding then change it to Opcode, which has operand order:
156 // destination, rouding-mode, source, exact-suppress.
157 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) {
158 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
159 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
160 MachineOperand Dest(MI.getOperand(0));
161 MachineOperand Src(MI.getOperand(1));
162 MachineOperand Suppress(MI.getOperand(2));
163 MachineOperand Mode(MI.getOperand(3));
168 MI.setDesc(TII->get(Opcode));
169 MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
179 // MI is a three-operand select instruction. If one of the sources match
180 // the destination, convert to the equivalent load-on-condition.
181 bool SystemZShortenInst::shortenSelect(MachineInstr &MI, unsigned Opcode) {
182 if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
183 MI.setDesc(TII->get(Opcode));
184 MI.tieOperands(0, 1);
187 if (MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) {
188 TII->commuteInstruction(MI, false, 1, 2);
189 MI.setDesc(TII->get(Opcode));
190 MI.tieOperands(0, 1);
196 // Process all instructions in MBB. Return true if something changed.
197 bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) {
198 bool Changed = false;
200 // Set up the set of live registers at the end of MBB (live out)
202 LiveRegs.addLiveOuts(MBB);
204 // Iterate backwards through the block looking for instructions to change.
205 for (auto MBBI = MBB.rbegin(), MBBE = MBB.rend(); MBBI != MBBE; ++MBBI) {
206 MachineInstr &MI = *MBBI;
207 switch (MI.getOpcode()) {
209 Changed |= shortenIIF(MI, SystemZ::LLILL, SystemZ::LLILH);
213 Changed |= shortenIIF(MI, SystemZ::LLIHL, SystemZ::LLIHH);
217 Changed |= shortenSelect(MI, SystemZ::LOCR);
220 case SystemZ::SELFHR:
221 Changed |= shortenSelect(MI, SystemZ::LOCFHR);
225 Changed |= shortenSelect(MI, SystemZ::LOCGR);
229 Changed |= shortenOn001AddCC(MI, SystemZ::ADBR);
233 Changed |= shortenOn001AddCC(MI, SystemZ::AEBR);
237 Changed |= shortenOn001(MI, SystemZ::DDBR);
241 Changed |= shortenOn001(MI, SystemZ::DEBR);
245 Changed |= shortenFPConv(MI, SystemZ::FIDBRA);
249 Changed |= shortenFPConv(MI, SystemZ::FIEBRA);
253 Changed |= shortenOn01(MI, SystemZ::LDEBR);
257 Changed |= shortenFPConv(MI, SystemZ::LEDBRA);
261 Changed |= shortenOn001(MI, SystemZ::MDBR);
265 Changed |= shortenOn001(MI, SystemZ::MEEBR);
268 case SystemZ::WFLCDB:
269 Changed |= shortenOn01(MI, SystemZ::LCDFR);
272 case SystemZ::WFLCSB:
273 Changed |= shortenOn01(MI, SystemZ::LCDFR_32);
276 case SystemZ::WFLNDB:
277 Changed |= shortenOn01(MI, SystemZ::LNDFR);
280 case SystemZ::WFLNSB:
281 Changed |= shortenOn01(MI, SystemZ::LNDFR_32);
284 case SystemZ::WFLPDB:
285 Changed |= shortenOn01(MI, SystemZ::LPDFR);
288 case SystemZ::WFLPSB:
289 Changed |= shortenOn01(MI, SystemZ::LPDFR_32);
292 case SystemZ::WFSQDB:
293 Changed |= shortenOn01(MI, SystemZ::SQDBR);
296 case SystemZ::WFSQSB:
297 Changed |= shortenOn01(MI, SystemZ::SQEBR);
301 Changed |= shortenOn001AddCC(MI, SystemZ::SDBR);
305 Changed |= shortenOn001AddCC(MI, SystemZ::SEBR);
309 Changed |= shortenOn01(MI, SystemZ::CDBR);
313 Changed |= shortenOn01(MI, SystemZ::CEBR);
317 // For z13 we prefer LDE over LE to avoid partial register dependencies.
318 Changed |= shortenOn0(MI, SystemZ::LDE32);
322 Changed |= shortenOn0(MI, SystemZ::STE);
326 Changed |= shortenOn0(MI, SystemZ::LD);
330 Changed |= shortenOn0(MI, SystemZ::STD);
334 int TwoOperandOpcode = SystemZ::getTwoOperandOpcode(MI.getOpcode());
335 if (TwoOperandOpcode == -1)
338 if ((MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) &&
339 (!MI.isCommutable() ||
340 MI.getOperand(0).getReg() != MI.getOperand(2).getReg() ||
341 !TII->commuteInstruction(MI, false, 1, 2)))
344 MI.setDesc(TII->get(TwoOperandOpcode));
345 MI.tieOperands(0, 1);
346 if (TwoOperandOpcode == SystemZ::SLL ||
347 TwoOperandOpcode == SystemZ::SLA ||
348 TwoOperandOpcode == SystemZ::SRL ||
349 TwoOperandOpcode == SystemZ::SRA) {
350 // These shifts only use the low 6 bits of the shift count.
351 MachineOperand &ImmMO = MI.getOperand(3);
352 ImmMO.setImm(ImmMO.getImm() & 0xfff);
359 LiveRegs.stepBackward(MI);
365 bool SystemZShortenInst::runOnMachineFunction(MachineFunction &F) {
366 if (skipFunction(F.getFunction()))
369 const SystemZSubtarget &ST = F.getSubtarget<SystemZSubtarget>();
370 TII = ST.getInstrInfo();
371 TRI = ST.getRegisterInfo();
374 bool Changed = false;
376 Changed |= processBlock(MBB);