1 //===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 #include "SystemZTargetMachine.h"
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
12 #include "SystemZMachineScheduler.h"
13 #include "SystemZTargetTransformInfo.h"
14 #include "TargetInfo/SystemZTargetInfo.h"
15 #include "llvm/ADT/Optional.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/Analysis/TargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
22 #include "llvm/CodeGen/TargetPassConfig.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/Support/CodeGen.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Target/TargetLoweringObjectFile.h"
27 #include "llvm/Transforms/Scalar.h"
32 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTarget() {
33 // Register the target.
34 RegisterTargetMachine<SystemZTargetMachine> X(getTheSystemZTarget());
37 // Determine whether we use the vector ABI.
38 static bool UsesVectorABI(StringRef CPU, StringRef FS) {
39 // We use the vector ABI whenever the vector facility is avaiable.
40 // This is the case by default if CPU is z13 or later, and can be
41 // overridden via "[+-]vector" feature string elements.
42 bool VectorABI = true;
43 bool SoftFloat = false;
44 if (CPU.empty() || CPU == "generic" ||
45 CPU == "z10" || CPU == "z196" || CPU == "zEC12" ||
46 CPU == "arch8" || CPU == "arch9" || CPU == "arch10")
49 SmallVector<StringRef, 3> Features;
50 FS.split(Features, ',', -1, false /* KeepEmpty */);
51 for (auto &Feature : Features) {
52 if (Feature == "vector" || Feature == "+vector")
54 if (Feature == "-vector")
56 if (Feature == "soft-float" || Feature == "+soft-float")
58 if (Feature == "-soft-float")
62 return VectorABI && !SoftFloat;
65 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
67 bool VectorABI = UsesVectorABI(CPU, FS);
74 Ret += DataLayout::getManglingComponent(TT);
76 // Make sure that global data has at least 16 bits of alignment by
77 // default, so that we can refer to it using LARL. We don't have any
78 // special requirements for stack variables though.
79 Ret += "-i1:8:16-i8:8:16";
81 // 64-bit integers are naturally aligned.
84 // 128-bit floats are aligned only to 64 bits.
87 // When using the vector ABI, 128-bit vectors are also aligned to 64 bits.
91 // We prefer 16 bits of aligned for all globals; see above.
94 // Integer registers are 32 or 64 bits.
100 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
101 // Static code is suitable for use in a dynamic executable; there is no
102 // separate DynamicNoPIC model.
103 if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
104 return Reloc::Static;
108 // For SystemZ we define the models as follows:
110 // Small: BRASL can call any function and will use a stub if necessary.
111 // Locally-binding symbols will always be in range of LARL.
113 // Medium: BRASL can call any function and will use a stub if necessary.
114 // GOT slots and locally-defined text will always be in range
115 // of LARL, but other symbols might not be.
117 // Large: Equivalent to Medium for now.
119 // Kernel: Equivalent to Medium for now.
121 // This means that any PIC module smaller than 4GB meets the
122 // requirements of Small, so Small seems like the best default there.
124 // All symbols bind locally in a non-PIC module, so the choice is less
125 // obvious. There are two cases:
127 // - When creating an executable, PLTs and copy relocations allow
128 // us to treat external symbols as part of the executable.
129 // Any executable smaller than 4GB meets the requirements of Small,
130 // so that seems like the best default.
132 // - When creating JIT code, stubs will be in range of BRASL if the
133 // image is less than 4GB in size. GOT entries will likewise be
134 // in range of LARL. However, the JIT environment has no equivalent
135 // of copy relocs, so locally-binding data symbols might not be in
136 // the range of LARL. We need the Medium model in that case.
137 static CodeModel::Model
138 getEffectiveSystemZCodeModel(Optional<CodeModel::Model> CM, Reloc::Model RM,
141 if (*CM == CodeModel::Tiny)
142 report_fatal_error("Target does not support the tiny CodeModel", false);
143 if (*CM == CodeModel::Kernel)
144 report_fatal_error("Target does not support the kernel CodeModel", false);
148 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
149 return CodeModel::Small;
152 SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
153 StringRef CPU, StringRef FS,
154 const TargetOptions &Options,
155 Optional<Reloc::Model> RM,
156 Optional<CodeModel::Model> CM,
157 CodeGenOpt::Level OL, bool JIT)
159 T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
160 getEffectiveRelocModel(RM),
161 getEffectiveSystemZCodeModel(CM, getEffectiveRelocModel(RM), JIT),
163 TLOF(std::make_unique<TargetLoweringObjectFileELF>()) {
167 SystemZTargetMachine::~SystemZTargetMachine() = default;
169 const SystemZSubtarget *
170 SystemZTargetMachine::getSubtargetImpl(const Function &F) const {
171 Attribute CPUAttr = F.getFnAttribute("target-cpu");
172 Attribute FSAttr = F.getFnAttribute("target-features");
174 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
175 ? CPUAttr.getValueAsString().str()
177 std::string FS = !FSAttr.hasAttribute(Attribute::None)
178 ? FSAttr.getValueAsString().str()
181 // FIXME: This is related to the code below to reset the target options,
182 // we need to know whether or not the soft float flag is set on the
183 // function, so we can enable it as a subtarget feature.
185 F.hasFnAttribute("use-soft-float") &&
186 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
189 FS += FS.empty() ? "+soft-float" : ",+soft-float";
191 auto &I = SubtargetMap[CPU + FS];
193 // This needs to be done before we create a new subtarget since any
194 // creation will depend on the TM and the code generation flags on the
195 // function that reside in TargetOptions.
196 resetTargetOptions(F);
197 I = std::make_unique<SystemZSubtarget>(TargetTriple, CPU, FS, *this);
205 /// SystemZ Code Generator Pass Configuration Options.
206 class SystemZPassConfig : public TargetPassConfig {
208 SystemZPassConfig(SystemZTargetMachine &TM, PassManagerBase &PM)
209 : TargetPassConfig(TM, PM) {}
211 SystemZTargetMachine &getSystemZTargetMachine() const {
212 return getTM<SystemZTargetMachine>();
216 createPostMachineScheduler(MachineSchedContext *C) const override {
217 return new ScheduleDAGMI(C,
218 std::make_unique<SystemZPostRASchedStrategy>(C),
219 /*RemoveKillFlags=*/true);
222 void addIRPasses() override;
223 bool addInstSelector() override;
224 bool addILPOpts() override;
225 void addPreRegAlloc() override;
226 void addPostRewrite() override;
227 void addPostRegAlloc() override;
228 void addPreSched2() override;
229 void addPreEmitPass() override;
232 } // end anonymous namespace
234 void SystemZPassConfig::addIRPasses() {
235 if (getOptLevel() != CodeGenOpt::None) {
236 addPass(createSystemZTDCPass());
237 addPass(createLoopDataPrefetchPass());
240 TargetPassConfig::addIRPasses();
243 bool SystemZPassConfig::addInstSelector() {
244 addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));
246 if (getOptLevel() != CodeGenOpt::None)
247 addPass(createSystemZLDCleanupPass(getSystemZTargetMachine()));
252 bool SystemZPassConfig::addILPOpts() {
253 addPass(&EarlyIfConverterID);
257 void SystemZPassConfig::addPreRegAlloc() {
258 addPass(createSystemZCopyPhysRegsPass(getSystemZTargetMachine()));
261 void SystemZPassConfig::addPostRewrite() {
262 addPass(createSystemZPostRewritePass(getSystemZTargetMachine()));
265 void SystemZPassConfig::addPostRegAlloc() {
266 // PostRewrite needs to be run at -O0 also (in which case addPostRewrite()
268 if (getOptLevel() == CodeGenOpt::None)
269 addPass(createSystemZPostRewritePass(getSystemZTargetMachine()));
272 void SystemZPassConfig::addPreSched2() {
273 if (getOptLevel() != CodeGenOpt::None)
274 addPass(&IfConverterID);
277 void SystemZPassConfig::addPreEmitPass() {
278 // Do instruction shortening before compare elimination because some
279 // vector instructions will be shortened into opcodes that compare
280 // elimination recognizes.
281 if (getOptLevel() != CodeGenOpt::None)
282 addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false);
284 // We eliminate comparisons here rather than earlier because some
285 // transformations can change the set of available CC values and we
286 // generally want those transformations to have priority. This is
287 // especially true in the commonest case where the result of the comparison
288 // is used by a single in-range branch instruction, since we will then
289 // be able to fuse the compare and the branch instead.
291 // For example, two-address NILF can sometimes be converted into
292 // three-address RISBLG. NILF produces a CC value that indicates whether
293 // the low word is zero, but RISBLG does not modify CC at all. On the
294 // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG.
295 // The CC value produced by NILL isn't useful for our purposes, but the
296 // value produced by RISBG can be used for any comparison with zero
297 // (not just equality). So there are some transformations that lose
298 // CC values (while still being worthwhile) and others that happen to make
299 // the CC result more useful than it was originally.
301 // Another reason is that we only want to use BRANCH ON COUNT in cases
302 // where we know that the count register is not going to be spilled.
304 // Doing it so late makes it more likely that a register will be reused
305 // between the comparison and the branch, but it isn't clear whether
306 // preventing that would be a win or not.
307 if (getOptLevel() != CodeGenOpt::None)
308 addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false);
309 addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
311 // Do final scheduling after all other optimizations, to get an
312 // optimal input for the decoder (branch relaxation must happen
313 // after block placement).
314 if (getOptLevel() != CodeGenOpt::None)
315 addPass(&PostMachineSchedulerID);
318 TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) {
319 return new SystemZPassConfig(*this, PM);
323 SystemZTargetMachine::getTargetTransformInfo(const Function &F) {
324 return TargetTransformInfo(SystemZTTIImpl(this, F));