1 //===-- VEInstrFormats.td - VE Instruction Formats ---------*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern>
19 dag OutOperandList = outs;
20 dag InOperandList = ins;
21 let AsmString = asmstr;
22 let Pattern = pattern;
24 let DecoderNamespace = "VE";
25 field bits<64> SoftFail = 0;
28 class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]>
29 : InstVE<outs, ins, asmstr, pattern> {
44 let Inst{63-32} = imm32;
47 class RR<bits<8>opVal, dag outs, dag ins, string asmstr>
48 : RM<opVal, outs, ins, asmstr> {
56 let imm32{28-31} = cfw;
59 class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]>
60 : RM<opVal, outs, ins, asmstr, pattern> {
70 // Pseudo instructions.
71 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern=[]>
72 : InstVE<outs, ins, asmstr, pattern> {
73 let isCodeGenOnly = 1;