1 //===-- VEInstrFormats.td - VE Instruction Formats ---------*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // SX-Aurora uses little endian, but instructions are encoded little bit
10 // different manner. Therefore, we need to tranlate the address of each
11 // bitfield described in ISA documentation like below.
13 // ISA | InstrFormats.td
14 // ---------------------------
19 //===----------------------------------------------------------------------===//
21 //===----------------------------------------------------------------------===//
23 class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern>
33 dag OutOperandList = outs;
34 dag InOperandList = ins;
35 let AsmString = asmstr;
36 let Pattern = pattern;
38 let DecoderNamespace = "VE";
39 field bits<64> SoftFail = 0;
42 //-----------------------------------------------------------------------------
43 // Section 5.1 RM Type
45 // RM type has sx, sy, sz, and imm32.
46 // The effective address is generated by sz + sy + imm32.
47 //-----------------------------------------------------------------------------
49 class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
50 : InstVE<outs, ins, asmstr, pattern> {
54 bits<7> sz; // defines sz prior to sy to assign from sz
65 let Inst{31-0} = imm32;
68 //-----------------------------------------------------------------------------
69 // Section 5.2 RRM Type
71 // RRM type is identical to RM, but the effective address is generated
72 // by sz + imm32. The sy field is used by other purposes.
73 //-----------------------------------------------------------------------------
75 class RRM<bits<8>opVal, dag outs, dag ins, string asmstr,
76 list<dag> pattern = []>
77 : RM<opVal, outs, ins, asmstr, pattern>;
79 // RRMHM type is to load/store host memory
80 // It is similar to RRM and not use sy.
81 class RRMHM<bits<8>opVal, dag outs, dag ins, string asmstr,
82 list<dag> pattern = []>
83 : RRM<opVal, outs, ins, asmstr, pattern> {
90 //-----------------------------------------------------------------------------
91 // Section 5.3 CF Type
93 // CF type is used for control flow.
94 //-----------------------------------------------------------------------------
96 class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
97 : InstVE<outs, ins, asmstr, pattern> {
110 let Inst{53-52} = bpf;
111 let Inst{51-48} = cf;
113 let Inst{46-40} = sy;
115 let Inst{38-32} = sz;
116 let Inst{31-0} = imm32;
119 //-----------------------------------------------------------------------------
120 // Section 5.4 RR Type
122 // RR type is for generic arithmetic instructions.
123 //-----------------------------------------------------------------------------
125 class RR<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
126 : InstVE<outs, ins, asmstr, pattern> {
132 bits<7> sz; // m field places at the top sz field
140 let Inst{54-48} = sx;
142 let Inst{46-40} = sy;
144 let Inst{38-32} = sz;
145 let Inst{31-24} = vx;
154 // RRFENCE type is special RR type for a FENCE instruction.
155 class RRFENCE<bits<8>opVal, dag outs, dag ins, string asmstr,
156 list<dag> pattern = []>
157 : InstVE<outs, ins, asmstr, pattern> {
176 //-----------------------------------------------------------------------------
177 // Section 5.5 RW Type
178 //-----------------------------------------------------------------------------
180 //-----------------------------------------------------------------------------
181 // Section 5.6 RVM Type
182 //-----------------------------------------------------------------------------
184 //-----------------------------------------------------------------------------
185 // Section 5.7 RV Type
186 //-----------------------------------------------------------------------------
188 // Pseudo instructions.
189 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = []>
190 : InstVE<outs, ins, asmstr, pattern> {
191 let isCodeGenOnly = 1;