contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssembly.td

   1 //- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 ///
   9 /// \file
  10 /// This is a target description file for the WebAssembly architecture,
  11 /// which is also known as "wasm".
  12 ///
  13 //===----------------------------------------------------------------------===//
  14
  15 //===----------------------------------------------------------------------===//
  16 // Target-independent interfaces which we are implementing
  17 //===----------------------------------------------------------------------===//
  18
  19 include "llvm/Target/Target.td"
  20
  21 //===----------------------------------------------------------------------===//
  22 // WebAssembly Subtarget features.
  23 //===----------------------------------------------------------------------===//
  24
  25 def FeatureSIMD128 : SubtargetFeature<"simd128", "SIMDLevel", "SIMD128",
  26                                       "Enable 128-bit SIMD">;
  27
  28 def FeatureUnimplementedSIMD128 :
  29       SubtargetFeature<"unimplemented-simd128",
  30                        "SIMDLevel", "UnimplementedSIMD128",
  31                        "Enable 128-bit SIMD not yet implemented in engines",
  32                        [FeatureSIMD128]>;
  33
  34 def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
  35                                       "Enable Atomics">;
  36
  37 def FeatureNontrappingFPToInt :
  38       SubtargetFeature<"nontrapping-fptoint",
  39                        "HasNontrappingFPToInt", "true",
  40                        "Enable non-trapping float-to-int conversion operators">;
  41
  42 def FeatureSignExt :
  43       SubtargetFeature<"sign-ext",
  44                        "HasSignExt", "true",
  45                        "Enable sign extension operators">;
  46
  47 def FeatureTailCall :
  48       SubtargetFeature<"tail-call",
  49                        "HasTailCall", "true",
  50                        "Enable tail call instructions">;
  51
  52 def FeatureExceptionHandling :
  53       SubtargetFeature<"exception-handling", "HasExceptionHandling", "true",
  54                        "Enable Wasm exception handling">;
  55
  56 def FeatureBulkMemory :
  57       SubtargetFeature<"bulk-memory", "HasBulkMemory", "true",
  58                        "Enable bulk memory operations">;
  59
  60 def FeatureMultivalue :
  61       SubtargetFeature<"multivalue",
  62                        "HasMultivalue", "true",
  63                        "Enable multivalue blocks, instructions, and functions">;
  64
  65 def FeatureMutableGlobals :
  66       SubtargetFeature<"mutable-globals", "HasMutableGlobals", "true",
  67                        "Enable mutable globals">;
  68
  69 //===----------------------------------------------------------------------===//
  70 // Architectures.
  71 //===----------------------------------------------------------------------===//
  72
  73 //===----------------------------------------------------------------------===//
  74 // Register File Description
  75 //===----------------------------------------------------------------------===//
  76
  77 include "WebAssemblyRegisterInfo.td"
  78
  79 //===----------------------------------------------------------------------===//
  80 // Instruction Descriptions
  81 //===----------------------------------------------------------------------===//
  82
  83 include "WebAssemblyInstrInfo.td"
  84
  85 def WebAssemblyInstrInfo : InstrInfo;
  86
  87 //===----------------------------------------------------------------------===//
  88 // WebAssembly Processors supported.
  89 //===----------------------------------------------------------------------===//
  90
  91 // Minimal Viable Product.
  92 def : ProcessorModel<"mvp", NoSchedModel, []>;
  93
  94 // Generic processor: latest stable version.
  95 def : ProcessorModel<"generic", NoSchedModel, []>;
  96
  97 // Latest and greatest experimental version of WebAssembly. Bugs included!
  98 def : ProcessorModel<"bleeding-edge", NoSchedModel,
  99                       [FeatureSIMD128, FeatureAtomics,
 100                        FeatureNontrappingFPToInt, FeatureSignExt,
 101                        FeatureMutableGlobals]>;
 102
 103 //===----------------------------------------------------------------------===//
 104 // Target Declaration
 105 //===----------------------------------------------------------------------===//
 106
 107 def WebAssemblyAsmParser : AsmParser {
 108   // The physical register names are not in the binary format or asm text
 109   let ShouldEmitMatchRegisterName = 0;
 110 }
 111
 112 def WebAssemblyAsmWriter : AsmWriter {
 113   string AsmWriterClassName  = "InstPrinter";
 114   int PassSubtarget = 0;
 115   int Variant = 0;
 116   bit isMCAsmWriter = 1;
 117 }
 118
 119 def WebAssembly : Target {
 120   let InstructionSet = WebAssemblyInstrInfo;
 121   let AssemblyParsers  = [WebAssemblyAsmParser];
 122   let AssemblyWriters = [WebAssemblyAsmWriter];
 123 }