1 //===-- X86InstrBuilder.h - Functions to aid building x86 insts -*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file exposes functions that may be used with BuildMI from the
10 // MachineInstrBuilder.h file to handle X86'isms in a clean way.
12 // The BuildMem function may be used with the BuildMI function to add entire
13 // memory references in a single, typed, function call. X86 memory references
14 // can be very complex expressions (described in the README), so wrapping them
15 // up behind an easier to use interface makes sense. Descriptions of the
16 // functions are included below.
18 // For reference, the order of operands for memory references is:
19 // (Operand), Base, Scale, Index, Displacement.
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H
24 #define LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/CodeGen/MachineOperand.h"
33 #include "llvm/MC/MCInstrDesc.h"
38 /// X86AddressMode - This struct holds a generalized full x86 address mode.
39 /// The base register can be a frame index, which will eventually be replaced
40 /// with BP or SP and Disp being offsetted accordingly. The displacement may
41 /// also include the offset of a global value.
42 struct X86AddressMode {
56 const GlobalValue *GV;
60 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
65 void getFullAddress(SmallVectorImpl<MachineOperand> &MO) {
66 assert(Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8);
68 if (BaseType == X86AddressMode::RegBase)
69 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false,
70 false, false, false, 0, false));
72 assert(BaseType == X86AddressMode::FrameIndexBase);
73 MO.push_back(MachineOperand::CreateFI(Base.FrameIndex));
76 MO.push_back(MachineOperand::CreateImm(Scale));
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false,
78 false, false, 0, false));
81 MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags));
83 MO.push_back(MachineOperand::CreateImm(Disp));
85 MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false,
90 /// Compute the addressing mode from an machine instruction starting with the
92 static inline X86AddressMode getAddressFromInstr(const MachineInstr *MI,
95 const MachineOperand &Op0 = MI->getOperand(Operand);
97 AM.BaseType = X86AddressMode::RegBase;
98 AM.Base.Reg = Op0.getReg();
100 AM.BaseType = X86AddressMode::FrameIndexBase;
101 AM.Base.FrameIndex = Op0.getIndex();
104 const MachineOperand &Op1 = MI->getOperand(Operand + 1);
105 AM.Scale = Op1.getImm();
107 const MachineOperand &Op2 = MI->getOperand(Operand + 2);
108 AM.IndexReg = Op2.getReg();
110 const MachineOperand &Op3 = MI->getOperand(Operand + 3);
112 AM.GV = Op3.getGlobal();
114 AM.Disp = Op3.getImm();
119 /// addDirectMem - This function is used to add a direct memory reference to the
120 /// current instruction -- that is, a dereference of an address in a register,
121 /// with no scale, index or displacement. An example is: DWORD PTR [EAX].
123 static inline const MachineInstrBuilder &
124 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
125 // Because memory references are always represented with five
126 // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction.
127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
130 /// Replace the address used in the instruction with the direct memory
132 static inline void setDirectAddressInInstr(MachineInstr *MI, unsigned Operand,
134 // Direct memory address is in a form of: Reg/FI, 1 (Scale), NoReg, 0, NoReg.
135 MI->getOperand(Operand).ChangeToRegister(Reg, /*isDef=*/false);
136 MI->getOperand(Operand + 1).setImm(1);
137 MI->getOperand(Operand + 2).setReg(0);
138 MI->getOperand(Operand + 3).ChangeToImmediate(0);
139 MI->getOperand(Operand + 4).setReg(0);
142 static inline const MachineInstrBuilder &
143 addOffset(const MachineInstrBuilder &MIB, int Offset) {
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
147 static inline const MachineInstrBuilder &
148 addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) {
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0);
152 /// addRegOffset - This function is used to add a memory reference of the form
153 /// [Reg + Offset], i.e., one with no scale or index, but with a
154 /// displacement. An example is: DWORD PTR [EAX + 4].
156 static inline const MachineInstrBuilder &
157 addRegOffset(const MachineInstrBuilder &MIB,
158 unsigned Reg, bool isKill, int Offset) {
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
162 /// addRegReg - This function is used to add a memory reference of the form:
164 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
165 unsigned Reg1, bool isKill1,
166 unsigned Reg2, bool isKill2) {
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
171 static inline const MachineInstrBuilder &
172 addFullAddress(const MachineInstrBuilder &MIB,
173 const X86AddressMode &AM) {
174 assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
176 if (AM.BaseType == X86AddressMode::RegBase)
177 MIB.addReg(AM.Base.Reg);
179 assert(AM.BaseType == X86AddressMode::FrameIndexBase);
180 MIB.addFrameIndex(AM.Base.FrameIndex);
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
185 MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
189 return MIB.addReg(0);
192 /// addFrameReference - This function is used to add a reference to the base of
193 /// an abstract object on the stack frame of the current function. This
194 /// reference has base register as the FrameIndex offset until it is resolved.
195 /// This allows a constant offset to be specified as well...
197 static inline const MachineInstrBuilder &
198 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
199 MachineInstr *MI = MIB;
200 MachineFunction &MF = *MI->getParent()->getParent();
201 MachineFrameInfo &MFI = MF.getFrameInfo();
202 const MCInstrDesc &MCID = MI->getDesc();
203 auto Flags = MachineMemOperand::MONone;
205 Flags |= MachineMemOperand::MOLoad;
207 Flags |= MachineMemOperand::MOStore;
208 MachineMemOperand *MMO = MF.getMachineMemOperand(
209 MachinePointerInfo::getFixedStack(MF, FI, Offset), Flags,
210 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
211 return addOffset(MIB.addFrameIndex(FI), Offset)
215 /// addConstantPoolReference - This function is used to add a reference to the
216 /// base of a constant value spilled to the per-function constant pool. The
217 /// reference uses the abstract ConstantPoolIndex which is retained until
218 /// either machine code emission or assembly output. In PIC mode on x86-32,
219 /// the GlobalBaseReg parameter can be used to make this a
220 /// GlobalBaseReg-relative reference.
222 static inline const MachineInstrBuilder &
223 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
224 unsigned GlobalBaseReg, unsigned char OpFlags) {
226 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
227 .addConstantPoolIndex(CPI, 0, OpFlags).addReg(0);
230 } // end namespace llvm
232 #endif // LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H