contrib/llvm-project/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td

   1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file provides pattern fragments useful for SIMD instructions.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // MMX specific DAG Nodes.
  15 //===----------------------------------------------------------------------===//
  16
  17 // Low word of MMX to GPR.
  18 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
  19                             [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
  20 // GPR to low word of MMX.
  21 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
  22                             [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
  23
  24 //===----------------------------------------------------------------------===//
  25 // MMX Pattern Fragments
  26 //===----------------------------------------------------------------------===//
  27
  28 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
  29
  30 //===----------------------------------------------------------------------===//
  31 // SSE specific DAG Nodes.
  32 //===----------------------------------------------------------------------===//
  33
  34 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>,
  35                                        SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
  36                                        SDTCisVT<3, i8>]>;
  37
  38 def X86fmin    : SDNode<"X86ISD::FMIN",      SDTFPBinOp>;
  39 def X86fmax    : SDNode<"X86ISD::FMAX",      SDTFPBinOp>;
  40 def X86fmins   : SDNode<"X86ISD::FMINS",     SDTFPBinOp>;
  41 def X86fmaxs   : SDNode<"X86ISD::FMAXS",     SDTFPBinOp>;
  42
  43 // Commutative and Associative FMIN and FMAX.
  44 def X86fminc    : SDNode<"X86ISD::FMINC", SDTFPBinOp,
  45     [SDNPCommutative, SDNPAssociative]>;
  46 def X86fmaxc    : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
  47     [SDNPCommutative, SDNPAssociative]>;
  48
  49 def X86fand    : SDNode<"X86ISD::FAND",      SDTFPBinOp,
  50                         [SDNPCommutative, SDNPAssociative]>;
  51 def X86for     : SDNode<"X86ISD::FOR",       SDTFPBinOp,
  52                         [SDNPCommutative, SDNPAssociative]>;
  53 def X86fxor    : SDNode<"X86ISD::FXOR",      SDTFPBinOp,
  54                         [SDNPCommutative, SDNPAssociative]>;
  55 def X86fandn   : SDNode<"X86ISD::FANDN",     SDTFPBinOp>;
  56 def X86frsqrt  : SDNode<"X86ISD::FRSQRT",    SDTFPUnaryOp>;
  57 def X86frcp    : SDNode<"X86ISD::FRCP",      SDTFPUnaryOp>;
  58 def X86fhadd   : SDNode<"X86ISD::FHADD",     SDTFPBinOp>;
  59 def X86fhsub   : SDNode<"X86ISD::FHSUB",     SDTFPBinOp>;
  60 def X86hadd    : SDNode<"X86ISD::HADD",      SDTIntBinOp>;
  61 def X86hsub    : SDNode<"X86ISD::HSUB",      SDTIntBinOp>;
  62 def X86comi    : SDNode<"X86ISD::COMI",      SDTX86FCmp>;
  63 def X86ucomi   : SDNode<"X86ISD::UCOMI",     SDTX86FCmp>;
  64
  65 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<0, 1>,
  66                                       SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
  67 def X86cmps    : SDNode<"X86ISD::FSETCC",    SDTX86Cmps>;
  68
  69 def X86pshufb  : SDNode<"X86ISD::PSHUFB",
  70                  SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>,
  71                                       SDTCisSameAs<0,2>]>>;
  72 def X86psadbw  : SDNode<"X86ISD::PSADBW",
  73                  SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
  74                                       SDTCVecEltisVT<1, i8>,
  75                                       SDTCisSameSizeAs<0,1>,
  76                                       SDTCisSameAs<1,2>]>, [SDNPCommutative]>;
  77 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
  78                   SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>,
  79                                        SDTCVecEltisVT<1, i8>,
  80                                        SDTCisSameSizeAs<0,1>,
  81                                        SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>>;
  82 def X86andnp   : SDNode<"X86ISD::ANDNP",
  83                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  84                                       SDTCisSameAs<0,2>]>>;
  85 def X86multishift   : SDNode<"X86ISD::MULTISHIFT",
  86                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
  87                                       SDTCisSameAs<1,2>]>>;
  88 def X86pextrb  : SDNode<"X86ISD::PEXTRB",
  89                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>,
  90                                       SDTCisPtrTy<2>]>>;
  91 def X86pextrw  : SDNode<"X86ISD::PEXTRW",
  92                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>,
  93                                       SDTCisPtrTy<2>]>>;
  94 def X86pinsrb  : SDNode<"X86ISD::PINSRB",
  95                  SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
  96                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
  97 def X86pinsrw  : SDNode<"X86ISD::PINSRW",
  98                  SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
  99                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
 100 def X86insertps : SDNode<"X86ISD::INSERTPS",
 101                  SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
 102                                       SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
 103 def X86vzmovl  : SDNode<"X86ISD::VZEXT_MOVL",
 104                  SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
 105
 106 def X86vzld  : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
 107                       [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 108 def X86vextractst  : SDNode<"X86ISD::VEXTRACT_STORE", SDTStore,
 109                      [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 110 def X86VBroadcastld  : SDNode<"X86ISD::VBROADCAST_LOAD", SDTLoad,
 111                       [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 112
 113 def SDTVtrunc    : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 114                                         SDTCisInt<0>, SDTCisInt<1>,
 115                                         SDTCisOpSmallerThanOp<0, 1>]>;
 116 def SDTVmtrunc   : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
 117                                         SDTCisInt<0>, SDTCisInt<1>,
 118                                         SDTCisOpSmallerThanOp<0, 1>,
 119                                         SDTCisSameAs<0, 2>,
 120                                         SDTCVecEltisVT<3, i1>,
 121                                         SDTCisSameNumEltsAs<1, 3>]>;
 122
 123 def X86vtrunc    : SDNode<"X86ISD::VTRUNC",   SDTVtrunc>;
 124 def X86vtruncs   : SDNode<"X86ISD::VTRUNCS",  SDTVtrunc>;
 125 def X86vtruncus  : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
 126 def X86vmtrunc   : SDNode<"X86ISD::VMTRUNC",   SDTVmtrunc>;
 127 def X86vmtruncs  : SDNode<"X86ISD::VMTRUNCS",  SDTVmtrunc>;
 128 def X86vmtruncus : SDNode<"X86ISD::VMTRUNCUS", SDTVmtrunc>;
 129
 130 def X86vfpext  : SDNode<"X86ISD::VFPEXT",
 131                         SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>,
 132                                              SDTCVecEltisVT<1, f32>,
 133                                              SDTCisSameSizeAs<0, 1>]>>;
 134
 135 def X86strict_vfpext  : SDNode<"X86ISD::STRICT_VFPEXT",
 136                                SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>,
 137                                                     SDTCVecEltisVT<1, f32>,
 138                                                     SDTCisSameSizeAs<0, 1>]>,
 139                                                     [SDNPHasChain]>;
 140
 141 def X86any_vfpext : PatFrags<(ops node:$src),
 142                               [(X86strict_vfpext node:$src),
 143                                (X86vfpext node:$src)]>;
 144
 145 def X86vfpround: SDNode<"X86ISD::VFPROUND",
 146                         SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
 147                                              SDTCVecEltisVT<1, f64>,
 148                                              SDTCisOpSmallerThanOp<0, 1>]>>;
 149
 150 def X86strict_vfpround: SDNode<"X86ISD::STRICT_VFPROUND",
 151                         SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
 152                                              SDTCVecEltisVT<1, f64>,
 153                                              SDTCisOpSmallerThanOp<0, 1>]>,
 154                                              [SDNPHasChain]>;
 155
 156 def X86any_vfpround : PatFrags<(ops node:$src),
 157                               [(X86strict_vfpround node:$src),
 158                                (X86vfpround node:$src)]>;
 159
 160 def X86frounds   : SDNode<"X86ISD::VFPROUNDS",
 161                            SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>,
 162                                                 SDTCisSameAs<0, 1>,
 163                                                 SDTCVecEltisVT<2, f64>,
 164                                                 SDTCisSameSizeAs<0, 2>]>>;
 165
 166 def X86froundsRnd: SDNode<"X86ISD::VFPROUNDS_RND",
 167                         SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>,
 168                                              SDTCisSameAs<0, 1>,
 169                                              SDTCVecEltisVT<2, f64>,
 170                                              SDTCisSameSizeAs<0, 2>,
 171                                              SDTCisVT<3, i32>]>>;
 172
 173 def X86fpexts     : SDNode<"X86ISD::VFPEXTS",
 174                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>,
 175                                              SDTCisSameAs<0, 1>,
 176                                              SDTCVecEltisVT<2, f32>,
 177                                              SDTCisSameSizeAs<0, 2>]>>;
 178 def X86fpextsSAE  : SDNode<"X86ISD::VFPEXTS_SAE",
 179                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>,
 180                                              SDTCisSameAs<0, 1>,
 181                                              SDTCVecEltisVT<2, f32>,
 182                                              SDTCisSameSizeAs<0, 2>]>>;
 183
 184 def X86vmfpround: SDNode<"X86ISD::VMFPROUND",
 185                          SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>,
 186                                               SDTCVecEltisVT<1, f64>,
 187                                               SDTCisSameSizeAs<0, 1>,
 188                                               SDTCisSameAs<0, 2>,
 189                                               SDTCVecEltisVT<3, i1>,
 190                                               SDTCisSameNumEltsAs<1, 3>]>>;
 191
 192 def X86vshiftimm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 193                                         SDTCisVT<2, i8>, SDTCisInt<0>]>;
 194
 195 def X86vshldq  : SDNode<"X86ISD::VSHLDQ",    X86vshiftimm>;
 196 def X86vshrdq  : SDNode<"X86ISD::VSRLDQ",    X86vshiftimm>;
 197 def X86pcmpeq  : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
 198 def X86pcmpgt  : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
 199
 200 def X86cmpp    : SDNode<"X86ISD::CMPP",      SDTX86VFCMP>;
 201 def X86strict_cmpp : SDNode<"X86ISD::STRICT_CMPP", SDTX86VFCMP, [SDNPHasChain]>;
 202 def X86any_cmpp    : PatFrags<(ops node:$src1, node:$src2, node:$src3),
 203                                [(X86strict_cmpp node:$src1, node:$src2, node:$src3),
 204                                 (X86cmpp node:$src1, node:$src2, node:$src3)]>;
 205
 206 def X86CmpMaskCC :
 207       SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
 208                        SDTCisVec<1>, SDTCisSameAs<2, 1>,
 209                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
 210 def X86CmpMaskCCScalar :
 211       SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>,
 212                            SDTCisVT<3, i8>]>;
 213
 214 def X86cmpm     : SDNode<"X86ISD::CMPM",     X86CmpMaskCC>;
 215 def X86strict_cmpm : SDNode<"X86ISD::STRICT_CMPM", X86CmpMaskCC, [SDNPHasChain]>;
 216 def X86any_cmpm    : PatFrags<(ops node:$src1, node:$src2, node:$src3),
 217                                [(X86strict_cmpm node:$src1, node:$src2, node:$src3),
 218                                 (X86cmpm node:$src1, node:$src2, node:$src3)]>;
 219 def X86cmpmSAE  : SDNode<"X86ISD::CMPM_SAE", X86CmpMaskCC>;
 220 def X86cmpms    : SDNode<"X86ISD::FSETCCM",   X86CmpMaskCCScalar>;
 221 def X86cmpmsSAE : SDNode<"X86ISD::FSETCCM_SAE",   X86CmpMaskCCScalar>;
 222
 223 def X86phminpos: SDNode<"X86ISD::PHMINPOS",
 224                  SDTypeProfile<1, 1, [SDTCisVT<0, v8i16>, SDTCisVT<1, v8i16>]>>;
 225
 226 def X86vshiftuniform : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 227                                             SDTCisVec<2>, SDTCisInt<0>,
 228                                             SDTCisInt<2>]>;
 229
 230 def X86vshl    : SDNode<"X86ISD::VSHL", X86vshiftuniform>;
 231 def X86vsrl    : SDNode<"X86ISD::VSRL", X86vshiftuniform>;
 232 def X86vsra    : SDNode<"X86ISD::VSRA", X86vshiftuniform>;
 233
 234 def X86vshiftvariable : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 235                                              SDTCisSameAs<0,2>, SDTCisInt<0>]>;
 236
 237 def X86vshlv   : SDNode<"X86ISD::VSHLV", X86vshiftvariable>;
 238 def X86vsrlv   : SDNode<"X86ISD::VSRLV", X86vshiftvariable>;
 239 def X86vsrav   : SDNode<"X86ISD::VSRAV", X86vshiftvariable>;
 240
 241 def X86vshli   : SDNode<"X86ISD::VSHLI", X86vshiftimm>;
 242 def X86vsrli   : SDNode<"X86ISD::VSRLI", X86vshiftimm>;
 243 def X86vsrai   : SDNode<"X86ISD::VSRAI", X86vshiftimm>;
 244
 245 def X86kshiftl : SDNode<"X86ISD::KSHIFTL",
 246                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
 247                                              SDTCisSameAs<0, 1>,
 248                                              SDTCisVT<2, i8>]>>;
 249 def X86kshiftr : SDNode<"X86ISD::KSHIFTR",
 250                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
 251                                              SDTCisSameAs<0, 1>,
 252                                              SDTCisVT<2, i8>]>>;
 253
 254 def X86kadd : SDNode<"X86ISD::KADD", SDTIntBinOp, [SDNPCommutative]>;
 255
 256 def X86vrotli  : SDNode<"X86ISD::VROTLI", X86vshiftimm>;
 257 def X86vrotri  : SDNode<"X86ISD::VROTRI", X86vshiftimm>;
 258
 259 def X86vpshl   : SDNode<"X86ISD::VPSHL", X86vshiftvariable>;
 260 def X86vpsha   : SDNode<"X86ISD::VPSHA", X86vshiftvariable>;
 261
 262 def X86vpcom   : SDNode<"X86ISD::VPCOM",
 263                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 264                                              SDTCisSameAs<0,2>,
 265                                              SDTCisVT<3, i8>, SDTCisInt<0>]>>;
 266 def X86vpcomu  : SDNode<"X86ISD::VPCOMU",
 267                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 268                                              SDTCisSameAs<0,2>,
 269                                              SDTCisVT<3, i8>, SDTCisInt<0>]>>;
 270 def X86vpermil2 : SDNode<"X86ISD::VPERMIL2",
 271                         SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 272                                              SDTCisSameAs<0,2>,
 273                                              SDTCisFP<0>, SDTCisInt<3>,
 274                                              SDTCisSameNumEltsAs<0, 3>,
 275                                              SDTCisSameSizeAs<0,3>,
 276                                              SDTCisVT<4, i8>]>>;
 277 def X86vpperm : SDNode<"X86ISD::VPPERM",
 278                         SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
 279                                              SDTCisSameAs<0,2>, SDTCisSameAs<0, 3>]>>;
 280
 281 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
 282                                           SDTCisVec<1>,
 283                                           SDTCisSameAs<2, 1>]>;
 284
 285 def X86mulhrs  : SDNode<"X86ISD::MULHRS", SDTIntBinOp, [SDNPCommutative]>;
 286 def X86avg     : SDNode<"X86ISD::AVG" , SDTIntBinOp, [SDNPCommutative]>;
 287 def X86ptest   : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
 288 def X86testp   : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
 289 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
 290 def X86ktest   : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
 291
 292 def X86movmsk : SDNode<"X86ISD::MOVMSK",
 293                         SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>>;
 294
 295 def X86selects : SDNode<"X86ISD::SELECTS",
 296                         SDTypeProfile<1, 3, [SDTCisVT<1, v1i1>,
 297                                              SDTCisSameAs<0, 2>,
 298                                              SDTCisSameAs<2, 3>]>>;
 299
 300 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
 301                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
 302                                              SDTCisSameAs<0,1>,
 303                                              SDTCisSameAs<1,2>]>,
 304                                              [SDNPCommutative]>;
 305 def X86pmuldq  : SDNode<"X86ISD::PMULDQ",
 306                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
 307                                              SDTCisSameAs<0,1>,
 308                                              SDTCisSameAs<1,2>]>,
 309                                              [SDNPCommutative]>;
 310
 311 def X86extrqi : SDNode<"X86ISD::EXTRQI",
 312                   SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 313                                        SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
 314 def X86insertqi : SDNode<"X86ISD::INSERTQI",
 315                     SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 316                                          SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
 317                                          SDTCisVT<4, i8>]>>;
 318
 319 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
 320 // translated into one of the target nodes below during lowering.
 321 // Note: this is a work in progress...
 322 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
 323 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 324                                 SDTCisSameAs<0,2>]>;
 325 def SDTShuff2OpFP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>,
 326                                          SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>;
 327
 328 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 329                                         SDTCisFP<0>, SDTCisInt<2>,
 330                                         SDTCisSameNumEltsAs<0,2>,
 331                                         SDTCisSameSizeAs<0,2>]>;
 332 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
 333                                  SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>;
 334 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 335                                  SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>;
 336 def SDTFPBinOpImm: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>,
 337                                         SDTCisSameAs<0,1>,
 338                                         SDTCisSameAs<0,2>,
 339                                         SDTCisVT<3, i32>]>;
 340 def SDTFPTernaryOpImm: SDTypeProfile<1, 4, [SDTCisFP<0>, SDTCisSameAs<0,1>,
 341                                             SDTCisSameAs<0,2>,
 342                                             SDTCisInt<3>,
 343                                             SDTCisSameSizeAs<0, 3>,
 344                                             SDTCisSameNumEltsAs<0, 3>,
 345                                             SDTCisVT<4, i32>]>;
 346 def SDTFPUnaryOpImm: SDTypeProfile<1, 2, [SDTCisFP<0>,
 347                                           SDTCisSameAs<0,1>,
 348                                           SDTCisVT<2, i32>]>;
 349
 350 def SDTVBroadcast  : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
 351 def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>,
 352                                           SDTCisInt<0>, SDTCisInt<1>]>;
 353
 354 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 355                              SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
 356
 357 def SDTTernlog  : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisVec<0>,
 358                                        SDTCisSameAs<0,1>, SDTCisSameAs<0,2>,
 359                                        SDTCisSameAs<0,3>, SDTCisVT<4, i8>]>;
 360
 361 def SDTFPBinOpRound : SDTypeProfile<1, 3, [      // fadd_round, fmul_round, etc.
 362   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisVT<3, i32>]>;
 363
 364 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [      // fsqrt_round, fgetexp_round, etc.
 365   SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisVT<2, i32>]>;
 366
 367 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
 368                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>,
 369                            SDTCisFP<0>, SDTCisVT<4, i32>]>;
 370
 371 def X86PAlignr : SDNode<"X86ISD::PALIGNR",
 372                         SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i8>,
 373                                              SDTCisSameAs<0,1>,
 374                                              SDTCisSameAs<0,2>,
 375                                              SDTCisVT<3, i8>]>>;
 376 def X86VAlign  : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
 377
 378 def X86VShld   : SDNode<"X86ISD::VSHLD", SDTShuff3OpI>;
 379 def X86VShrd   : SDNode<"X86ISD::VSHRD", SDTShuff3OpI>;
 380 def X86VShldv  : SDNode<"X86ISD::VSHLDV",
 381                         SDTypeProfile<1, 3, [SDTCisVec<0>,
 382                                              SDTCisSameAs<0,1>,
 383                                              SDTCisSameAs<0,2>,
 384                                              SDTCisSameAs<0,3>]>>;
 385 def X86VShrdv  : SDNode<"X86ISD::VSHRDV",
 386                         SDTypeProfile<1, 3, [SDTCisVec<0>,
 387                                              SDTCisSameAs<0,1>,
 388                                              SDTCisSameAs<0,2>,
 389                                              SDTCisSameAs<0,3>]>>;
 390
 391 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
 392
 393 def X86PShufd  : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
 394 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
 395 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
 396
 397 def X86Shufp   : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
 398 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
 399
 400 def X86Movddup  : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
 401 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
 402 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
 403
 404 def X86Movsd : SDNode<"X86ISD::MOVSD",
 405                       SDTypeProfile<1, 2, [SDTCisVT<0, v2f64>,
 406                                            SDTCisVT<1, v2f64>,
 407                                            SDTCisVT<2, v2f64>]>>;
 408 def X86Movss : SDNode<"X86ISD::MOVSS",
 409                       SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>,
 410                                            SDTCisVT<1, v4f32>,
 411                                            SDTCisVT<2, v4f32>]>>;
 412
 413 def X86Movlhps : SDNode<"X86ISD::MOVLHPS",
 414                         SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>,
 415                                              SDTCisVT<1, v4f32>,
 416                                              SDTCisVT<2, v4f32>]>>;
 417 def X86Movhlps : SDNode<"X86ISD::MOVHLPS",
 418                         SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>,
 419                                              SDTCisVT<1, v4f32>,
 420                                              SDTCisVT<2, v4f32>]>>;
 421
 422 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>,
 423                                    SDTCisVec<1>, SDTCisInt<1>,
 424                                    SDTCisSameSizeAs<0,1>,
 425                                    SDTCisSameAs<1,2>,
 426                                    SDTCisOpSmallerThanOp<0, 1>]>;
 427 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
 428 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
 429
 430 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
 431 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
 432
 433 def X86vpmaddubsw  : SDNode<"X86ISD::VPMADDUBSW",
 434                             SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>,
 435                                                  SDTCVecEltisVT<1, i8>,
 436                                                  SDTCisSameSizeAs<0,1>,
 437                                                  SDTCisSameAs<1,2>]>>;
 438 def X86vpmaddwd    : SDNode<"X86ISD::VPMADDWD",
 439                             SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i32>,
 440                                                  SDTCVecEltisVT<1, i16>,
 441                                                  SDTCisSameSizeAs<0,1>,
 442                                                  SDTCisSameAs<1,2>]>,
 443                             [SDNPCommutative]>;
 444
 445 def X86VPermilpv  : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
 446 def X86VPermilpi  : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
 447 def X86VPermv     : SDNode<"X86ISD::VPERMV",
 448                            SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<1>,
 449                                                 SDTCisSameNumEltsAs<0,1>,
 450                                                 SDTCisSameSizeAs<0,1>,
 451                                                 SDTCisSameAs<0,2>]>>;
 452 def X86VPermi     : SDNode<"X86ISD::VPERMI",    SDTShuff2OpI>;
 453 def X86VPermt2     : SDNode<"X86ISD::VPERMV3",
 454                     SDTypeProfile<1, 3, [SDTCisVec<0>,
 455                                          SDTCisSameAs<0,1>, SDTCisInt<2>,
 456                                          SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>,
 457                                          SDTCisSameSizeAs<0,2>,
 458                                          SDTCisSameAs<0,3>]>, []>;
 459
 460 def X86vpternlog  : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>;
 461
 462 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
 463
 464 def X86VFixupimm     : SDNode<"X86ISD::VFIXUPIMM", SDTFPTernaryOpImm>;
 465 def X86VFixupimmSAE  : SDNode<"X86ISD::VFIXUPIMM_SAE", SDTFPTernaryOpImm>;
 466 def X86VFixupimms    : SDNode<"X86ISD::VFIXUPIMMS", SDTFPTernaryOpImm>;
 467 def X86VFixupimmSAEs : SDNode<"X86ISD::VFIXUPIMMS_SAE", SDTFPTernaryOpImm>;
 468 def X86VRange      : SDNode<"X86ISD::VRANGE",        SDTFPBinOpImm>;
 469 def X86VRangeSAE   : SDNode<"X86ISD::VRANGE_SAE",    SDTFPBinOpImm>;
 470 def X86VReduce     : SDNode<"X86ISD::VREDUCE",       SDTFPUnaryOpImm>;
 471 def X86VReduceSAE  : SDNode<"X86ISD::VREDUCE_SAE",   SDTFPUnaryOpImm>;
 472 def X86VRndScale   : SDNode<"X86ISD::VRNDSCALE",     SDTFPUnaryOpImm>;
 473 def X86strict_VRndScale : SDNode<"X86ISD::STRICT_VRNDSCALE", SDTFPUnaryOpImm,
 474                                   [SDNPHasChain]>;
 475 def X86any_VRndScale    : PatFrags<(ops node:$src1, node:$src2),
 476                                     [(X86strict_VRndScale node:$src1, node:$src2),
 477                                     (X86VRndScale node:$src1, node:$src2)]>;
 478
 479 def X86VRndScaleSAE: SDNode<"X86ISD::VRNDSCALE_SAE", SDTFPUnaryOpImm>;
 480 def X86VGetMant    : SDNode<"X86ISD::VGETMANT",      SDTFPUnaryOpImm>;
 481 def X86VGetMantSAE : SDNode<"X86ISD::VGETMANT_SAE",  SDTFPUnaryOpImm>;
 482 def X86Vfpclass    : SDNode<"X86ISD::VFPCLASS",
 483                        SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
 484                                             SDTCisFP<1>,
 485                                             SDTCisSameNumEltsAs<0,1>,
 486                                             SDTCisVT<2, i32>]>, []>;
 487 def X86Vfpclasss   : SDNode<"X86ISD::VFPCLASSS",
 488                        SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>,
 489                                             SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>;
 490
 491 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
 492                     SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 493                                          SDTCisSubVecOfVec<1, 0>]>, []>;
 494
 495 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
 496 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
 497
 498 def X86Blendi    : SDNode<"X86ISD::BLENDI",   SDTBlend>;
 499 def X86Blendv    : SDNode<"X86ISD::BLENDV",
 500                      SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<1>,
 501                                           SDTCisSameAs<0, 2>,
 502                                           SDTCisSameAs<2, 3>,
 503                                           SDTCisSameNumEltsAs<0, 1>,
 504                                           SDTCisSameSizeAs<0, 1>]>>;
 505
 506 def X86Addsub    : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
 507
 508 def X86faddRnd   : SDNode<"X86ISD::FADD_RND",  SDTFPBinOpRound>;
 509 def X86fadds     : SDNode<"X86ISD::FADDS",     SDTFPBinOp>;
 510 def X86faddRnds  : SDNode<"X86ISD::FADDS_RND", SDTFPBinOpRound>;
 511 def X86fsubRnd   : SDNode<"X86ISD::FSUB_RND",  SDTFPBinOpRound>;
 512 def X86fsubs     : SDNode<"X86ISD::FSUBS",     SDTFPBinOp>;
 513 def X86fsubRnds  : SDNode<"X86ISD::FSUBS_RND", SDTFPBinOpRound>;
 514 def X86fmulRnd   : SDNode<"X86ISD::FMUL_RND",  SDTFPBinOpRound>;
 515 def X86fmuls     : SDNode<"X86ISD::FMULS",     SDTFPBinOp>;
 516 def X86fmulRnds  : SDNode<"X86ISD::FMULS_RND", SDTFPBinOpRound>;
 517 def X86fdivRnd   : SDNode<"X86ISD::FDIV_RND",  SDTFPBinOpRound>;
 518 def X86fdivs     : SDNode<"X86ISD::FDIVS",     SDTFPBinOp>;
 519 def X86fdivRnds  : SDNode<"X86ISD::FDIVS_RND", SDTFPBinOpRound>;
 520 def X86fmaxSAE   : SDNode<"X86ISD::FMAX_SAE",  SDTFPBinOp>;
 521 def X86fmaxSAEs  : SDNode<"X86ISD::FMAXS_SAE", SDTFPBinOp>;
 522 def X86fminSAE   : SDNode<"X86ISD::FMIN_SAE",  SDTFPBinOp>;
 523 def X86fminSAEs  : SDNode<"X86ISD::FMINS_SAE", SDTFPBinOp>;
 524 def X86scalef    : SDNode<"X86ISD::SCALEF",         SDTFPBinOp>;
 525 def X86scalefRnd : SDNode<"X86ISD::SCALEF_RND",     SDTFPBinOpRound>;
 526 def X86scalefs   : SDNode<"X86ISD::SCALEFS",        SDTFPBinOp>;
 527 def X86scalefsRnd: SDNode<"X86ISD::SCALEFS_RND",    SDTFPBinOpRound>;
 528 def X86fsqrtRnd     : SDNode<"X86ISD::FSQRT_RND",   SDTFPUnaryOpRound>;
 529 def X86fsqrts       : SDNode<"X86ISD::FSQRTS", SDTFPBinOp>;
 530 def X86fsqrtRnds    : SDNode<"X86ISD::FSQRTS_RND", SDTFPBinOpRound>;
 531 def X86fgetexp      : SDNode<"X86ISD::FGETEXP", SDTFPUnaryOp>;
 532 def X86fgetexpSAE   : SDNode<"X86ISD::FGETEXP_SAE", SDTFPUnaryOp>;
 533 def X86fgetexps     : SDNode<"X86ISD::FGETEXPS", SDTFPBinOp>;
 534 def X86fgetexpSAEs  : SDNode<"X86ISD::FGETEXPS_SAE", SDTFPBinOp>;
 535
 536 def X86Fmadd        : SDNode<"ISD::FMA",          SDTFPTernaryOp, [SDNPCommutative]>;
 537 def X86strict_Fmadd : SDNode<"ISD::STRICT_FMA",   SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>;
 538 def X86any_Fmadd    : PatFrags<(ops node:$src1, node:$src2, node:$src3),
 539                                [(X86strict_Fmadd node:$src1, node:$src2, node:$src3),
 540                                 (X86Fmadd node:$src1, node:$src2, node:$src3)]>;
 541 def X86Fnmadd    : SDNode<"X86ISD::FNMADD",    SDTFPTernaryOp, [SDNPCommutative]>;
 542 def X86strict_Fnmadd : SDNode<"X86ISD::STRICT_FNMADD", SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>;
 543 def X86any_Fnmadd : PatFrags<(ops node:$src1, node:$src2, node:$src3),
 544                              [(X86strict_Fnmadd node:$src1, node:$src2, node:$src3),
 545                               (X86Fnmadd node:$src1, node:$src2, node:$src3)]>;
 546 def X86Fmsub     : SDNode<"X86ISD::FMSUB",     SDTFPTernaryOp, [SDNPCommutative]>;
 547 def X86strict_Fmsub : SDNode<"X86ISD::STRICT_FMSUB",     SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>;
 548 def X86any_Fmsub : PatFrags<(ops node:$src1, node:$src2, node:$src3),
 549                             [(X86strict_Fmsub node:$src1, node:$src2, node:$src3),
 550                              (X86Fmsub node:$src1, node:$src2, node:$src3)]>;
 551 def X86Fnmsub    : SDNode<"X86ISD::FNMSUB",    SDTFPTernaryOp, [SDNPCommutative]>;
 552 def X86strict_Fnmsub : SDNode<"X86ISD::STRICT_FNMSUB",    SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>;
 553 def X86any_Fnmsub : PatFrags<(ops node:$src1, node:$src2, node:$src3),
 554                              [(X86strict_Fnmsub node:$src1, node:$src2, node:$src3),
 555                               (X86Fnmsub node:$src1, node:$src2, node:$src3)]>;
 556 def X86Fmaddsub  : SDNode<"X86ISD::FMADDSUB",  SDTFPTernaryOp, [SDNPCommutative]>;
 557 def X86Fmsubadd  : SDNode<"X86ISD::FMSUBADD",  SDTFPTernaryOp, [SDNPCommutative]>;
 558
 559 def X86FmaddRnd     : SDNode<"X86ISD::FMADD_RND",     SDTFmaRound, [SDNPCommutative]>;
 560 def X86FnmaddRnd    : SDNode<"X86ISD::FNMADD_RND",    SDTFmaRound, [SDNPCommutative]>;
 561 def X86FmsubRnd     : SDNode<"X86ISD::FMSUB_RND",     SDTFmaRound, [SDNPCommutative]>;
 562 def X86FnmsubRnd    : SDNode<"X86ISD::FNMSUB_RND",    SDTFmaRound, [SDNPCommutative]>;
 563 def X86FmaddsubRnd  : SDNode<"X86ISD::FMADDSUB_RND",  SDTFmaRound, [SDNPCommutative]>;
 564 def X86FmsubaddRnd  : SDNode<"X86ISD::FMSUBADD_RND",  SDTFmaRound, [SDNPCommutative]>;
 565
 566 def X86vp2intersect : SDNode<"X86ISD::VP2INTERSECT",
 567                               SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
 568                                                    SDTCisVec<1>, SDTCisSameAs<1, 2>]>>;
 569
 570 def SDTIFma : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0,1>,
 571                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
 572 def x86vpmadd52l     : SDNode<"X86ISD::VPMADD52L",     SDTIFma, [SDNPCommutative]>;
 573 def x86vpmadd52h     : SDNode<"X86ISD::VPMADD52H",     SDTIFma, [SDNPCommutative]>;
 574
 575 def X86rsqrt14   : SDNode<"X86ISD::RSQRT14",  SDTFPUnaryOp>;
 576 def X86rcp14     : SDNode<"X86ISD::RCP14",    SDTFPUnaryOp>;
 577
 578 // VNNI
 579 def SDTVnni : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 580                                    SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
 581 def X86Vpdpbusd  : SDNode<"X86ISD::VPDPBUSD", SDTVnni>;
 582 def X86Vpdpbusds : SDNode<"X86ISD::VPDPBUSDS", SDTVnni>;
 583 def X86Vpdpwssd  : SDNode<"X86ISD::VPDPWSSD", SDTVnni>;
 584 def X86Vpdpwssds : SDNode<"X86ISD::VPDPWSSDS", SDTVnni>;
 585
 586 def X86rsqrt28   : SDNode<"X86ISD::RSQRT28",     SDTFPUnaryOp>;
 587 def X86rsqrt28SAE: SDNode<"X86ISD::RSQRT28_SAE", SDTFPUnaryOp>;
 588 def X86rcp28     : SDNode<"X86ISD::RCP28",       SDTFPUnaryOp>;
 589 def X86rcp28SAE  : SDNode<"X86ISD::RCP28_SAE",   SDTFPUnaryOp>;
 590 def X86exp2      : SDNode<"X86ISD::EXP2",        SDTFPUnaryOp>;
 591 def X86exp2SAE   : SDNode<"X86ISD::EXP2_SAE",    SDTFPUnaryOp>;
 592
 593 def X86rsqrt14s  : SDNode<"X86ISD::RSQRT14S",   SDTFPBinOp>;
 594 def X86rcp14s    : SDNode<"X86ISD::RCP14S",     SDTFPBinOp>;
 595 def X86rsqrt28s  : SDNode<"X86ISD::RSQRT28S",   SDTFPBinOp>;
 596 def X86rsqrt28SAEs : SDNode<"X86ISD::RSQRT28S_SAE", SDTFPBinOp>;
 597 def X86rcp28s    : SDNode<"X86ISD::RCP28S",     SDTFPBinOp>;
 598 def X86rcp28SAEs : SDNode<"X86ISD::RCP28S_SAE", SDTFPBinOp>;
 599 def X86Ranges    : SDNode<"X86ISD::VRANGES",    SDTFPBinOpImm>;
 600 def X86RndScales : SDNode<"X86ISD::VRNDSCALES", SDTFPBinOpImm>;
 601 def X86Reduces   : SDNode<"X86ISD::VREDUCES",   SDTFPBinOpImm>;
 602 def X86GetMants  : SDNode<"X86ISD::VGETMANTS",  SDTFPBinOpImm>;
 603 def X86RangesSAE    : SDNode<"X86ISD::VRANGES_SAE",    SDTFPBinOpImm>;
 604 def X86RndScalesSAE : SDNode<"X86ISD::VRNDSCALES_SAE", SDTFPBinOpImm>;
 605 def X86ReducesSAE   : SDNode<"X86ISD::VREDUCES_SAE",   SDTFPBinOpImm>;
 606 def X86GetMantsSAE  : SDNode<"X86ISD::VGETMANTS_SAE",  SDTFPBinOpImm>;
 607
 608 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 3,
 609                               [SDTCisSameAs<0, 1>, SDTCisVec<1>,
 610                                SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>,
 611                                SDTCisSameNumEltsAs<0, 3>]>, []>;
 612 def X86expand  : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 3,
 613                               [SDTCisSameAs<0, 1>, SDTCisVec<1>,
 614                                SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>,
 615                                SDTCisSameNumEltsAs<0, 3>]>, []>;
 616
 617 // vpshufbitqmb
 618 def X86Vpshufbitqmb : SDNode<"X86ISD::VPSHUFBITQMB",
 619                              SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 620                                                   SDTCisSameAs<1,2>,
 621                                                   SDTCVecEltisVT<0,i1>,
 622                                                   SDTCisSameNumEltsAs<0,1>]>>;
 623
 624 def SDTintToFP: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>,
 625                                      SDTCisSameAs<0,1>, SDTCisInt<2>]>;
 626 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
 627                                           SDTCisSameAs<0,1>, SDTCisInt<2>,
 628                                           SDTCisVT<3, i32>]>;
 629
 630 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 631                                         SDTCisInt<0>, SDTCisFP<1>]>;
 632 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 633                                            SDTCisInt<0>, SDTCisFP<1>,
 634                                            SDTCisVT<2, i32>]>;
 635 def SDTSFloatToInt: SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisFP<1>,
 636                                          SDTCisVec<1>]>;
 637 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
 638                                             SDTCisVec<1>, SDTCisVT<2, i32>]>;
 639
 640 def SDTVintToFP: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 641                                       SDTCisFP<0>, SDTCisInt<1>]>;
 642 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 643                                            SDTCisFP<0>, SDTCisInt<1>,
 644                                            SDTCisVT<2, i32>]>;
 645
 646 // Scalar
 647 def X86SintToFp     : SDNode<"X86ISD::SCALAR_SINT_TO_FP",      SDTintToFP>;
 648 def X86SintToFpRnd  : SDNode<"X86ISD::SCALAR_SINT_TO_FP_RND",  SDTintToFPRound>;
 649 def X86UintToFp     : SDNode<"X86ISD::SCALAR_UINT_TO_FP",      SDTintToFP>;
 650 def X86UintToFpRnd  : SDNode<"X86ISD::SCALAR_UINT_TO_FP_RND",  SDTintToFPRound>;
 651
 652 def X86cvtts2Int  : SDNode<"X86ISD::CVTTS2SI",  SDTSFloatToInt>;
 653 def X86cvtts2UInt : SDNode<"X86ISD::CVTTS2UI",  SDTSFloatToInt>;
 654 def X86cvtts2IntSAE  : SDNode<"X86ISD::CVTTS2SI_SAE",  SDTSFloatToInt>;
 655 def X86cvtts2UIntSAE : SDNode<"X86ISD::CVTTS2UI_SAE",  SDTSFloatToInt>;
 656
 657 def X86cvts2si  : SDNode<"X86ISD::CVTS2SI", SDTSFloatToInt>;
 658 def X86cvts2usi : SDNode<"X86ISD::CVTS2UI", SDTSFloatToInt>;
 659 def X86cvts2siRnd  : SDNode<"X86ISD::CVTS2SI_RND", SDTSFloatToIntRnd>;
 660 def X86cvts2usiRnd : SDNode<"X86ISD::CVTS2UI_RND", SDTSFloatToIntRnd>;
 661
 662 // Vector with rounding mode
 663
 664 // cvtt fp-to-int staff
 665 def X86cvttp2siSAE    : SDNode<"X86ISD::CVTTP2SI_SAE", SDTFloatToInt>;
 666 def X86cvttp2uiSAE    : SDNode<"X86ISD::CVTTP2UI_SAE", SDTFloatToInt>;
 667
 668 def X86VSintToFpRnd   : SDNode<"X86ISD::SINT_TO_FP_RND",  SDTVintToFPRound>;
 669 def X86VUintToFpRnd   : SDNode<"X86ISD::UINT_TO_FP_RND",  SDTVintToFPRound>;
 670
 671 // cvt fp-to-int staff
 672 def X86cvtp2IntRnd      : SDNode<"X86ISD::CVTP2SI_RND",  SDTFloatToIntRnd>;
 673 def X86cvtp2UIntRnd     : SDNode<"X86ISD::CVTP2UI_RND",  SDTFloatToIntRnd>;
 674
 675 // Vector without rounding mode
 676
 677 // cvtt fp-to-int staff
 678 def X86cvttp2si      : SDNode<"X86ISD::CVTTP2SI",  SDTFloatToInt>;
 679 def X86cvttp2ui      : SDNode<"X86ISD::CVTTP2UI",  SDTFloatToInt>;
 680 def X86strict_cvttp2si : SDNode<"X86ISD::STRICT_CVTTP2SI",  SDTFloatToInt, [SDNPHasChain]>;
 681 def X86strict_cvttp2ui : SDNode<"X86ISD::STRICT_CVTTP2UI",  SDTFloatToInt, [SDNPHasChain]>;
 682 def X86any_cvttp2si : PatFrags<(ops node:$src),
 683                                [(X86strict_cvttp2si node:$src),
 684                                 (X86cvttp2si node:$src)]>;
 685 def X86any_cvttp2ui : PatFrags<(ops node:$src),
 686                                [(X86strict_cvttp2ui node:$src),
 687                                 (X86cvttp2ui node:$src)]>;
 688
 689 def X86VSintToFP      : SDNode<"X86ISD::CVTSI2P",  SDTVintToFP>;
 690 def X86VUintToFP      : SDNode<"X86ISD::CVTUI2P",  SDTVintToFP>;
 691 def X86strict_VSintToFP : SDNode<"X86ISD::STRICT_CVTSI2P",  SDTVintToFP, [SDNPHasChain]>;
 692 def X86strict_VUintToFP : SDNode<"X86ISD::STRICT_CVTUI2P",  SDTVintToFP, [SDNPHasChain]>;
 693 def X86any_VSintToFP : PatFrags<(ops node:$src),
 694                                 [(X86strict_VSintToFP node:$src),
 695                                  (X86VSintToFP node:$src)]>;
 696 def X86any_VUintToFP : PatFrags<(ops node:$src),
 697                                 [(X86strict_VUintToFP node:$src),
 698                                  (X86VUintToFP node:$src)]>;
 699
 700
 701 // cvt int-to-fp staff
 702 def X86cvtp2Int      : SDNode<"X86ISD::CVTP2SI",  SDTFloatToInt>;
 703 def X86cvtp2UInt     : SDNode<"X86ISD::CVTP2UI",  SDTFloatToInt>;
 704
 705
 706 // Masked versions of above
 707 def SDTMVintToFP: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
 708                                        SDTCisFP<0>, SDTCisInt<1>,
 709                                        SDTCisSameSizeAs<0, 1>,
 710                                        SDTCisSameAs<0, 2>,
 711                                        SDTCVecEltisVT<3, i1>,
 712                                        SDTCisSameNumEltsAs<1, 3>]>;
 713 def SDTMFloatToInt: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
 714                                          SDTCisInt<0>, SDTCisFP<1>,
 715                                          SDTCisSameSizeAs<0, 1>,
 716                                          SDTCisSameAs<0, 2>,
 717                                          SDTCVecEltisVT<3, i1>,
 718                                          SDTCisSameNumEltsAs<1, 3>]>;
 719
 720 def X86VMSintToFP    : SDNode<"X86ISD::MCVTSI2P",  SDTMVintToFP>;
 721 def X86VMUintToFP    : SDNode<"X86ISD::MCVTUI2P",  SDTMVintToFP>;
 722
 723 def X86mcvtp2Int     : SDNode<"X86ISD::MCVTP2SI",  SDTMFloatToInt>;
 724 def X86mcvtp2UInt    : SDNode<"X86ISD::MCVTP2UI",  SDTMFloatToInt>;
 725 def X86mcvttp2si     : SDNode<"X86ISD::MCVTTP2SI", SDTMFloatToInt>;
 726 def X86mcvttp2ui     : SDNode<"X86ISD::MCVTTP2UI", SDTMFloatToInt>;
 727
 728 def SDTcvtph2ps : SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
 729                                        SDTCVecEltisVT<1, i16>]>;
 730 def X86cvtph2ps        : SDNode<"X86ISD::CVTPH2PS", SDTcvtph2ps>;
 731 def X86strict_cvtph2ps : SDNode<"X86ISD::STRICT_CVTPH2PS", SDTcvtph2ps,
 732                                 [SDNPHasChain]>;
 733 def X86any_cvtph2ps : PatFrags<(ops node:$src),
 734                                [(X86strict_cvtph2ps node:$src),
 735                                 (X86cvtph2ps node:$src)]>;
 736
 737 def X86cvtph2psSAE     : SDNode<"X86ISD::CVTPH2PS_SAE", SDTcvtph2ps>;
 738
 739 def SDTcvtps2ph : SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>,
 740                                        SDTCVecEltisVT<1, f32>,
 741                                        SDTCisVT<2, i32>]>;
 742 def X86cvtps2ph        : SDNode<"X86ISD::CVTPS2PH", SDTcvtps2ph>;
 743 def X86strict_cvtps2ph : SDNode<"X86ISD::STRICT_CVTPS2PH", SDTcvtps2ph,
 744                                 [SDNPHasChain]>;
 745 def X86any_cvtps2ph : PatFrags<(ops node:$src1, node:$src2),
 746                                [(X86strict_cvtps2ph node:$src1, node:$src2),
 747                                 (X86cvtps2ph node:$src1, node:$src2)]>;
 748
 749 def X86mcvtps2ph   : SDNode<"X86ISD::MCVTPS2PH",
 750                         SDTypeProfile<1, 4, [SDTCVecEltisVT<0, i16>,
 751                                              SDTCVecEltisVT<1, f32>,
 752                                              SDTCisVT<2, i32>,
 753                                              SDTCisSameAs<0, 3>,
 754                                              SDTCVecEltisVT<4, i1>,
 755                                              SDTCisSameNumEltsAs<1, 4>]> >;
 756 def X86vfpextSAE  : SDNode<"X86ISD::VFPEXT_SAE",
 757                         SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>,
 758                                              SDTCVecEltisVT<1, f32>,
 759                                              SDTCisOpSmallerThanOp<1, 0>]>>;
 760 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND_RND",
 761                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>,
 762                                              SDTCVecEltisVT<1, f64>,
 763                                              SDTCisOpSmallerThanOp<0, 1>,
 764                                              SDTCisVT<2, i32>]>>;
 765
 766 // cvt fp to bfloat16
 767 def X86cvtne2ps2bf16 : SDNode<"X86ISD::CVTNE2PS2BF16",
 768                        SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>,
 769                                             SDTCVecEltisVT<1, f32>,
 770                                             SDTCisSameSizeAs<0,1>,
 771                                             SDTCisSameAs<1,2>]>>;
 772 def X86mcvtneps2bf16 : SDNode<"X86ISD::MCVTNEPS2BF16",
 773                        SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>,
 774                                             SDTCVecEltisVT<1, f32>,
 775                                             SDTCisSameAs<0, 2>,
 776                                             SDTCVecEltisVT<3, i1>,
 777                                             SDTCisSameNumEltsAs<1, 3>]>>;
 778 def X86cvtneps2bf16 :  SDNode<"X86ISD::CVTNEPS2BF16",
 779                        SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i16>,
 780                                             SDTCVecEltisVT<1, f32>]>>;
 781 def X86dpbf16ps :      SDNode<"X86ISD::DPBF16PS",
 782                        SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>,
 783                                             SDTCisSameAs<0,1>,
 784                                             SDTCVecEltisVT<2, i32>,
 785                                             SDTCisSameAs<2,3>]>>;
 786
 787 // galois field arithmetic
 788 def X86GF2P8affineinvqb : SDNode<"X86ISD::GF2P8AFFINEINVQB", SDTBlend>;
 789 def X86GF2P8affineqb    : SDNode<"X86ISD::GF2P8AFFINEQB", SDTBlend>;
 790 def X86GF2P8mulb        : SDNode<"X86ISD::GF2P8MULB", SDTIntBinOp>;
 791
 792 def SDTX86MaskedStore: SDTypeProfile<0, 3, [       // masked store
 793   SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>
 794 ]>;
 795
 796 //===----------------------------------------------------------------------===//
 797 // SSE pattern fragments
 798 //===----------------------------------------------------------------------===//
 799
 800 // 128-bit load pattern fragments
 801 def loadv4f32    : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
 802 def loadv2f64    : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
 803 def loadv2i64    : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
 804 def loadv4i32    : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
 805 def loadv8i16    : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>;
 806 def loadv16i8    : PatFrag<(ops node:$ptr), (v16i8 (load node:$ptr))>;
 807
 808 // 256-bit load pattern fragments
 809 def loadv8f32    : PatFrag<(ops node:$ptr), (v8f32  (load node:$ptr))>;
 810 def loadv4f64    : PatFrag<(ops node:$ptr), (v4f64  (load node:$ptr))>;
 811 def loadv4i64    : PatFrag<(ops node:$ptr), (v4i64  (load node:$ptr))>;
 812 def loadv8i32    : PatFrag<(ops node:$ptr), (v8i32  (load node:$ptr))>;
 813 def loadv16i16   : PatFrag<(ops node:$ptr), (v16i16 (load node:$ptr))>;
 814 def loadv32i8    : PatFrag<(ops node:$ptr), (v32i8  (load node:$ptr))>;
 815
 816 // 512-bit load pattern fragments
 817 def loadv16f32   : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
 818 def loadv8f64    : PatFrag<(ops node:$ptr), (v8f64  (load node:$ptr))>;
 819 def loadv8i64    : PatFrag<(ops node:$ptr), (v8i64  (load node:$ptr))>;
 820 def loadv16i32   : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
 821 def loadv32i16   : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
 822 def loadv64i8    : PatFrag<(ops node:$ptr), (v64i8  (load node:$ptr))>;
 823
 824 // 128-/256-/512-bit extload pattern fragments
 825 def extloadv2f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>;
 826 def extloadv4f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>;
 827 def extloadv8f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>;
 828
 829 // Like 'store', but always requires vector size alignment.
 830 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
 831                            (store node:$val, node:$ptr), [{
 832   auto *St = cast<StoreSDNode>(N);
 833   return St->getAlignment() >= St->getMemoryVT().getStoreSize();
 834 }]>;
 835
 836 // Like 'load', but always requires vector size alignment.
 837 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 838   auto *Ld = cast<LoadSDNode>(N);
 839   return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
 840 }]>;
 841
 842 // 128-bit aligned load pattern fragments
 843 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 844 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
 845                                (v4f32 (alignedload node:$ptr))>;
 846 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
 847                                (v2f64 (alignedload node:$ptr))>;
 848 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
 849                                (v2i64 (alignedload node:$ptr))>;
 850 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
 851                                (v4i32 (alignedload node:$ptr))>;
 852 def alignedloadv8i16 : PatFrag<(ops node:$ptr),
 853                                (v8i16 (alignedload node:$ptr))>;
 854 def alignedloadv16i8 : PatFrag<(ops node:$ptr),
 855                                (v16i8 (alignedload node:$ptr))>;
 856
 857 // 256-bit aligned load pattern fragments
 858 // NOTE: all 256-bit integer vector loads are promoted to v4i64
 859 def alignedloadv8f32  : PatFrag<(ops node:$ptr),
 860                                 (v8f32  (alignedload node:$ptr))>;
 861 def alignedloadv4f64  : PatFrag<(ops node:$ptr),
 862                                 (v4f64  (alignedload node:$ptr))>;
 863 def alignedloadv4i64  : PatFrag<(ops node:$ptr),
 864                                 (v4i64  (alignedload node:$ptr))>;
 865 def alignedloadv8i32  : PatFrag<(ops node:$ptr),
 866                                 (v8i32  (alignedload node:$ptr))>;
 867 def alignedloadv16i16 : PatFrag<(ops node:$ptr),
 868                                 (v16i16 (alignedload node:$ptr))>;
 869 def alignedloadv32i8  : PatFrag<(ops node:$ptr),
 870                                 (v32i8  (alignedload node:$ptr))>;
 871
 872 // 512-bit aligned load pattern fragments
 873 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
 874                                 (v16f32 (alignedload node:$ptr))>;
 875 def alignedloadv8f64  : PatFrag<(ops node:$ptr),
 876                                 (v8f64  (alignedload node:$ptr))>;
 877 def alignedloadv8i64  : PatFrag<(ops node:$ptr),
 878                                 (v8i64  (alignedload node:$ptr))>;
 879 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
 880                                 (v16i32 (alignedload node:$ptr))>;
 881 def alignedloadv32i16 : PatFrag<(ops node:$ptr),
 882                                 (v32i16 (alignedload node:$ptr))>;
 883 def alignedloadv64i8  : PatFrag<(ops node:$ptr),
 884                                 (v64i8  (alignedload node:$ptr))>;
 885
 886 // Like 'load', but uses special alignment checks suitable for use in
 887 // memory operands in most SSE instructions, which are required to
 888 // be naturally aligned on some targets but not on others.  If the subtarget
 889 // allows unaligned accesses, match any load, though this may require
 890 // setting a feature bit in the processor (on startup, for example).
 891 // Opteron 10h and later implement such a feature.
 892 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 893   auto *Ld = cast<LoadSDNode>(N);
 894   return Subtarget->hasSSEUnalignedMem() ||
 895          Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
 896 }]>;
 897
 898 // 128-bit memop pattern fragments
 899 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 900 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
 901 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
 902 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
 903 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
 904 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>;
 905 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
 906
 907 // 128-bit bitconvert pattern fragments
 908 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
 909 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
 910 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
 911 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
 912 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
 913 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
 914
 915 // 256-bit bitconvert pattern fragments
 916 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
 917 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
 918 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
 919 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
 920 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
 921 def bc_v4f64 : PatFrag<(ops node:$in), (v4f64 (bitconvert node:$in))>;
 922
 923 // 512-bit bitconvert pattern fragments
 924 def bc_v64i8 : PatFrag<(ops node:$in), (v64i8 (bitconvert node:$in))>;
 925 def bc_v32i16 : PatFrag<(ops node:$in), (v32i16 (bitconvert node:$in))>;
 926 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
 927 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
 928 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
 929 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
 930
 931 def X86vzload32 : PatFrag<(ops node:$src),
 932                           (X86vzld node:$src), [{
 933   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 4;
 934 }]>;
 935
 936 def X86vzload64 : PatFrag<(ops node:$src),
 937                           (X86vzld node:$src), [{
 938   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 8;
 939 }]>;
 940
 941 def X86vextractstore64 : PatFrag<(ops node:$val, node:$ptr),
 942                                  (X86vextractst node:$val, node:$ptr), [{
 943   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 8;
 944 }]>;
 945
 946 def X86VBroadcastld8 : PatFrag<(ops node:$src),
 947                                (X86VBroadcastld node:$src), [{
 948   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 1;
 949 }]>;
 950
 951 def X86VBroadcastld16 : PatFrag<(ops node:$src),
 952                                 (X86VBroadcastld node:$src), [{
 953   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 2;
 954 }]>;
 955
 956 def X86VBroadcastld32 : PatFrag<(ops node:$src),
 957                                 (X86VBroadcastld node:$src), [{
 958   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 4;
 959 }]>;
 960
 961 def X86VBroadcastld64 : PatFrag<(ops node:$src),
 962                                 (X86VBroadcastld node:$src), [{
 963   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 8;
 964 }]>;
 965
 966 // Scalar SSE intrinsic fragments to match several different types of loads.
 967 // Used by scalar SSE intrinsic instructions which have 128 bit types, but
 968 // only load a single element.
 969 // FIXME: We should add more canolicalizing in DAGCombine. Particulary removing
 970 // the simple_load case.
 971 def sse_load_f32 : PatFrags<(ops node:$ptr),
 972                             [(v4f32 (simple_load node:$ptr)),
 973                              (v4f32 (X86vzload32 node:$ptr)),
 974                              (v4f32 (scalar_to_vector (loadf32 node:$ptr)))]>;
 975 def sse_load_f64 : PatFrags<(ops node:$ptr),
 976                             [(v2f64 (simple_load node:$ptr)),
 977                              (v2f64 (X86vzload64 node:$ptr)),
 978                              (v2f64 (scalar_to_vector (loadf64 node:$ptr)))]>;
 979
 980 def ssmem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand>;
 981 def sdmem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand>;
 982
 983
 984 def fp32imm0 : PatLeaf<(f32 fpimm), [{
 985   return N->isExactlyValue(+0.0);
 986 }]>;
 987
 988 def fp64imm0 : PatLeaf<(f64 fpimm), [{
 989   return N->isExactlyValue(+0.0);
 990 }]>;
 991
 992 def fp128imm0 : PatLeaf<(f128 fpimm), [{
 993   return N->isExactlyValue(+0.0);
 994 }]>;
 995
 996 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
 997 // to VEXTRACTF128/VEXTRACTI128 imm.
 998 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
 999   return getExtractVEXTRACTImmediate(N, 128, SDLoc(N));
1000 }]>;
1001
1002 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
1003 // VINSERTF128/VINSERTI128 imm.
1004 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
1005   return getInsertVINSERTImmediate(N, 128, SDLoc(N));
1006 }]>;
1007
1008 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
1009 // to VEXTRACTF64x4 imm.
1010 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
1011   return getExtractVEXTRACTImmediate(N, 256, SDLoc(N));
1012 }]>;
1013
1014 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
1015 // VINSERTF64x4 imm.
1016 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
1017   return getInsertVINSERTImmediate(N, 256, SDLoc(N));
1018 }]>;
1019
1020 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
1021                                    (extract_subvector node:$bigvec,
1022                                                       node:$index), [{
1023   // Index 0 can be handled via extract_subreg.
1024   return !isNullConstant(N->getOperand(1));
1025 }], EXTRACT_get_vextract128_imm>;
1026
1027 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
1028                                       node:$index),
1029                                  (insert_subvector node:$bigvec, node:$smallvec,
1030                                                    node:$index), [{}],
1031                                 INSERT_get_vinsert128_imm>;
1032
1033 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
1034                                    (extract_subvector node:$bigvec,
1035                                                       node:$index), [{
1036   // Index 0 can be handled via extract_subreg.
1037   return !isNullConstant(N->getOperand(1));
1038 }], EXTRACT_get_vextract256_imm>;
1039
1040 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
1041                                       node:$index),
1042                                  (insert_subvector node:$bigvec, node:$smallvec,
1043                                                    node:$index), [{}],
1044                                 INSERT_get_vinsert256_imm>;
1045
1046 def masked_load : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1047                           (masked_ld node:$src1, undef, node:$src2, node:$src3), [{
1048   return !cast<MaskedLoadSDNode>(N)->isExpandingLoad() &&
1049     cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD &&
1050     cast<MaskedLoadSDNode>(N)->isUnindexed();
1051 }]>;
1052
1053 def masked_load_aligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1054                          (masked_load node:$src1, node:$src2, node:$src3), [{
1055   // Use the node type to determine the size the alignment needs to match.
1056   // We can't use memory VT because type widening changes the node VT, but
1057   // not the memory VT.
1058   auto *Ld = cast<MaskedLoadSDNode>(N);
1059   return Ld->getAlignment() >= Ld->getValueType(0).getStoreSize();
1060 }]>;
1061
1062 def X86mExpandingLoad : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1063                          (masked_ld node:$src1, undef, node:$src2, node:$src3), [{
1064   return cast<MaskedLoadSDNode>(N)->isExpandingLoad() &&
1065          cast<MaskedLoadSDNode>(N)->isUnindexed();
1066 }]>;
1067
1068 // Masked store fragments.
1069 // X86mstore can't be implemented in core DAG files because some targets
1070 // do not support vector types (llvm-tblgen will fail).
1071 def masked_store : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1072                         (masked_st node:$src1, node:$src2, undef, node:$src3), [{
1073   return !cast<MaskedStoreSDNode>(N)->isTruncatingStore() &&
1074          !cast<MaskedStoreSDNode>(N)->isCompressingStore() &&
1075          cast<MaskedStoreSDNode>(N)->isUnindexed();
1076 }]>;
1077
1078 def masked_store_aligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1079                          (masked_store node:$src1, node:$src2, node:$src3), [{
1080   // Use the node type to determine the size the alignment needs to match.
1081   // We can't use memory VT because type widening changes the node VT, but
1082   // not the memory VT.
1083   auto *St = cast<MaskedStoreSDNode>(N);
1084   return St->getAlignment() >= St->getOperand(1).getValueType().getStoreSize();
1085 }]>;
1086
1087 def X86mCompressingStore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1088                              (masked_st node:$src1, node:$src2, undef, node:$src3), [{
1089     return cast<MaskedStoreSDNode>(N)->isCompressingStore() &&
1090            cast<MaskedStoreSDNode>(N)->isUnindexed();
1091 }]>;
1092
1093 // masked truncstore fragments
1094 // X86mtruncstore can't be implemented in core DAG files because some targets
1095 // doesn't support vector type ( llvm-tblgen will fail)
1096 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1097                              (masked_st node:$src1, node:$src2, undef, node:$src3), [{
1098     return cast<MaskedStoreSDNode>(N)->isTruncatingStore() &&
1099            cast<MaskedStoreSDNode>(N)->isUnindexed();
1100 }]>;
1101 def masked_truncstorevi8 :
1102   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1103           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1104   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1105 }]>;
1106 def masked_truncstorevi16 :
1107   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1108           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1109   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1110 }]>;
1111 def masked_truncstorevi32 :
1112   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1113           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1114   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1115 }]>;
1116
1117 def X86TruncSStore : SDNode<"X86ISD::VTRUNCSTORES",  SDTStore,
1118                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1119
1120 def X86TruncUSStore : SDNode<"X86ISD::VTRUNCSTOREUS",  SDTStore,
1121                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1122
1123 def X86MTruncSStore : SDNode<"X86ISD::VMTRUNCSTORES",  SDTX86MaskedStore,
1124                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1125
1126 def X86MTruncUSStore : SDNode<"X86ISD::VMTRUNCSTOREUS",  SDTX86MaskedStore,
1127                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1128
1129 def truncstore_s_vi8 : PatFrag<(ops node:$val, node:$ptr),
1130                                (X86TruncSStore node:$val, node:$ptr), [{
1131   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1132 }]>;
1133
1134 def truncstore_us_vi8 : PatFrag<(ops node:$val, node:$ptr),
1135                                (X86TruncUSStore node:$val, node:$ptr), [{
1136   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1137 }]>;
1138
1139 def truncstore_s_vi16 : PatFrag<(ops node:$val, node:$ptr),
1140                                (X86TruncSStore node:$val, node:$ptr), [{
1141   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1142 }]>;
1143
1144 def truncstore_us_vi16 : PatFrag<(ops node:$val, node:$ptr),
1145                                (X86TruncUSStore node:$val, node:$ptr), [{
1146   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1147 }]>;
1148
1149 def truncstore_s_vi32 : PatFrag<(ops node:$val, node:$ptr),
1150                                (X86TruncSStore node:$val, node:$ptr), [{
1151   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1152 }]>;
1153
1154 def truncstore_us_vi32 : PatFrag<(ops node:$val, node:$ptr),
1155                                (X86TruncUSStore node:$val, node:$ptr), [{
1156   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1157 }]>;
1158
1159 def masked_truncstore_s_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1160                      (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1161   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1162 }]>;
1163
1164 def masked_truncstore_us_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1165                                (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1166   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1167 }]>;
1168
1169 def masked_truncstore_s_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1170                                (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1171   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1172 }]>;
1173
1174 def masked_truncstore_us_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1175                                (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1176   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1177 }]>;
1178
1179 def masked_truncstore_s_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1180                                (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1181   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1182 }]>;
1183
1184 def masked_truncstore_us_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1185                                (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1186   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1187 }]>;