1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //===----------------------------------------------------------------------===//
13 #include "X86InstrInfo.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrFoldTables.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Sequence.h"
22 #include "llvm/CodeGen/LivePhysRegs.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/StackMaps.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/LLVMContext.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCExpr.h"
36 #include "llvm/MC/MCInst.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
45 #define DEBUG_TYPE "x86-instr-info"
47 #define GET_INSTRINFO_CTOR_DTOR
48 #include "X86GenInstrInfo.inc"
51 NoFusing("disable-spill-fusing",
52 cl::desc("Disable fusing of spill code into instructions"),
55 PrintFailedFusing("print-failed-fuse-candidates",
56 cl::desc("Print instructions that the allocator wants to"
57 " fuse, but the X86 backend currently can't"),
60 ReMatPICStubLoad("remat-pic-stub-load",
61 cl::desc("Re-materialize load from stub in PIC mode"),
62 cl::init(false), cl::Hidden);
63 static cl::opt<unsigned>
64 PartialRegUpdateClearance("partial-reg-update-clearance",
65 cl::desc("Clearance between two register writes "
66 "for inserting XOR to avoid partial "
68 cl::init(64), cl::Hidden);
69 static cl::opt<unsigned>
70 UndefRegClearance("undef-reg-clearance",
71 cl::desc("How many idle instructions we would like before "
72 "certain undef register reads"),
73 cl::init(128), cl::Hidden);
76 // Pin the vtable to this file.
77 void X86InstrInfo::anchor() {}
79 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
80 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
81 : X86::ADJCALLSTACKDOWN32),
82 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
83 : X86::ADJCALLSTACKUP32),
85 (STI.is64Bit() ? X86::RETQ : X86::RETL)),
86 Subtarget(STI), RI(STI.getTargetTriple()) {
90 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
91 unsigned &SrcReg, unsigned &DstReg,
92 unsigned &SubIdx) const {
93 switch (MI.getOpcode()) {
100 if (!Subtarget.is64Bit())
101 // It's not always legal to reference the low 8-bit of the larger
102 // register in 32-bit mode.
105 case X86::MOVSX32rr16:
106 case X86::MOVZX32rr16:
107 case X86::MOVSX64rr16:
108 case X86::MOVSX64rr32: {
109 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
112 SrcReg = MI.getOperand(1).getReg();
113 DstReg = MI.getOperand(0).getReg();
114 switch (MI.getOpcode()) {
115 default: llvm_unreachable("Unreachable!");
116 case X86::MOVSX16rr8:
117 case X86::MOVZX16rr8:
118 case X86::MOVSX32rr8:
119 case X86::MOVZX32rr8:
120 case X86::MOVSX64rr8:
121 SubIdx = X86::sub_8bit;
123 case X86::MOVSX32rr16:
124 case X86::MOVZX32rr16:
125 case X86::MOVSX64rr16:
126 SubIdx = X86::sub_16bit;
128 case X86::MOVSX64rr32:
129 SubIdx = X86::sub_32bit;
138 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
139 const MachineFunction *MF = MI.getParent()->getParent();
140 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
142 if (isFrameInstr(MI)) {
143 unsigned StackAlign = TFI->getStackAlignment();
144 int SPAdj = alignTo(getFrameSize(MI), StackAlign);
145 SPAdj -= getFrameAdjustment(MI);
146 if (!isFrameSetup(MI))
151 // To know whether a call adjusts the stack, we need information
152 // that is bound to the following ADJCALLSTACKUP pseudo.
153 // Look for the next ADJCALLSTACKUP that follows the call.
155 const MachineBasicBlock *MBB = MI.getParent();
156 auto I = ++MachineBasicBlock::const_iterator(MI);
157 for (auto E = MBB->end(); I != E; ++I) {
158 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
163 // If we could not find a frame destroy opcode, then it has already
164 // been simplified, so we don't care.
165 if (I->getOpcode() != getCallFrameDestroyOpcode())
168 return -(I->getOperand(1).getImm());
171 // Currently handle only PUSHes we can reasonably expect to see
173 switch (MI.getOpcode()) {
191 /// Return true and the FrameIndex if the specified
192 /// operand and follow operands form a reference to the stack frame.
193 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
194 int &FrameIndex) const {
195 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
196 MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
197 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
198 MI.getOperand(Op + X86::AddrDisp).isImm() &&
199 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
200 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
201 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
202 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
208 static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
222 case X86::MOVSSrm_alt:
224 case X86::VMOVSSrm_alt:
226 case X86::VMOVSSZrm_alt:
233 case X86::MOVSDrm_alt:
235 case X86::VMOVSDrm_alt:
237 case X86::VMOVSDZrm_alt:
238 case X86::MMX_MOVD64rm:
239 case X86::MMX_MOVQ64rm:
255 case X86::VMOVAPSZ128rm:
256 case X86::VMOVUPSZ128rm:
257 case X86::VMOVAPSZ128rm_NOVLX:
258 case X86::VMOVUPSZ128rm_NOVLX:
259 case X86::VMOVAPDZ128rm:
260 case X86::VMOVUPDZ128rm:
261 case X86::VMOVDQU8Z128rm:
262 case X86::VMOVDQU16Z128rm:
263 case X86::VMOVDQA32Z128rm:
264 case X86::VMOVDQU32Z128rm:
265 case X86::VMOVDQA64Z128rm:
266 case X86::VMOVDQU64Z128rm:
269 case X86::VMOVAPSYrm:
270 case X86::VMOVUPSYrm:
271 case X86::VMOVAPDYrm:
272 case X86::VMOVUPDYrm:
273 case X86::VMOVDQAYrm:
274 case X86::VMOVDQUYrm:
275 case X86::VMOVAPSZ256rm:
276 case X86::VMOVUPSZ256rm:
277 case X86::VMOVAPSZ256rm_NOVLX:
278 case X86::VMOVUPSZ256rm_NOVLX:
279 case X86::VMOVAPDZ256rm:
280 case X86::VMOVUPDZ256rm:
281 case X86::VMOVDQU8Z256rm:
282 case X86::VMOVDQU16Z256rm:
283 case X86::VMOVDQA32Z256rm:
284 case X86::VMOVDQU32Z256rm:
285 case X86::VMOVDQA64Z256rm:
286 case X86::VMOVDQU64Z256rm:
289 case X86::VMOVAPSZrm:
290 case X86::VMOVUPSZrm:
291 case X86::VMOVAPDZrm:
292 case X86::VMOVUPDZrm:
293 case X86::VMOVDQU8Zrm:
294 case X86::VMOVDQU16Zrm:
295 case X86::VMOVDQA32Zrm:
296 case X86::VMOVDQU32Zrm:
297 case X86::VMOVDQA64Zrm:
298 case X86::VMOVDQU64Zrm:
304 static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
328 case X86::MMX_MOVD64mr:
329 case X86::MMX_MOVQ64mr:
330 case X86::MMX_MOVNTQmr:
346 case X86::VMOVUPSZ128mr:
347 case X86::VMOVAPSZ128mr:
348 case X86::VMOVUPSZ128mr_NOVLX:
349 case X86::VMOVAPSZ128mr_NOVLX:
350 case X86::VMOVUPDZ128mr:
351 case X86::VMOVAPDZ128mr:
352 case X86::VMOVDQA32Z128mr:
353 case X86::VMOVDQU32Z128mr:
354 case X86::VMOVDQA64Z128mr:
355 case X86::VMOVDQU64Z128mr:
356 case X86::VMOVDQU8Z128mr:
357 case X86::VMOVDQU16Z128mr:
360 case X86::VMOVUPSYmr:
361 case X86::VMOVAPSYmr:
362 case X86::VMOVUPDYmr:
363 case X86::VMOVAPDYmr:
364 case X86::VMOVDQUYmr:
365 case X86::VMOVDQAYmr:
366 case X86::VMOVUPSZ256mr:
367 case X86::VMOVAPSZ256mr:
368 case X86::VMOVUPSZ256mr_NOVLX:
369 case X86::VMOVAPSZ256mr_NOVLX:
370 case X86::VMOVUPDZ256mr:
371 case X86::VMOVAPDZ256mr:
372 case X86::VMOVDQU8Z256mr:
373 case X86::VMOVDQU16Z256mr:
374 case X86::VMOVDQA32Z256mr:
375 case X86::VMOVDQU32Z256mr:
376 case X86::VMOVDQA64Z256mr:
377 case X86::VMOVDQU64Z256mr:
380 case X86::VMOVUPSZmr:
381 case X86::VMOVAPSZmr:
382 case X86::VMOVUPDZmr:
383 case X86::VMOVAPDZmr:
384 case X86::VMOVDQU8Zmr:
385 case X86::VMOVDQU16Zmr:
386 case X86::VMOVDQA32Zmr:
387 case X86::VMOVDQU32Zmr:
388 case X86::VMOVDQA64Zmr:
389 case X86::VMOVDQU64Zmr:
396 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
397 int &FrameIndex) const {
399 return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
402 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
404 unsigned &MemBytes) const {
405 if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
406 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
407 return MI.getOperand(0).getReg();
411 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
412 int &FrameIndex) const {
414 if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
416 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
418 // Check for post-frame index elimination operations
419 SmallVector<const MachineMemOperand *, 1> Accesses;
420 if (hasLoadFromStackSlot(MI, Accesses)) {
422 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
430 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
431 int &FrameIndex) const {
433 return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
436 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
438 unsigned &MemBytes) const {
439 if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
440 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
441 isFrameOperand(MI, 0, FrameIndex))
442 return MI.getOperand(X86::AddrNumOperands).getReg();
446 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
447 int &FrameIndex) const {
449 if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
451 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
453 // Check for post-frame index elimination operations
454 SmallVector<const MachineMemOperand *, 1> Accesses;
455 if (hasStoreToStackSlot(MI, Accesses)) {
457 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
465 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
466 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
467 // Don't waste compile time scanning use-def chains of physregs.
468 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
470 bool isPICBase = false;
471 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
472 E = MRI.def_instr_end(); I != E; ++I) {
473 MachineInstr *DefMI = &*I;
474 if (DefMI->getOpcode() != X86::MOVPC32r)
476 assert(!isPICBase && "More than one PIC base?");
482 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
483 AliasAnalysis *AA) const {
484 switch (MI.getOpcode()) {
487 case X86::MOV8rm_NOREX:
492 case X86::MOVSSrm_alt:
494 case X86::MOVSDrm_alt:
502 case X86::VMOVSSrm_alt:
504 case X86::VMOVSDrm_alt:
511 case X86::VMOVAPSYrm:
512 case X86::VMOVUPSYrm:
513 case X86::VMOVAPDYrm:
514 case X86::VMOVUPDYrm:
515 case X86::VMOVDQAYrm:
516 case X86::VMOVDQUYrm:
517 case X86::MMX_MOVD64rm:
518 case X86::MMX_MOVQ64rm:
521 case X86::VMOVSSZrm_alt:
523 case X86::VMOVSDZrm_alt:
524 case X86::VMOVAPDZ128rm:
525 case X86::VMOVAPDZ256rm:
526 case X86::VMOVAPDZrm:
527 case X86::VMOVAPSZ128rm:
528 case X86::VMOVAPSZ256rm:
529 case X86::VMOVAPSZ128rm_NOVLX:
530 case X86::VMOVAPSZ256rm_NOVLX:
531 case X86::VMOVAPSZrm:
532 case X86::VMOVDQA32Z128rm:
533 case X86::VMOVDQA32Z256rm:
534 case X86::VMOVDQA32Zrm:
535 case X86::VMOVDQA64Z128rm:
536 case X86::VMOVDQA64Z256rm:
537 case X86::VMOVDQA64Zrm:
538 case X86::VMOVDQU16Z128rm:
539 case X86::VMOVDQU16Z256rm:
540 case X86::VMOVDQU16Zrm:
541 case X86::VMOVDQU32Z128rm:
542 case X86::VMOVDQU32Z256rm:
543 case X86::VMOVDQU32Zrm:
544 case X86::VMOVDQU64Z128rm:
545 case X86::VMOVDQU64Z256rm:
546 case X86::VMOVDQU64Zrm:
547 case X86::VMOVDQU8Z128rm:
548 case X86::VMOVDQU8Z256rm:
549 case X86::VMOVDQU8Zrm:
550 case X86::VMOVUPDZ128rm:
551 case X86::VMOVUPDZ256rm:
552 case X86::VMOVUPDZrm:
553 case X86::VMOVUPSZ128rm:
554 case X86::VMOVUPSZ256rm:
555 case X86::VMOVUPSZ128rm_NOVLX:
556 case X86::VMOVUPSZ256rm_NOVLX:
557 case X86::VMOVUPSZrm: {
558 // Loads from constant pools are trivially rematerializable.
559 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
560 MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
561 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
562 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
563 MI.isDereferenceableInvariantLoad(AA)) {
564 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
565 if (BaseReg == 0 || BaseReg == X86::RIP)
567 // Allow re-materialization of PIC load.
568 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
570 const MachineFunction &MF = *MI.getParent()->getParent();
571 const MachineRegisterInfo &MRI = MF.getRegInfo();
572 return regIsPICBase(BaseReg, MRI);
579 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
580 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
581 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
582 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
583 // lea fi#, lea GV, etc. are all rematerializable.
584 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
586 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
589 // Allow re-materialization of lea PICBase + x.
590 const MachineFunction &MF = *MI.getParent()->getParent();
591 const MachineRegisterInfo &MRI = MF.getRegInfo();
592 return regIsPICBase(BaseReg, MRI);
598 // All other instructions marked M_REMATERIALIZABLE are always trivially
603 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
604 MachineBasicBlock::iterator I,
605 unsigned DestReg, unsigned SubIdx,
606 const MachineInstr &Orig,
607 const TargetRegisterInfo &TRI) const {
608 bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
609 if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
610 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
613 switch (Orig.getOpcode()) {
614 case X86::MOV32r0: Value = 0; break;
615 case X86::MOV32r1: Value = 1; break;
616 case X86::MOV32r_1: Value = -1; break;
618 llvm_unreachable("Unexpected instruction!");
621 const DebugLoc &DL = Orig.getDebugLoc();
622 BuildMI(MBB, I, DL, get(X86::MOV32ri))
623 .add(Orig.getOperand(0))
626 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
630 MachineInstr &NewMI = *std::prev(I);
631 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
634 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
635 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
636 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
637 MachineOperand &MO = MI.getOperand(i);
638 if (MO.isReg() && MO.isDef() &&
639 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
646 /// Check whether the shift count for a machine operand is non-zero.
647 inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
648 unsigned ShiftAmtOperandIdx) {
649 // The shift count is six bits with the REX.W prefix and five bits without.
650 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
651 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
652 return Imm & ShiftCountMask;
655 /// Check whether the given shift count is appropriate
656 /// can be represented by a LEA instruction.
657 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
658 // Left shift instructions can be transformed into load-effective-address
659 // instructions if we can encode them appropriately.
660 // A LEA instruction utilizes a SIB byte to encode its scale factor.
661 // The SIB.scale field is two bits wide which means that we can encode any
662 // shift amount less than 4.
663 return ShAmt < 4 && ShAmt > 0;
666 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
667 unsigned Opc, bool AllowSP, unsigned &NewSrc,
668 bool &isKill, MachineOperand &ImplicitOp,
669 LiveVariables *LV) const {
670 MachineFunction &MF = *MI.getParent()->getParent();
671 const TargetRegisterClass *RC;
673 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
675 RC = Opc != X86::LEA32r ?
676 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
678 unsigned SrcReg = Src.getReg();
680 // For both LEA64 and LEA32 the register already has essentially the right
681 // type (32-bit or 64-bit) we may just need to forbid SP.
682 if (Opc != X86::LEA64_32r) {
684 isKill = Src.isKill();
685 assert(!Src.isUndef() && "Undef op doesn't need optimization");
687 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
688 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
694 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
695 // another we need to add 64-bit registers to the final MI.
696 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
698 ImplicitOp.setImplicit();
700 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
701 isKill = Src.isKill();
702 assert(!Src.isUndef() && "Undef op doesn't need optimization");
704 // Virtual register of the wrong class, we have to create a temporary 64-bit
705 // vreg to feed into the LEA.
706 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
708 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
709 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
712 // Which is obviously going to be dead after we're done with it.
716 LV->replaceKillInstruction(SrcReg, MI, *Copy);
719 // We've set all the parameters without issue.
723 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
724 unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
725 LiveVariables *LV, bool Is8BitOp) const {
726 // We handle 8-bit adds and various 16-bit opcodes in the switch below.
727 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
728 assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
729 *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
730 "Unexpected type for LEA transform");
732 // TODO: For a 32-bit target, we need to adjust the LEA variables with
733 // something like this:
734 // Opcode = X86::LEA32r;
735 // InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
737 // Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
738 // : RegInfo.createVirtualRegister(&X86::GR32RegClass);
739 if (!Subtarget.is64Bit())
742 unsigned Opcode = X86::LEA64_32r;
743 unsigned InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
744 unsigned OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
746 // Build and insert into an implicit UNDEF value. This is OK because
747 // we will be shifting and then extracting the lower 8/16-bits.
748 // This has the potential to cause partial register stall. e.g.
749 // movw (%rbp,%rcx,2), %dx
750 // leal -65(%rdx), %esi
751 // But testing has shown this *does* help performance in 64-bit mode (at
752 // least on modern x86 machines).
753 MachineBasicBlock::iterator MBBI = MI.getIterator();
754 unsigned Dest = MI.getOperand(0).getReg();
755 unsigned Src = MI.getOperand(1).getReg();
756 bool IsDead = MI.getOperand(0).isDead();
757 bool IsKill = MI.getOperand(1).isKill();
758 unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
759 assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
760 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
761 MachineInstr *InsMI =
762 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
763 .addReg(InRegLEA, RegState::Define, SubReg)
764 .addReg(Src, getKillRegState(IsKill));
766 MachineInstrBuilder MIB =
767 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
769 default: llvm_unreachable("Unreachable!");
772 unsigned ShAmt = MI.getOperand(2).getImm();
773 MIB.addReg(0).addImm(1ULL << ShAmt)
774 .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
779 addRegOffset(MIB, InRegLEA, true, 1);
783 addRegOffset(MIB, InRegLEA, true, -1);
789 case X86::ADD16ri_DB:
790 case X86::ADD16ri8_DB:
791 addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
796 case X86::ADD16rr_DB: {
797 unsigned Src2 = MI.getOperand(2).getReg();
798 bool IsKill2 = MI.getOperand(2).isKill();
799 assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
800 unsigned InRegLEA2 = 0;
801 MachineInstr *InsMI2 = nullptr;
803 // ADD8rr/ADD16rr killed %reg1028, %reg1028
804 // just a single insert_subreg.
805 addRegReg(MIB, InRegLEA, true, InRegLEA, false);
807 if (Subtarget.is64Bit())
808 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
810 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
811 // Build and insert into an implicit UNDEF value. This is OK because
812 // we will be shifting and then extracting the lower 8/16-bits.
813 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
814 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
815 .addReg(InRegLEA2, RegState::Define, SubReg)
816 .addReg(Src2, getKillRegState(IsKill2));
817 addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
819 if (LV && IsKill2 && InsMI2)
820 LV->replaceKillInstruction(Src2, MI, *InsMI2);
825 MachineInstr *NewMI = MIB;
826 MachineInstr *ExtMI =
827 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
828 .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
829 .addReg(OutRegLEA, RegState::Kill, SubReg);
832 // Update live variables.
833 LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
834 LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
836 LV->replaceKillInstruction(Src, MI, *InsMI);
838 LV->replaceKillInstruction(Dest, MI, *ExtMI);
844 /// This method must be implemented by targets that
845 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
846 /// may be able to convert a two-address instruction into a true
847 /// three-address instruction on demand. This allows the X86 target (for
848 /// example) to convert ADD and SHL instructions into LEA instructions if they
849 /// would require register copies due to two-addressness.
851 /// This method returns a null pointer if the transformation cannot be
852 /// performed, otherwise it returns the new instruction.
855 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
856 MachineInstr &MI, LiveVariables *LV) const {
857 // The following opcodes also sets the condition code register(s). Only
858 // convert them to equivalent lea if the condition code register def's
860 if (hasLiveCondCodeDef(MI))
863 MachineFunction &MF = *MI.getParent()->getParent();
864 // All instructions input are two-addr instructions. Get the known operands.
865 const MachineOperand &Dest = MI.getOperand(0);
866 const MachineOperand &Src = MI.getOperand(1);
868 // Ideally, operations with undef should be folded before we get here, but we
869 // can't guarantee it. Bail out because optimizing undefs is a waste of time.
870 // Without this, we have to forward undef state to new register operands to
871 // avoid machine verifier errors.
874 if (MI.getNumOperands() > 2)
875 if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
878 MachineInstr *NewMI = nullptr;
879 bool Is64Bit = Subtarget.is64Bit();
881 bool Is8BitOp = false;
882 unsigned MIOpc = MI.getOpcode();
884 default: llvm_unreachable("Unreachable!");
886 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
887 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
888 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
890 // LEA can't handle RSP.
891 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
892 !MF.getRegInfo().constrainRegClass(Src.getReg(),
893 &X86::GR64_NOSPRegClass))
896 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
899 .addImm(1ULL << ShAmt)
906 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
907 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
908 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
910 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
912 // LEA can't handle ESP.
915 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
916 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
917 SrcReg, isKill, ImplicitOp, LV))
920 MachineInstrBuilder MIB =
921 BuildMI(MF, MI.getDebugLoc(), get(Opc))
924 .addImm(1ULL << ShAmt)
925 .addReg(SrcReg, getKillRegState(isKill))
928 if (ImplicitOp.getReg() != 0)
938 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
939 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
940 if (!isTruncatedShiftCountForLEA(ShAmt))
942 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
946 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
947 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
948 (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
951 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
952 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
956 MachineInstrBuilder MIB =
957 BuildMI(MF, MI.getDebugLoc(), get(Opc))
959 .addReg(SrcReg, getKillRegState(isKill));
960 if (ImplicitOp.getReg() != 0)
963 NewMI = addOffset(MIB, 1);
968 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
969 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
970 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
974 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
975 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
979 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
981 .addReg(SrcReg, getKillRegState(isKill));
982 if (ImplicitOp.getReg() != 0)
985 NewMI = addOffset(MIB, -1);
995 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
997 case X86::ADD64rr_DB:
999 case X86::ADD32rr_DB: {
1000 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1002 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1005 Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1009 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1010 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1011 SrcReg, isKill, ImplicitOp, LV))
1014 const MachineOperand &Src2 = MI.getOperand(2);
1017 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1018 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
1019 SrcReg2, isKill2, ImplicitOp2, LV))
1022 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1023 if (ImplicitOp.getReg() != 0)
1024 MIB.add(ImplicitOp);
1025 if (ImplicitOp2.getReg() != 0)
1026 MIB.add(ImplicitOp2);
1028 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1029 if (LV && Src2.isKill())
1030 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1034 case X86::ADD8rr_DB:
1038 case X86::ADD16rr_DB:
1039 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1040 case X86::ADD64ri32:
1042 case X86::ADD64ri32_DB:
1043 case X86::ADD64ri8_DB:
1044 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1046 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1051 case X86::ADD32ri_DB:
1052 case X86::ADD32ri8_DB: {
1053 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1054 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1058 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1059 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1060 SrcReg, isKill, ImplicitOp, LV))
1063 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1065 .addReg(SrcReg, getKillRegState(isKill));
1066 if (ImplicitOp.getReg() != 0)
1067 MIB.add(ImplicitOp);
1069 NewMI = addOffset(MIB, MI.getOperand(2));
1073 case X86::ADD8ri_DB:
1078 case X86::ADD16ri_DB:
1079 case X86::ADD16ri8_DB:
1080 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1084 /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1087 case X86::SUB32ri: {
1088 if (!MI.getOperand(2).isImm())
1090 int64_t Imm = MI.getOperand(2).getImm();
1091 if (!isInt<32>(-Imm))
1094 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1095 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1099 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1100 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1101 SrcReg, isKill, ImplicitOp, LV))
1104 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1106 .addReg(SrcReg, getKillRegState(isKill));
1107 if (ImplicitOp.getReg() != 0)
1108 MIB.add(ImplicitOp);
1110 NewMI = addOffset(MIB, -Imm);
1115 case X86::SUB64ri32: {
1116 if (!MI.getOperand(2).isImm())
1118 int64_t Imm = MI.getOperand(2).getImm();
1119 if (!isInt<32>(-Imm))
1122 assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!");
1124 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
1125 get(X86::LEA64r)).add(Dest).add(Src);
1126 NewMI = addOffset(MIB, -Imm);
1130 case X86::VMOVDQU8Z128rmk:
1131 case X86::VMOVDQU8Z256rmk:
1132 case X86::VMOVDQU8Zrmk:
1133 case X86::VMOVDQU16Z128rmk:
1134 case X86::VMOVDQU16Z256rmk:
1135 case X86::VMOVDQU16Zrmk:
1136 case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1137 case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1138 case X86::VMOVDQU32Zrmk: case X86::VMOVDQA32Zrmk:
1139 case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1140 case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1141 case X86::VMOVDQU64Zrmk: case X86::VMOVDQA64Zrmk:
1142 case X86::VMOVUPDZ128rmk: case X86::VMOVAPDZ128rmk:
1143 case X86::VMOVUPDZ256rmk: case X86::VMOVAPDZ256rmk:
1144 case X86::VMOVUPDZrmk: case X86::VMOVAPDZrmk:
1145 case X86::VMOVUPSZ128rmk: case X86::VMOVAPSZ128rmk:
1146 case X86::VMOVUPSZ256rmk: case X86::VMOVAPSZ256rmk:
1147 case X86::VMOVUPSZrmk: case X86::VMOVAPSZrmk: {
1150 default: llvm_unreachable("Unreachable!");
1151 case X86::VMOVDQU8Z128rmk: Opc = X86::VPBLENDMBZ128rmk; break;
1152 case X86::VMOVDQU8Z256rmk: Opc = X86::VPBLENDMBZ256rmk; break;
1153 case X86::VMOVDQU8Zrmk: Opc = X86::VPBLENDMBZrmk; break;
1154 case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
1155 case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
1156 case X86::VMOVDQU16Zrmk: Opc = X86::VPBLENDMWZrmk; break;
1157 case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1158 case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1159 case X86::VMOVDQU32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1160 case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1161 case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1162 case X86::VMOVDQU64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1163 case X86::VMOVUPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1164 case X86::VMOVUPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1165 case X86::VMOVUPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1166 case X86::VMOVUPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1167 case X86::VMOVUPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1168 case X86::VMOVUPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1169 case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1170 case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1171 case X86::VMOVDQA32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1172 case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1173 case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1174 case X86::VMOVDQA64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1175 case X86::VMOVAPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1176 case X86::VMOVAPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1177 case X86::VMOVAPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1178 case X86::VMOVAPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1179 case X86::VMOVAPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1180 case X86::VMOVAPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1183 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1185 .add(MI.getOperand(2))
1187 .add(MI.getOperand(3))
1188 .add(MI.getOperand(4))
1189 .add(MI.getOperand(5))
1190 .add(MI.getOperand(6))
1191 .add(MI.getOperand(7));
1194 case X86::VMOVDQU8Z128rrk:
1195 case X86::VMOVDQU8Z256rrk:
1196 case X86::VMOVDQU8Zrrk:
1197 case X86::VMOVDQU16Z128rrk:
1198 case X86::VMOVDQU16Z256rrk:
1199 case X86::VMOVDQU16Zrrk:
1200 case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1201 case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1202 case X86::VMOVDQU32Zrrk: case X86::VMOVDQA32Zrrk:
1203 case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1204 case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1205 case X86::VMOVDQU64Zrrk: case X86::VMOVDQA64Zrrk:
1206 case X86::VMOVUPDZ128rrk: case X86::VMOVAPDZ128rrk:
1207 case X86::VMOVUPDZ256rrk: case X86::VMOVAPDZ256rrk:
1208 case X86::VMOVUPDZrrk: case X86::VMOVAPDZrrk:
1209 case X86::VMOVUPSZ128rrk: case X86::VMOVAPSZ128rrk:
1210 case X86::VMOVUPSZ256rrk: case X86::VMOVAPSZ256rrk:
1211 case X86::VMOVUPSZrrk: case X86::VMOVAPSZrrk: {
1214 default: llvm_unreachable("Unreachable!");
1215 case X86::VMOVDQU8Z128rrk: Opc = X86::VPBLENDMBZ128rrk; break;
1216 case X86::VMOVDQU8Z256rrk: Opc = X86::VPBLENDMBZ256rrk; break;
1217 case X86::VMOVDQU8Zrrk: Opc = X86::VPBLENDMBZrrk; break;
1218 case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1219 case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1220 case X86::VMOVDQU16Zrrk: Opc = X86::VPBLENDMWZrrk; break;
1221 case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1222 case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1223 case X86::VMOVDQU32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1224 case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1225 case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1226 case X86::VMOVDQU64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1227 case X86::VMOVUPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1228 case X86::VMOVUPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1229 case X86::VMOVUPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1230 case X86::VMOVUPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1231 case X86::VMOVUPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1232 case X86::VMOVUPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1233 case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1234 case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1235 case X86::VMOVDQA32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1236 case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1237 case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1238 case X86::VMOVDQA64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1239 case X86::VMOVAPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1240 case X86::VMOVAPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1241 case X86::VMOVAPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1242 case X86::VMOVAPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1243 case X86::VMOVAPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1244 case X86::VMOVAPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1247 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1249 .add(MI.getOperand(2))
1251 .add(MI.getOperand(3));
1256 if (!NewMI) return nullptr;
1258 if (LV) { // Update live variables
1260 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1262 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1265 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
1269 /// This determines which of three possible cases of a three source commute
1270 /// the source indexes correspond to taking into account any mask operands.
1271 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1273 /// Case 0 - Possible to commute the first and second operands.
1274 /// Case 1 - Possible to commute the first and third operands.
1275 /// Case 2 - Possible to commute the second and third operands.
1276 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1277 unsigned SrcOpIdx2) {
1278 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1279 if (SrcOpIdx1 > SrcOpIdx2)
1280 std::swap(SrcOpIdx1, SrcOpIdx2);
1282 unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1283 if (X86II::isKMasked(TSFlags)) {
1288 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1290 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1292 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1294 llvm_unreachable("Unknown three src commute case.");
1297 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1298 const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1299 const X86InstrFMA3Group &FMA3Group) const {
1301 unsigned Opc = MI.getOpcode();
1303 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1304 // analysis. The commute optimization is legal only if all users of FMA*_Int
1305 // use only the lowest element of the FMA*_Int instruction. Such analysis are
1306 // not implemented yet. So, just return 0 in that case.
1307 // When such analysis are available this place will be the right place for
1309 assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
1310 "Intrinsic instructions can't commute operand 1");
1312 // Determine which case this commute is or if it can't be done.
1313 unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1315 assert(Case < 3 && "Unexpected case number!");
1317 // Define the FMA forms mapping array that helps to map input FMA form
1318 // to output FMA form to preserve the operation semantics after
1319 // commuting the operands.
1320 const unsigned Form132Index = 0;
1321 const unsigned Form213Index = 1;
1322 const unsigned Form231Index = 2;
1323 static const unsigned FormMapping[][3] = {
1324 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1325 // FMA132 A, C, b; ==> FMA231 C, A, b;
1326 // FMA213 B, A, c; ==> FMA213 A, B, c;
1327 // FMA231 C, A, b; ==> FMA132 A, C, b;
1328 { Form231Index, Form213Index, Form132Index },
1329 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1330 // FMA132 A, c, B; ==> FMA132 B, c, A;
1331 // FMA213 B, a, C; ==> FMA231 C, a, B;
1332 // FMA231 C, a, B; ==> FMA213 B, a, C;
1333 { Form132Index, Form231Index, Form213Index },
1334 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1335 // FMA132 a, C, B; ==> FMA213 a, B, C;
1336 // FMA213 b, A, C; ==> FMA132 b, C, A;
1337 // FMA231 c, A, B; ==> FMA231 c, B, A;
1338 { Form213Index, Form132Index, Form231Index }
1341 unsigned FMAForms[3];
1342 FMAForms[0] = FMA3Group.get132Opcode();
1343 FMAForms[1] = FMA3Group.get213Opcode();
1344 FMAForms[2] = FMA3Group.get231Opcode();
1346 for (FormIndex = 0; FormIndex < 3; FormIndex++)
1347 if (Opc == FMAForms[FormIndex])
1350 // Everything is ready, just adjust the FMA opcode and return it.
1351 FormIndex = FormMapping[Case][FormIndex];
1352 return FMAForms[FormIndex];
1355 static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1356 unsigned SrcOpIdx2) {
1357 // Determine which case this commute is or if it can't be done.
1358 unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1360 assert(Case < 3 && "Unexpected case value!");
1362 // For each case we need to swap two pairs of bits in the final immediate.
1363 static const uint8_t SwapMasks[3][4] = {
1364 { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1365 { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1366 { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1369 uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1370 // Clear out the bits we are swapping.
1371 uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1372 SwapMasks[Case][2] | SwapMasks[Case][3]);
1373 // If the immediate had a bit of the pair set, then set the opposite bit.
1374 if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1375 if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1376 if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1377 if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1378 MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1381 // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1383 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1384 #define VPERM_CASES(Suffix) \
1385 case X86::VPERMI2##Suffix##128rr: case X86::VPERMT2##Suffix##128rr: \
1386 case X86::VPERMI2##Suffix##256rr: case X86::VPERMT2##Suffix##256rr: \
1387 case X86::VPERMI2##Suffix##rr: case X86::VPERMT2##Suffix##rr: \
1388 case X86::VPERMI2##Suffix##128rm: case X86::VPERMT2##Suffix##128rm: \
1389 case X86::VPERMI2##Suffix##256rm: case X86::VPERMT2##Suffix##256rm: \
1390 case X86::VPERMI2##Suffix##rm: case X86::VPERMT2##Suffix##rm: \
1391 case X86::VPERMI2##Suffix##128rrkz: case X86::VPERMT2##Suffix##128rrkz: \
1392 case X86::VPERMI2##Suffix##256rrkz: case X86::VPERMT2##Suffix##256rrkz: \
1393 case X86::VPERMI2##Suffix##rrkz: case X86::VPERMT2##Suffix##rrkz: \
1394 case X86::VPERMI2##Suffix##128rmkz: case X86::VPERMT2##Suffix##128rmkz: \
1395 case X86::VPERMI2##Suffix##256rmkz: case X86::VPERMT2##Suffix##256rmkz: \
1396 case X86::VPERMI2##Suffix##rmkz: case X86::VPERMT2##Suffix##rmkz:
1398 #define VPERM_CASES_BROADCAST(Suffix) \
1399 VPERM_CASES(Suffix) \
1400 case X86::VPERMI2##Suffix##128rmb: case X86::VPERMT2##Suffix##128rmb: \
1401 case X86::VPERMI2##Suffix##256rmb: case X86::VPERMT2##Suffix##256rmb: \
1402 case X86::VPERMI2##Suffix##rmb: case X86::VPERMT2##Suffix##rmb: \
1403 case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1404 case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1405 case X86::VPERMI2##Suffix##rmbkz: case X86::VPERMT2##Suffix##rmbkz:
1408 default: return false;
1410 VPERM_CASES_BROADCAST(D)
1411 VPERM_CASES_BROADCAST(PD)
1412 VPERM_CASES_BROADCAST(PS)
1413 VPERM_CASES_BROADCAST(Q)
1417 #undef VPERM_CASES_BROADCAST
1421 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1422 // from the I opcode to the T opcode and vice versa.
1423 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1424 #define VPERM_CASES(Orig, New) \
1425 case X86::Orig##128rr: return X86::New##128rr; \
1426 case X86::Orig##128rrkz: return X86::New##128rrkz; \
1427 case X86::Orig##128rm: return X86::New##128rm; \
1428 case X86::Orig##128rmkz: return X86::New##128rmkz; \
1429 case X86::Orig##256rr: return X86::New##256rr; \
1430 case X86::Orig##256rrkz: return X86::New##256rrkz; \
1431 case X86::Orig##256rm: return X86::New##256rm; \
1432 case X86::Orig##256rmkz: return X86::New##256rmkz; \
1433 case X86::Orig##rr: return X86::New##rr; \
1434 case X86::Orig##rrkz: return X86::New##rrkz; \
1435 case X86::Orig##rm: return X86::New##rm; \
1436 case X86::Orig##rmkz: return X86::New##rmkz;
1438 #define VPERM_CASES_BROADCAST(Orig, New) \
1439 VPERM_CASES(Orig, New) \
1440 case X86::Orig##128rmb: return X86::New##128rmb; \
1441 case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1442 case X86::Orig##256rmb: return X86::New##256rmb; \
1443 case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1444 case X86::Orig##rmb: return X86::New##rmb; \
1445 case X86::Orig##rmbkz: return X86::New##rmbkz;
1448 VPERM_CASES(VPERMI2B, VPERMT2B)
1449 VPERM_CASES_BROADCAST(VPERMI2D, VPERMT2D)
1450 VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
1451 VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
1452 VPERM_CASES_BROADCAST(VPERMI2Q, VPERMT2Q)
1453 VPERM_CASES(VPERMI2W, VPERMT2W)
1454 VPERM_CASES(VPERMT2B, VPERMI2B)
1455 VPERM_CASES_BROADCAST(VPERMT2D, VPERMI2D)
1456 VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
1457 VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
1458 VPERM_CASES_BROADCAST(VPERMT2Q, VPERMI2Q)
1459 VPERM_CASES(VPERMT2W, VPERMI2W)
1462 llvm_unreachable("Unreachable!");
1463 #undef VPERM_CASES_BROADCAST
1467 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
1469 unsigned OpIdx2) const {
1470 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
1472 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
1476 switch (MI.getOpcode()) {
1477 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1478 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1479 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1480 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1481 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1482 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1485 switch (MI.getOpcode()) {
1486 default: llvm_unreachable("Unreachable!");
1487 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1488 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1489 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1490 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1491 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1492 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1494 unsigned Amt = MI.getOperand(3).getImm();
1495 auto &WorkingMI = cloneIfNew(MI);
1496 WorkingMI.setDesc(get(Opc));
1497 WorkingMI.getOperand(3).setImm(Size - Amt);
1498 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1502 case X86::PFSUBRrr: {
1503 // PFSUB x, y: x = x - y
1504 // PFSUBR x, y: x = y - x
1506 (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
1507 auto &WorkingMI = cloneIfNew(MI);
1508 WorkingMI.setDesc(get(Opc));
1509 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1512 case X86::BLENDPDrri:
1513 case X86::BLENDPSrri:
1514 case X86::VBLENDPDrri:
1515 case X86::VBLENDPSrri:
1516 // If we're optimizing for size, try to use MOVSD/MOVSS.
1517 if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
1519 switch (MI.getOpcode()) {
1520 default: llvm_unreachable("Unreachable!");
1521 case X86::BLENDPDrri: Opc = X86::MOVSDrr; Mask = 0x03; break;
1522 case X86::BLENDPSrri: Opc = X86::MOVSSrr; Mask = 0x0F; break;
1523 case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
1524 case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
1526 if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
1527 auto &WorkingMI = cloneIfNew(MI);
1528 WorkingMI.setDesc(get(Opc));
1529 WorkingMI.RemoveOperand(3);
1530 return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
1536 case X86::PBLENDWrri:
1537 case X86::VBLENDPDYrri:
1538 case X86::VBLENDPSYrri:
1539 case X86::VPBLENDDrri:
1540 case X86::VPBLENDWrri:
1541 case X86::VPBLENDDYrri:
1542 case X86::VPBLENDWYrri:{
1544 switch (MI.getOpcode()) {
1545 default: llvm_unreachable("Unreachable!");
1546 case X86::BLENDPDrri: Mask = (int8_t)0x03; break;
1547 case X86::BLENDPSrri: Mask = (int8_t)0x0F; break;
1548 case X86::PBLENDWrri: Mask = (int8_t)0xFF; break;
1549 case X86::VBLENDPDrri: Mask = (int8_t)0x03; break;
1550 case X86::VBLENDPSrri: Mask = (int8_t)0x0F; break;
1551 case X86::VBLENDPDYrri: Mask = (int8_t)0x0F; break;
1552 case X86::VBLENDPSYrri: Mask = (int8_t)0xFF; break;
1553 case X86::VPBLENDDrri: Mask = (int8_t)0x0F; break;
1554 case X86::VPBLENDWrri: Mask = (int8_t)0xFF; break;
1555 case X86::VPBLENDDYrri: Mask = (int8_t)0xFF; break;
1556 case X86::VPBLENDWYrri: Mask = (int8_t)0xFF; break;
1558 // Only the least significant bits of Imm are used.
1559 // Using int8_t to ensure it will be sign extended to the int64_t that
1560 // setImm takes in order to match isel behavior.
1561 int8_t Imm = MI.getOperand(3).getImm() & Mask;
1562 auto &WorkingMI = cloneIfNew(MI);
1563 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
1564 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1567 case X86::INSERTPSrr:
1568 case X86::VINSERTPSrr:
1569 case X86::VINSERTPSZrr: {
1570 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
1571 unsigned ZMask = Imm & 15;
1572 unsigned DstIdx = (Imm >> 4) & 3;
1573 unsigned SrcIdx = (Imm >> 6) & 3;
1575 // We can commute insertps if we zero 2 of the elements, the insertion is
1576 // "inline" and we don't override the insertion with a zero.
1577 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
1578 countPopulation(ZMask) == 2) {
1579 unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
1580 assert(AltIdx < 4 && "Illegal insertion index");
1581 unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
1582 auto &WorkingMI = cloneIfNew(MI);
1583 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
1584 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1592 case X86::VMOVSSrr:{
1593 // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
1594 if (Subtarget.hasSSE41()) {
1596 switch (MI.getOpcode()) {
1597 default: llvm_unreachable("Unreachable!");
1598 case X86::MOVSDrr: Opc = X86::BLENDPDrri; Mask = 0x02; break;
1599 case X86::MOVSSrr: Opc = X86::BLENDPSrri; Mask = 0x0E; break;
1600 case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
1601 case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
1604 auto &WorkingMI = cloneIfNew(MI);
1605 WorkingMI.setDesc(get(Opc));
1606 WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
1607 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1611 // Convert to SHUFPD.
1612 assert(MI.getOpcode() == X86::MOVSDrr &&
1613 "Can only commute MOVSDrr without SSE4.1");
1615 auto &WorkingMI = cloneIfNew(MI);
1616 WorkingMI.setDesc(get(X86::SHUFPDrri));
1617 WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
1618 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1621 case X86::SHUFPDrri: {
1622 // Commute to MOVSD.
1623 assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
1624 auto &WorkingMI = cloneIfNew(MI);
1625 WorkingMI.setDesc(get(X86::MOVSDrr));
1626 WorkingMI.RemoveOperand(3);
1627 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1630 case X86::PCLMULQDQrr:
1631 case X86::VPCLMULQDQrr:
1632 case X86::VPCLMULQDQYrr:
1633 case X86::VPCLMULQDQZrr:
1634 case X86::VPCLMULQDQZ128rr:
1635 case X86::VPCLMULQDQZ256rr: {
1636 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
1637 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
1638 unsigned Imm = MI.getOperand(3).getImm();
1639 unsigned Src1Hi = Imm & 0x01;
1640 unsigned Src2Hi = Imm & 0x10;
1641 auto &WorkingMI = cloneIfNew(MI);
1642 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
1643 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1646 case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri:
1647 case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri:
1648 case X86::VPCMPBZrri: case X86::VPCMPUBZrri:
1649 case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri:
1650 case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri:
1651 case X86::VPCMPDZrri: case X86::VPCMPUDZrri:
1652 case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri:
1653 case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri:
1654 case X86::VPCMPQZrri: case X86::VPCMPUQZrri:
1655 case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri:
1656 case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri:
1657 case X86::VPCMPWZrri: case X86::VPCMPUWZrri:
1658 case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
1659 case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
1660 case X86::VPCMPBZrrik: case X86::VPCMPUBZrrik:
1661 case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
1662 case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
1663 case X86::VPCMPDZrrik: case X86::VPCMPUDZrrik:
1664 case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
1665 case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
1666 case X86::VPCMPQZrrik: case X86::VPCMPUQZrrik:
1667 case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
1668 case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
1669 case X86::VPCMPWZrrik: case X86::VPCMPUWZrrik: {
1670 // Flip comparison mode immediate (if necessary).
1671 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
1672 Imm = X86::getSwappedVPCMPImm(Imm);
1673 auto &WorkingMI = cloneIfNew(MI);
1674 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
1675 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1678 case X86::VPCOMBri: case X86::VPCOMUBri:
1679 case X86::VPCOMDri: case X86::VPCOMUDri:
1680 case X86::VPCOMQri: case X86::VPCOMUQri:
1681 case X86::VPCOMWri: case X86::VPCOMUWri: {
1682 // Flip comparison mode immediate (if necessary).
1683 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
1684 Imm = X86::getSwappedVPCOMImm(Imm);
1685 auto &WorkingMI = cloneIfNew(MI);
1686 WorkingMI.getOperand(3).setImm(Imm);
1687 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1690 case X86::VPERM2F128rr:
1691 case X86::VPERM2I128rr: {
1692 // Flip permute source immediate.
1693 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
1694 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
1695 int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
1696 auto &WorkingMI = cloneIfNew(MI);
1697 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
1698 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1701 case X86::MOVHLPSrr:
1702 case X86::UNPCKHPDrr:
1703 case X86::VMOVHLPSrr:
1704 case X86::VUNPCKHPDrr:
1705 case X86::VMOVHLPSZrr:
1706 case X86::VUNPCKHPDZ128rr: {
1707 assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
1709 unsigned Opc = MI.getOpcode();
1711 default: llvm_unreachable("Unreachable!");
1712 case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
1713 case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
1714 case X86::VMOVHLPSrr: Opc = X86::VUNPCKHPDrr; break;
1715 case X86::VUNPCKHPDrr: Opc = X86::VMOVHLPSrr; break;
1716 case X86::VMOVHLPSZrr: Opc = X86::VUNPCKHPDZ128rr; break;
1717 case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr; break;
1719 auto &WorkingMI = cloneIfNew(MI);
1720 WorkingMI.setDesc(get(Opc));
1721 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1724 case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr: {
1725 auto &WorkingMI = cloneIfNew(MI);
1726 unsigned OpNo = MI.getDesc().getNumOperands() - 1;
1727 X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
1728 WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
1729 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1732 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
1733 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
1734 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
1735 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
1736 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
1737 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
1738 case X86::VPTERNLOGDZrrik:
1739 case X86::VPTERNLOGDZ128rrik:
1740 case X86::VPTERNLOGDZ256rrik:
1741 case X86::VPTERNLOGQZrrik:
1742 case X86::VPTERNLOGQZ128rrik:
1743 case X86::VPTERNLOGQZ256rrik:
1744 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
1745 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1746 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1747 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
1748 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1749 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1750 case X86::VPTERNLOGDZ128rmbi:
1751 case X86::VPTERNLOGDZ256rmbi:
1752 case X86::VPTERNLOGDZrmbi:
1753 case X86::VPTERNLOGQZ128rmbi:
1754 case X86::VPTERNLOGQZ256rmbi:
1755 case X86::VPTERNLOGQZrmbi:
1756 case X86::VPTERNLOGDZ128rmbikz:
1757 case X86::VPTERNLOGDZ256rmbikz:
1758 case X86::VPTERNLOGDZrmbikz:
1759 case X86::VPTERNLOGQZ128rmbikz:
1760 case X86::VPTERNLOGQZ256rmbikz:
1761 case X86::VPTERNLOGQZrmbikz: {
1762 auto &WorkingMI = cloneIfNew(MI);
1763 commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
1764 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1768 if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
1769 unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
1770 auto &WorkingMI = cloneIfNew(MI);
1771 WorkingMI.setDesc(get(Opc));
1772 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1776 const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
1777 MI.getDesc().TSFlags);
1780 getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
1781 auto &WorkingMI = cloneIfNew(MI);
1782 WorkingMI.setDesc(get(Opc));
1783 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1787 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1793 X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
1794 unsigned &SrcOpIdx1,
1795 unsigned &SrcOpIdx2,
1796 bool IsIntrinsic) const {
1797 uint64_t TSFlags = MI.getDesc().TSFlags;
1799 unsigned FirstCommutableVecOp = 1;
1800 unsigned LastCommutableVecOp = 3;
1801 unsigned KMaskOp = -1U;
1802 if (X86II::isKMasked(TSFlags)) {
1803 // For k-zero-masked operations it is Ok to commute the first vector
1805 // For regular k-masked operations a conservative choice is done as the
1806 // elements of the first vector operand, for which the corresponding bit
1807 // in the k-mask operand is set to 0, are copied to the result of the
1809 // TODO/FIXME: The commute still may be legal if it is known that the
1810 // k-mask operand is set to either all ones or all zeroes.
1811 // It is also Ok to commute the 1st operand if all users of MI use only
1812 // the elements enabled by the k-mask operand. For example,
1813 // v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
1815 // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
1816 // // Ok, to commute v1 in FMADD213PSZrk.
1818 // The k-mask operand has index = 2 for masked and zero-masked operations.
1821 // The operand with index = 1 is used as a source for those elements for
1822 // which the corresponding bit in the k-mask is set to 0.
1823 if (X86II::isKMergeMasked(TSFlags))
1824 FirstCommutableVecOp = 3;
1826 LastCommutableVecOp++;
1827 } else if (IsIntrinsic) {
1828 // Commuting the first operand of an intrinsic instruction isn't possible
1829 // unless we can prove that only the lowest element of the result is used.
1830 FirstCommutableVecOp = 2;
1833 if (isMem(MI, LastCommutableVecOp))
1834 LastCommutableVecOp--;
1836 // Only the first RegOpsNum operands are commutable.
1837 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
1838 // that the operand is not specified/fixed.
1839 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
1840 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
1841 SrcOpIdx1 == KMaskOp))
1843 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
1844 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
1845 SrcOpIdx2 == KMaskOp))
1848 // Look for two different register operands assumed to be commutable
1849 // regardless of the FMA opcode. The FMA opcode is adjusted later.
1850 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
1851 SrcOpIdx2 == CommuteAnyOperandIndex) {
1852 unsigned CommutableOpIdx2 = SrcOpIdx2;
1854 // At least one of operands to be commuted is not specified and
1855 // this method is free to choose appropriate commutable operands.
1856 if (SrcOpIdx1 == SrcOpIdx2)
1857 // Both of operands are not fixed. By default set one of commutable
1858 // operands to the last register operand of the instruction.
1859 CommutableOpIdx2 = LastCommutableVecOp;
1860 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
1861 // Only one of operands is not fixed.
1862 CommutableOpIdx2 = SrcOpIdx1;
1864 // CommutableOpIdx2 is well defined now. Let's choose another commutable
1865 // operand and assign its index to CommutableOpIdx1.
1866 unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
1868 unsigned CommutableOpIdx1;
1869 for (CommutableOpIdx1 = LastCommutableVecOp;
1870 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
1871 // Just ignore and skip the k-mask operand.
1872 if (CommutableOpIdx1 == KMaskOp)
1875 // The commuted operands must have different registers.
1876 // Otherwise, the commute transformation does not change anything and
1878 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
1882 // No appropriate commutable operands were found.
1883 if (CommutableOpIdx1 < FirstCommutableVecOp)
1886 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
1887 // to return those values.
1888 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
1889 CommutableOpIdx1, CommutableOpIdx2))
1896 bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
1897 unsigned &SrcOpIdx2) const {
1898 const MCInstrDesc &Desc = MI.getDesc();
1899 if (!Desc.isCommutable())
1902 switch (MI.getOpcode()) {
1909 case X86::VCMPPDrri:
1910 case X86::VCMPPSrri:
1911 case X86::VCMPPDYrri:
1912 case X86::VCMPPSYrri:
1913 case X86::VCMPSDZrr:
1914 case X86::VCMPSSZrr:
1915 case X86::VCMPPDZrri:
1916 case X86::VCMPPSZrri:
1917 case X86::VCMPPDZ128rri:
1918 case X86::VCMPPSZ128rri:
1919 case X86::VCMPPDZ256rri:
1920 case X86::VCMPPSZ256rri:
1921 case X86::VCMPPDZrrik:
1922 case X86::VCMPPSZrrik:
1923 case X86::VCMPPDZ128rrik:
1924 case X86::VCMPPSZ128rrik:
1925 case X86::VCMPPDZ256rrik:
1926 case X86::VCMPPSZ256rrik: {
1927 unsigned OpOffset = X86II::isKMasked(Desc.TSFlags) ? 1 : 0;
1929 // Float comparison can be safely commuted for
1930 // Ordered/Unordered/Equal/NotEqual tests
1931 unsigned Imm = MI.getOperand(3 + OpOffset).getImm() & 0x7;
1934 case 0x03: // UNORDERED
1935 case 0x04: // NOT EQUAL
1936 case 0x07: // ORDERED
1937 // The indices of the commutable operands are 1 and 2 (or 2 and 3
1939 // Assign them to the returned operand indices here.
1940 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
1946 // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
1947 // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
1948 // AVX implies sse4.1.
1949 if (Subtarget.hasSSE41())
1950 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1952 case X86::SHUFPDrri:
1953 // We can commute this to MOVSD.
1954 if (MI.getOperand(3).getImm() == 0x02)
1955 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1957 case X86::MOVHLPSrr:
1958 case X86::UNPCKHPDrr:
1959 case X86::VMOVHLPSrr:
1960 case X86::VUNPCKHPDrr:
1961 case X86::VMOVHLPSZrr:
1962 case X86::VUNPCKHPDZ128rr:
1963 if (Subtarget.hasSSE2())
1964 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1966 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
1967 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
1968 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
1969 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
1970 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
1971 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
1972 case X86::VPTERNLOGDZrrik:
1973 case X86::VPTERNLOGDZ128rrik:
1974 case X86::VPTERNLOGDZ256rrik:
1975 case X86::VPTERNLOGQZrrik:
1976 case X86::VPTERNLOGQZ128rrik:
1977 case X86::VPTERNLOGQZ256rrik:
1978 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
1979 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1980 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1981 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
1982 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1983 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1984 case X86::VPTERNLOGDZ128rmbi:
1985 case X86::VPTERNLOGDZ256rmbi:
1986 case X86::VPTERNLOGDZrmbi:
1987 case X86::VPTERNLOGQZ128rmbi:
1988 case X86::VPTERNLOGQZ256rmbi:
1989 case X86::VPTERNLOGQZrmbi:
1990 case X86::VPTERNLOGDZ128rmbikz:
1991 case X86::VPTERNLOGDZ256rmbikz:
1992 case X86::VPTERNLOGDZrmbikz:
1993 case X86::VPTERNLOGQZ128rmbikz:
1994 case X86::VPTERNLOGQZ256rmbikz:
1995 case X86::VPTERNLOGQZrmbikz:
1996 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1997 case X86::VPMADD52HUQZ128r:
1998 case X86::VPMADD52HUQZ128rk:
1999 case X86::VPMADD52HUQZ128rkz:
2000 case X86::VPMADD52HUQZ256r:
2001 case X86::VPMADD52HUQZ256rk:
2002 case X86::VPMADD52HUQZ256rkz:
2003 case X86::VPMADD52HUQZr:
2004 case X86::VPMADD52HUQZrk:
2005 case X86::VPMADD52HUQZrkz:
2006 case X86::VPMADD52LUQZ128r:
2007 case X86::VPMADD52LUQZ128rk:
2008 case X86::VPMADD52LUQZ128rkz:
2009 case X86::VPMADD52LUQZ256r:
2010 case X86::VPMADD52LUQZ256rk:
2011 case X86::VPMADD52LUQZ256rkz:
2012 case X86::VPMADD52LUQZr:
2013 case X86::VPMADD52LUQZrk:
2014 case X86::VPMADD52LUQZrkz: {
2015 unsigned CommutableOpIdx1 = 2;
2016 unsigned CommutableOpIdx2 = 3;
2017 if (X86II::isKMasked(Desc.TSFlags)) {
2018 // Skip the mask register.
2022 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2023 CommutableOpIdx1, CommutableOpIdx2))
2025 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2026 !MI.getOperand(SrcOpIdx2).isReg())
2033 const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2034 MI.getDesc().TSFlags);
2036 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2037 FMA3Group->isIntrinsic());
2039 // Handled masked instructions since we need to skip over the mask input
2040 // and the preserved input.
2041 if (X86II::isKMasked(Desc.TSFlags)) {
2042 // First assume that the first input is the mask operand and skip past it.
2043 unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2044 unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2045 // Check if the first input is tied. If there isn't one then we only
2046 // need to skip the mask operand which we did above.
2047 if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2048 MCOI::TIED_TO) != -1)) {
2049 // If this is zero masking instruction with a tied operand, we need to
2050 // move the first index back to the first input since this must
2051 // be a 3 input instruction and we want the first two non-mask inputs.
2052 // Otherwise this is a 2 input instruction with a preserved input and
2053 // mask, so we need to move the indices to skip one more input.
2054 if (X86II::isKMergeMasked(Desc.TSFlags)) {
2062 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2063 CommutableOpIdx1, CommutableOpIdx2))
2066 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2067 !MI.getOperand(SrcOpIdx2).isReg())
2073 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2078 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
2079 switch (MI.getOpcode()) {
2080 default: return X86::COND_INVALID;
2082 return static_cast<X86::CondCode>(
2083 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2087 /// Return condition code of a SETCC opcode.
2088 X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
2089 switch (MI.getOpcode()) {
2090 default: return X86::COND_INVALID;
2091 case X86::SETCCr: case X86::SETCCm:
2092 return static_cast<X86::CondCode>(
2093 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2097 /// Return condition code of a CMov opcode.
2098 X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
2099 switch (MI.getOpcode()) {
2100 default: return X86::COND_INVALID;
2101 case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
2102 case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
2103 return static_cast<X86::CondCode>(
2104 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2108 /// Return the inverse of the specified condition,
2109 /// e.g. turning COND_E to COND_NE.
2110 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2112 default: llvm_unreachable("Illegal condition code!");
2113 case X86::COND_E: return X86::COND_NE;
2114 case X86::COND_NE: return X86::COND_E;
2115 case X86::COND_L: return X86::COND_GE;
2116 case X86::COND_LE: return X86::COND_G;
2117 case X86::COND_G: return X86::COND_LE;
2118 case X86::COND_GE: return X86::COND_L;
2119 case X86::COND_B: return X86::COND_AE;
2120 case X86::COND_BE: return X86::COND_A;
2121 case X86::COND_A: return X86::COND_BE;
2122 case X86::COND_AE: return X86::COND_B;
2123 case X86::COND_S: return X86::COND_NS;
2124 case X86::COND_NS: return X86::COND_S;
2125 case X86::COND_P: return X86::COND_NP;
2126 case X86::COND_NP: return X86::COND_P;
2127 case X86::COND_O: return X86::COND_NO;
2128 case X86::COND_NO: return X86::COND_O;
2129 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP;
2130 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2134 /// Assuming the flags are set by MI(a,b), return the condition code if we
2135 /// modify the instructions such that flags are set by MI(b,a).
2136 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2138 default: return X86::COND_INVALID;
2139 case X86::COND_E: return X86::COND_E;
2140 case X86::COND_NE: return X86::COND_NE;
2141 case X86::COND_L: return X86::COND_G;
2142 case X86::COND_LE: return X86::COND_GE;
2143 case X86::COND_G: return X86::COND_L;
2144 case X86::COND_GE: return X86::COND_LE;
2145 case X86::COND_B: return X86::COND_A;
2146 case X86::COND_BE: return X86::COND_AE;
2147 case X86::COND_A: return X86::COND_B;
2148 case X86::COND_AE: return X86::COND_BE;
2152 std::pair<X86::CondCode, bool>
2153 X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2154 X86::CondCode CC = X86::COND_INVALID;
2155 bool NeedSwap = false;
2156 switch (Predicate) {
2158 // Floating-point Predicates
2159 case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
2160 case CmpInst::FCMP_OLT: NeedSwap = true; LLVM_FALLTHROUGH;
2161 case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
2162 case CmpInst::FCMP_OLE: NeedSwap = true; LLVM_FALLTHROUGH;
2163 case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;
2164 case CmpInst::FCMP_UGT: NeedSwap = true; LLVM_FALLTHROUGH;
2165 case CmpInst::FCMP_ULT: CC = X86::COND_B; break;
2166 case CmpInst::FCMP_UGE: NeedSwap = true; LLVM_FALLTHROUGH;
2167 case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;
2168 case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;
2169 case CmpInst::FCMP_UNO: CC = X86::COND_P; break;
2170 case CmpInst::FCMP_ORD: CC = X86::COND_NP; break;
2171 case CmpInst::FCMP_OEQ: LLVM_FALLTHROUGH;
2172 case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2174 // Integer Predicates
2175 case CmpInst::ICMP_EQ: CC = X86::COND_E; break;
2176 case CmpInst::ICMP_NE: CC = X86::COND_NE; break;
2177 case CmpInst::ICMP_UGT: CC = X86::COND_A; break;
2178 case CmpInst::ICMP_UGE: CC = X86::COND_AE; break;
2179 case CmpInst::ICMP_ULT: CC = X86::COND_B; break;
2180 case CmpInst::ICMP_ULE: CC = X86::COND_BE; break;
2181 case CmpInst::ICMP_SGT: CC = X86::COND_G; break;
2182 case CmpInst::ICMP_SGE: CC = X86::COND_GE; break;
2183 case CmpInst::ICMP_SLT: CC = X86::COND_L; break;
2184 case CmpInst::ICMP_SLE: CC = X86::COND_LE; break;
2187 return std::make_pair(CC, NeedSwap);
2190 /// Return a setcc opcode based on whether it has memory operand.
2191 unsigned X86::getSETOpc(bool HasMemoryOperand) {
2192 return HasMemoryOperand ? X86::SETCCr : X86::SETCCm;
2195 /// Return a cmov opcode for the given register size in bytes, and operand type.
2196 unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
2198 default: llvm_unreachable("Illegal register size!");
2199 case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
2200 case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
2201 case 8: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV64rr;
2205 /// Get the VPCMP immediate for the given condition.
2206 unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2208 default: llvm_unreachable("Unexpected SETCC condition");
2209 case ISD::SETNE: return 4;
2210 case ISD::SETEQ: return 0;
2212 case ISD::SETLT: return 1;
2214 case ISD::SETGT: return 6;
2216 case ISD::SETGE: return 5;
2218 case ISD::SETLE: return 2;
2222 /// Get the VPCMP immediate if the opcodes are swapped.
2223 unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2225 default: llvm_unreachable("Unreachable!");
2226 case 0x01: Imm = 0x06; break; // LT -> NLE
2227 case 0x02: Imm = 0x05; break; // LE -> NLT
2228 case 0x05: Imm = 0x02; break; // NLT -> LE
2229 case 0x06: Imm = 0x01; break; // NLE -> LT
2240 /// Get the VPCOM immediate if the opcodes are swapped.
2241 unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2243 default: llvm_unreachable("Unreachable!");
2244 case 0x00: Imm = 0x02; break; // LT -> GT
2245 case 0x01: Imm = 0x03; break; // LE -> GE
2246 case 0x02: Imm = 0x00; break; // GT -> LT
2247 case 0x03: Imm = 0x01; break; // GE -> LE
2258 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
2259 if (!MI.isTerminator()) return false;
2261 // Conditional branch is a special case.
2262 if (MI.isBranch() && !MI.isBarrier())
2264 if (!MI.isPredicable())
2266 return !isPredicated(MI);
2269 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2270 switch (MI.getOpcode()) {
2271 case X86::TCRETURNdi:
2272 case X86::TCRETURNri:
2273 case X86::TCRETURNmi:
2274 case X86::TCRETURNdi64:
2275 case X86::TCRETURNri64:
2276 case X86::TCRETURNmi64:
2283 bool X86InstrInfo::canMakeTailCallConditional(
2284 SmallVectorImpl<MachineOperand> &BranchCond,
2285 const MachineInstr &TailCall) const {
2286 if (TailCall.getOpcode() != X86::TCRETURNdi &&
2287 TailCall.getOpcode() != X86::TCRETURNdi64) {
2288 // Only direct calls can be done with a conditional branch.
2292 const MachineFunction *MF = TailCall.getParent()->getParent();
2293 if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2294 // Conditional tail calls confuse the Win64 unwinder.
2298 assert(BranchCond.size() == 1);
2299 if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2300 // Can't make a conditional tail call with this condition.
2304 const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2305 if (X86FI->getTCReturnAddrDelta() != 0 ||
2306 TailCall.getOperand(1).getImm() != 0) {
2307 // A conditional tail call cannot do any stack adjustment.
2314 void X86InstrInfo::replaceBranchWithTailCall(
2315 MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2316 const MachineInstr &TailCall) const {
2317 assert(canMakeTailCallConditional(BranchCond, TailCall));
2319 MachineBasicBlock::iterator I = MBB.end();
2320 while (I != MBB.begin()) {
2322 if (I->isDebugInstr())
2325 assert(0 && "Can't find the branch to replace!");
2327 X86::CondCode CC = X86::getCondFromBranch(*I);
2328 assert(BranchCond.size() == 1);
2329 if (CC != BranchCond[0].getImm())
2335 unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
2336 : X86::TCRETURNdi64cc;
2338 auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2339 MIB->addOperand(TailCall.getOperand(0)); // Destination.
2340 MIB.addImm(0); // Stack offset (not used).
2341 MIB->addOperand(BranchCond[0]); // Condition.
2342 MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2344 // Add implicit uses and defs of all live regs potentially clobbered by the
2345 // call. This way they still appear live across the call.
2346 LivePhysRegs LiveRegs(getRegisterInfo());
2347 LiveRegs.addLiveOuts(MBB);
2348 SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
2349 LiveRegs.stepForward(*MIB, Clobbers);
2350 for (const auto &C : Clobbers) {
2351 MIB.addReg(C.first, RegState::Implicit);
2352 MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2355 I->eraseFromParent();
2358 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
2359 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
2360 // fallthrough MBB cannot be identified.
2361 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
2362 MachineBasicBlock *TBB) {
2363 // Look for non-EHPad successors other than TBB. If we find exactly one, it
2364 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
2365 // and fallthrough MBB. If we find more than one, we cannot identify the
2366 // fallthrough MBB and should return nullptr.
2367 MachineBasicBlock *FallthroughBB = nullptr;
2368 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
2369 if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
2371 // Return a nullptr if we found more than one fallthrough successor.
2372 if (FallthroughBB && FallthroughBB != TBB)
2374 FallthroughBB = *SI;
2376 return FallthroughBB;
2379 bool X86InstrInfo::AnalyzeBranchImpl(
2380 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
2381 SmallVectorImpl<MachineOperand> &Cond,
2382 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
2384 // Start from the bottom of the block and work up, examining the
2385 // terminator instructions.
2386 MachineBasicBlock::iterator I = MBB.end();
2387 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2388 while (I != MBB.begin()) {
2390 if (I->isDebugInstr())
2393 // Working from the bottom, when we see a non-terminator instruction, we're
2395 if (!isUnpredicatedTerminator(*I))
2398 // A terminator that isn't a branch can't easily be handled by this
2403 // Handle unconditional branches.
2404 if (I->getOpcode() == X86::JMP_1) {
2408 TBB = I->getOperand(0).getMBB();
2412 // If the block has any instructions after a JMP, delete them.
2413 while (std::next(I) != MBB.end())
2414 std::next(I)->eraseFromParent();
2419 // Delete the JMP if it's equivalent to a fall-through.
2420 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2422 I->eraseFromParent();
2424 UnCondBrIter = MBB.end();
2428 // TBB is used to indicate the unconditional destination.
2429 TBB = I->getOperand(0).getMBB();
2433 // Handle conditional branches.
2434 X86::CondCode BranchCode = X86::getCondFromBranch(*I);
2435 if (BranchCode == X86::COND_INVALID)
2436 return true; // Can't handle indirect branch.
2438 // In practice we should never have an undef eflags operand, if we do
2439 // abort here as we are not prepared to preserve the flag.
2440 if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
2443 // Working from the bottom, handle the first conditional branch.
2445 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2446 if (AllowModify && UnCondBrIter != MBB.end() &&
2447 MBB.isLayoutSuccessor(TargetBB)) {
2448 // If we can modify the code and it ends in something like:
2456 // Then we can change this to:
2463 // Which is a bit more efficient.
2464 // We conditionally jump to the fall-through block.
2465 BranchCode = GetOppositeBranchCondition(BranchCode);
2466 MachineBasicBlock::iterator OldInst = I;
2468 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
2469 .addMBB(UnCondBrIter->getOperand(0).getMBB())
2470 .addImm(BranchCode);
2471 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
2474 OldInst->eraseFromParent();
2475 UnCondBrIter->eraseFromParent();
2477 // Restart the analysis.
2478 UnCondBrIter = MBB.end();
2484 TBB = I->getOperand(0).getMBB();
2485 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2486 CondBranches.push_back(&*I);
2490 // Handle subsequent conditional branches. Only handle the case where all
2491 // conditional branches branch to the same destination and their condition
2492 // opcodes fit one of the special multi-branch idioms.
2493 assert(Cond.size() == 1);
2496 // If the conditions are the same, we can leave them alone.
2497 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2498 auto NewTBB = I->getOperand(0).getMBB();
2499 if (OldBranchCode == BranchCode && TBB == NewTBB)
2502 // If they differ, see if they fit one of the known patterns. Theoretically,
2503 // we could handle more patterns here, but we shouldn't expect to see them
2504 // if instruction selection has done a reasonable job.
2505 if (TBB == NewTBB &&
2506 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
2507 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
2508 BranchCode = X86::COND_NE_OR_P;
2509 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
2510 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
2511 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
2514 // X86::COND_E_AND_NP usually has two different branch destinations.
2522 // Here this condition branches to B2 only if NP && E. It has another
2531 // Similarly it branches to B2 only if E && NP. That is why this condition
2532 // is named with COND_E_AND_NP.
2533 BranchCode = X86::COND_E_AND_NP;
2537 // Update the MachineOperand.
2538 Cond[0].setImm(BranchCode);
2539 CondBranches.push_back(&*I);
2545 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
2546 MachineBasicBlock *&TBB,
2547 MachineBasicBlock *&FBB,
2548 SmallVectorImpl<MachineOperand> &Cond,
2549 bool AllowModify) const {
2550 SmallVector<MachineInstr *, 4> CondBranches;
2551 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
2554 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
2555 MachineBranchPredicate &MBP,
2556 bool AllowModify) const {
2557 using namespace std::placeholders;
2559 SmallVector<MachineOperand, 4> Cond;
2560 SmallVector<MachineInstr *, 4> CondBranches;
2561 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
2565 if (Cond.size() != 1)
2568 assert(MBP.TrueDest && "expected!");
2571 MBP.FalseDest = MBB.getNextNode();
2573 const TargetRegisterInfo *TRI = &getRegisterInfo();
2575 MachineInstr *ConditionDef = nullptr;
2576 bool SingleUseCondition = true;
2578 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
2579 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
2584 if (I->readsRegister(X86::EFLAGS, TRI))
2585 SingleUseCondition = false;
2591 if (SingleUseCondition) {
2592 for (auto *Succ : MBB.successors())
2593 if (Succ->isLiveIn(X86::EFLAGS))
2594 SingleUseCondition = false;
2597 MBP.ConditionDef = ConditionDef;
2598 MBP.SingleUseCondition = SingleUseCondition;
2600 // Currently we only recognize the simple pattern:
2605 const unsigned TestOpcode =
2606 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
2608 if (ConditionDef->getOpcode() == TestOpcode &&
2609 ConditionDef->getNumOperands() == 3 &&
2610 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
2611 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
2612 MBP.LHS = ConditionDef->getOperand(0);
2613 MBP.RHS = MachineOperand::CreateImm(0);
2614 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
2615 ? MachineBranchPredicate::PRED_NE
2616 : MachineBranchPredicate::PRED_EQ;
2623 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
2624 int *BytesRemoved) const {
2625 assert(!BytesRemoved && "code size not handled");
2627 MachineBasicBlock::iterator I = MBB.end();
2630 while (I != MBB.begin()) {
2632 if (I->isDebugInstr())
2634 if (I->getOpcode() != X86::JMP_1 &&
2635 X86::getCondFromBranch(*I) == X86::COND_INVALID)
2637 // Remove the branch.
2638 I->eraseFromParent();
2646 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
2647 MachineBasicBlock *TBB,
2648 MachineBasicBlock *FBB,
2649 ArrayRef<MachineOperand> Cond,
2651 int *BytesAdded) const {
2652 // Shouldn't be a fall through.
2653 assert(TBB && "insertBranch must not be told to insert a fallthrough");
2654 assert((Cond.size() == 1 || Cond.size() == 0) &&
2655 "X86 branch conditions have one component!");
2656 assert(!BytesAdded && "code size not handled");
2659 // Unconditional branch?
2660 assert(!FBB && "Unconditional branch with multiple successors!");
2661 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
2665 // If FBB is null, it is implied to be a fall-through block.
2666 bool FallThru = FBB == nullptr;
2668 // Conditional branch.
2670 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2672 case X86::COND_NE_OR_P:
2673 // Synthesize NE_OR_P with two branches.
2674 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
2676 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
2679 case X86::COND_E_AND_NP:
2680 // Use the next block of MBB as FBB if it is null.
2681 if (FBB == nullptr) {
2682 FBB = getFallThroughMBB(&MBB, TBB);
2683 assert(FBB && "MBB cannot be the last block in function when the false "
2684 "body is a fall-through.");
2686 // Synthesize COND_E_AND_NP with two branches.
2687 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
2689 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
2693 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
2698 // Two-way Conditional branch. Insert the second branch.
2699 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
2706 canInsertSelect(const MachineBasicBlock &MBB,
2707 ArrayRef<MachineOperand> Cond,
2708 unsigned TrueReg, unsigned FalseReg,
2709 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2710 // Not all subtargets have cmov instructions.
2711 if (!Subtarget.hasCMov())
2713 if (Cond.size() != 1)
2715 // We cannot do the composite conditions, at least not in SSA form.
2716 if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
2719 // Check register classes.
2720 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2721 const TargetRegisterClass *RC =
2722 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2726 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2727 if (X86::GR16RegClass.hasSubClassEq(RC) ||
2728 X86::GR32RegClass.hasSubClassEq(RC) ||
2729 X86::GR64RegClass.hasSubClassEq(RC)) {
2730 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2731 // Bridge. Probably Ivy Bridge as well.
2738 // Can't do vectors.
2742 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
2743 MachineBasicBlock::iterator I,
2744 const DebugLoc &DL, unsigned DstReg,
2745 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
2746 unsigned FalseReg) const {
2747 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2748 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
2749 const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
2750 assert(Cond.size() == 1 && "Invalid Cond array");
2751 unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
2752 false /*HasMemoryOperand*/);
2753 BuildMI(MBB, I, DL, get(Opc), DstReg)
2756 .addImm(Cond[0].getImm());
2759 /// Test if the given register is a physical h register.
2760 static bool isHReg(unsigned Reg) {
2761 return X86::GR8_ABCD_HRegClass.contains(Reg);
2764 // Try and copy between VR128/VR64 and GR64 registers.
2765 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2766 const X86Subtarget &Subtarget) {
2767 bool HasAVX = Subtarget.hasAVX();
2768 bool HasAVX512 = Subtarget.hasAVX512();
2770 // SrcReg(MaskReg) -> DestReg(GR64)
2771 // SrcReg(MaskReg) -> DestReg(GR32)
2773 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2774 if (X86::VK16RegClass.contains(SrcReg)) {
2775 if (X86::GR64RegClass.contains(DestReg)) {
2776 assert(Subtarget.hasBWI());
2777 return X86::KMOVQrk;
2779 if (X86::GR32RegClass.contains(DestReg))
2780 return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
2783 // SrcReg(GR64) -> DestReg(MaskReg)
2784 // SrcReg(GR32) -> DestReg(MaskReg)
2786 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2787 if (X86::VK16RegClass.contains(DestReg)) {
2788 if (X86::GR64RegClass.contains(SrcReg)) {
2789 assert(Subtarget.hasBWI());
2790 return X86::KMOVQkr;
2792 if (X86::GR32RegClass.contains(SrcReg))
2793 return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
2797 // SrcReg(VR128) -> DestReg(GR64)
2798 // SrcReg(VR64) -> DestReg(GR64)
2799 // SrcReg(GR64) -> DestReg(VR128)
2800 // SrcReg(GR64) -> DestReg(VR64)
2802 if (X86::GR64RegClass.contains(DestReg)) {
2803 if (X86::VR128XRegClass.contains(SrcReg))
2804 // Copy from a VR128 register to a GR64 register.
2805 return HasAVX512 ? X86::VMOVPQIto64Zrr :
2806 HasAVX ? X86::VMOVPQIto64rr :
2808 if (X86::VR64RegClass.contains(SrcReg))
2809 // Copy from a VR64 register to a GR64 register.
2810 return X86::MMX_MOVD64from64rr;
2811 } else if (X86::GR64RegClass.contains(SrcReg)) {
2812 // Copy from a GR64 register to a VR128 register.
2813 if (X86::VR128XRegClass.contains(DestReg))
2814 return HasAVX512 ? X86::VMOV64toPQIZrr :
2815 HasAVX ? X86::VMOV64toPQIrr :
2817 // Copy from a GR64 register to a VR64 register.
2818 if (X86::VR64RegClass.contains(DestReg))
2819 return X86::MMX_MOVD64to64rr;
2822 // SrcReg(VR128) -> DestReg(GR32)
2823 // SrcReg(GR32) -> DestReg(VR128)
2825 if (X86::GR32RegClass.contains(DestReg) &&
2826 X86::VR128XRegClass.contains(SrcReg))
2827 // Copy from a VR128 register to a GR32 register.
2828 return HasAVX512 ? X86::VMOVPDI2DIZrr :
2829 HasAVX ? X86::VMOVPDI2DIrr :
2832 if (X86::VR128XRegClass.contains(DestReg) &&
2833 X86::GR32RegClass.contains(SrcReg))
2834 // Copy from a VR128 register to a VR128 register.
2835 return HasAVX512 ? X86::VMOVDI2PDIZrr :
2836 HasAVX ? X86::VMOVDI2PDIrr :
2841 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2842 MachineBasicBlock::iterator MI,
2843 const DebugLoc &DL, unsigned DestReg,
2844 unsigned SrcReg, bool KillSrc) const {
2845 // First deal with the normal symmetric copies.
2846 bool HasAVX = Subtarget.hasAVX();
2847 bool HasVLX = Subtarget.hasVLX();
2849 if (X86::GR64RegClass.contains(DestReg, SrcReg))
2851 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2853 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2855 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2856 // Copying to or from a physical H register on x86-64 requires a NOREX
2857 // move. Otherwise use a normal move.
2858 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2859 Subtarget.is64Bit()) {
2860 Opc = X86::MOV8rr_NOREX;
2861 // Both operands must be encodable without an REX prefix.
2862 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2863 "8-bit H register can not be copied outside GR8_NOREX");
2867 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2868 Opc = X86::MMX_MOVQ64rr;
2869 else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
2871 Opc = X86::VMOVAPSZ128rr;
2872 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2873 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2875 // If this an extended register and we don't have VLX we need to use a
2877 Opc = X86::VMOVAPSZrr;
2878 const TargetRegisterInfo *TRI = &getRegisterInfo();
2879 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
2880 &X86::VR512RegClass);
2881 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
2882 &X86::VR512RegClass);
2884 } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
2886 Opc = X86::VMOVAPSZ256rr;
2887 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2888 Opc = X86::VMOVAPSYrr;
2890 // If this an extended register and we don't have VLX we need to use a
2892 Opc = X86::VMOVAPSZrr;
2893 const TargetRegisterInfo *TRI = &getRegisterInfo();
2894 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
2895 &X86::VR512RegClass);
2896 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
2897 &X86::VR512RegClass);
2899 } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
2900 Opc = X86::VMOVAPSZrr;
2901 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2902 else if (X86::VK16RegClass.contains(DestReg, SrcReg))
2903 Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
2905 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
2908 BuildMI(MBB, MI, DL, get(Opc), DestReg)
2909 .addReg(SrcReg, getKillRegState(KillSrc));
2913 if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
2914 // FIXME: We use a fatal error here because historically LLVM has tried
2915 // lower some of these physreg copies and we want to ensure we get
2916 // reasonable bug reports if someone encounters a case no other testing
2917 // found. This path should be removed after the LLVM 7 release.
2918 report_fatal_error("Unable to copy EFLAGS physical register!");
2921 LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
2922 << RI.getName(DestReg) << '\n');
2923 report_fatal_error("Cannot emit physreg copy instruction");
2926 bool X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI,
2927 const MachineOperand *&Src,
2928 const MachineOperand *&Dest) const {
2929 if (MI.isMoveReg()) {
2930 Dest = &MI.getOperand(0);
2931 Src = &MI.getOperand(1);
2937 static unsigned getLoadStoreRegOpcode(unsigned Reg,
2938 const TargetRegisterClass *RC,
2939 bool isStackAligned,
2940 const X86Subtarget &STI,
2942 bool HasAVX = STI.hasAVX();
2943 bool HasAVX512 = STI.hasAVX512();
2944 bool HasVLX = STI.hasVLX();
2946 switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
2948 llvm_unreachable("Unknown spill size");
2950 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2952 // Copying to or from a physical H register on x86-64 requires a NOREX
2953 // move. Otherwise use a normal move.
2954 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2955 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2956 return load ? X86::MOV8rm : X86::MOV8mr;
2958 if (X86::VK16RegClass.hasSubClassEq(RC))
2959 return load ? X86::KMOVWkm : X86::KMOVWmk;
2960 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2961 return load ? X86::MOV16rm : X86::MOV16mr;
2963 if (X86::GR32RegClass.hasSubClassEq(RC))
2964 return load ? X86::MOV32rm : X86::MOV32mr;
2965 if (X86::FR32XRegClass.hasSubClassEq(RC))
2967 (HasAVX512 ? X86::VMOVSSZrm_alt :
2968 HasAVX ? X86::VMOVSSrm_alt :
2970 (HasAVX512 ? X86::VMOVSSZmr :
2971 HasAVX ? X86::VMOVSSmr :
2973 if (X86::RFP32RegClass.hasSubClassEq(RC))
2974 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2975 if (X86::VK32RegClass.hasSubClassEq(RC)) {
2976 assert(STI.hasBWI() && "KMOVD requires BWI");
2977 return load ? X86::KMOVDkm : X86::KMOVDmk;
2979 // All of these mask pair classes have the same spill size, the same kind
2980 // of kmov instructions can be used with all of them.
2981 if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
2982 X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
2983 X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
2984 X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
2985 X86::VK16PAIRRegClass.hasSubClassEq(RC))
2986 return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
2987 llvm_unreachable("Unknown 4-byte regclass");
2989 if (X86::GR64RegClass.hasSubClassEq(RC))
2990 return load ? X86::MOV64rm : X86::MOV64mr;
2991 if (X86::FR64XRegClass.hasSubClassEq(RC))
2993 (HasAVX512 ? X86::VMOVSDZrm_alt :
2994 HasAVX ? X86::VMOVSDrm_alt :
2996 (HasAVX512 ? X86::VMOVSDZmr :
2997 HasAVX ? X86::VMOVSDmr :
2999 if (X86::VR64RegClass.hasSubClassEq(RC))
3000 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3001 if (X86::RFP64RegClass.hasSubClassEq(RC))
3002 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3003 if (X86::VK64RegClass.hasSubClassEq(RC)) {
3004 assert(STI.hasBWI() && "KMOVQ requires BWI");
3005 return load ? X86::KMOVQkm : X86::KMOVQmk;
3007 llvm_unreachable("Unknown 8-byte regclass");
3009 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3010 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3012 if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3013 // If stack is realigned we can use aligned stores.
3016 (HasVLX ? X86::VMOVAPSZ128rm :
3017 HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3018 HasAVX ? X86::VMOVAPSrm :
3020 (HasVLX ? X86::VMOVAPSZ128mr :
3021 HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3022 HasAVX ? X86::VMOVAPSmr :
3026 (HasVLX ? X86::VMOVUPSZ128rm :
3027 HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3028 HasAVX ? X86::VMOVUPSrm :
3030 (HasVLX ? X86::VMOVUPSZ128mr :
3031 HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3032 HasAVX ? X86::VMOVUPSmr :
3035 if (X86::BNDRRegClass.hasSubClassEq(RC)) {
3037 return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
3039 return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
3041 llvm_unreachable("Unknown 16-byte regclass");
3044 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3045 // If stack is realigned we can use aligned stores.
3048 (HasVLX ? X86::VMOVAPSZ256rm :
3049 HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3051 (HasVLX ? X86::VMOVAPSZ256mr :
3052 HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3056 (HasVLX ? X86::VMOVUPSZ256rm :
3057 HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3059 (HasVLX ? X86::VMOVUPSZ256mr :
3060 HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3063 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3064 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
3066 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3068 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3072 bool X86InstrInfo::getMemOperandWithOffset(
3073 const MachineInstr &MemOp, const MachineOperand *&BaseOp, int64_t &Offset,
3074 const TargetRegisterInfo *TRI) const {
3075 const MCInstrDesc &Desc = MemOp.getDesc();
3076 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3077 if (MemRefBegin < 0)
3080 MemRefBegin += X86II::getOperandBias(Desc);
3082 BaseOp = &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3083 if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3086 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3089 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3093 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3095 // Displacement can be symbolic
3096 if (!DispMO.isImm())
3099 Offset = DispMO.getImm();
3101 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
3102 "operands of type register.");
3106 static unsigned getStoreRegOpcode(unsigned SrcReg,
3107 const TargetRegisterClass *RC,
3108 bool isStackAligned,
3109 const X86Subtarget &STI) {
3110 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3114 static unsigned getLoadRegOpcode(unsigned DestReg,
3115 const TargetRegisterClass *RC,
3116 bool isStackAligned,
3117 const X86Subtarget &STI) {
3118 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3121 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3122 MachineBasicBlock::iterator MI,
3123 unsigned SrcReg, bool isKill, int FrameIdx,
3124 const TargetRegisterClass *RC,
3125 const TargetRegisterInfo *TRI) const {
3126 const MachineFunction &MF = *MBB.getParent();
3127 assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
3128 "Stack slot too small for store");
3129 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3131 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3132 RI.canRealignStack(MF);
3133 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3134 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3135 .addReg(SrcReg, getKillRegState(isKill));
3138 void X86InstrInfo::storeRegToAddr(
3139 MachineFunction &MF, unsigned SrcReg, bool isKill,
3140 SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC,
3141 ArrayRef<MachineMemOperand *> MMOs,
3142 SmallVectorImpl<MachineInstr *> &NewMIs) const {
3143 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
3144 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
3145 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
3146 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3148 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3149 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3151 MIB.addReg(SrcReg, getKillRegState(isKill));
3152 MIB.setMemRefs(MMOs);
3153 NewMIs.push_back(MIB);
3157 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3158 MachineBasicBlock::iterator MI,
3159 unsigned DestReg, int FrameIdx,
3160 const TargetRegisterClass *RC,
3161 const TargetRegisterInfo *TRI) const {
3162 const MachineFunction &MF = *MBB.getParent();
3163 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3165 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3166 RI.canRealignStack(MF);
3167 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3168 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
3171 void X86InstrInfo::loadRegFromAddr(
3172 MachineFunction &MF, unsigned DestReg,
3173 SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC,
3174 ArrayRef<MachineMemOperand *> MMOs,
3175 SmallVectorImpl<MachineInstr *> &NewMIs) const {
3176 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
3177 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
3178 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
3179 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3181 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3182 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3184 MIB.setMemRefs(MMOs);
3185 NewMIs.push_back(MIB);
3188 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
3189 unsigned &SrcReg2, int &CmpMask,
3190 int &CmpValue) const {
3191 switch (MI.getOpcode()) {
3193 case X86::CMP64ri32:
3200 SrcReg = MI.getOperand(0).getReg();
3202 if (MI.getOperand(1).isImm()) {
3204 CmpValue = MI.getOperand(1).getImm();
3206 CmpMask = CmpValue = 0;
3209 // A SUB can be used to perform comparison.
3214 SrcReg = MI.getOperand(1).getReg();
3223 SrcReg = MI.getOperand(1).getReg();
3224 SrcReg2 = MI.getOperand(2).getReg();
3228 case X86::SUB64ri32:
3235 SrcReg = MI.getOperand(1).getReg();
3237 if (MI.getOperand(2).isImm()) {
3239 CmpValue = MI.getOperand(2).getImm();
3241 CmpMask = CmpValue = 0;
3248 SrcReg = MI.getOperand(0).getReg();
3249 SrcReg2 = MI.getOperand(1).getReg();
3257 SrcReg = MI.getOperand(0).getReg();
3258 if (MI.getOperand(1).getReg() != SrcReg)
3260 // Compare against zero.
3269 /// Check whether the first instruction, whose only
3270 /// purpose is to update flags, can be made redundant.
3271 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3272 /// This function can be extended later on.
3273 /// SrcReg, SrcRegs: register operands for FlagI.
3274 /// ImmValue: immediate for FlagI if it takes an immediate.
3275 inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
3276 unsigned SrcReg, unsigned SrcReg2,
3277 int ImmMask, int ImmValue,
3278 const MachineInstr &OI) {
3279 if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
3280 (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
3281 (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
3282 (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
3283 ((OI.getOperand(1).getReg() == SrcReg &&
3284 OI.getOperand(2).getReg() == SrcReg2) ||
3285 (OI.getOperand(1).getReg() == SrcReg2 &&
3286 OI.getOperand(2).getReg() == SrcReg)))
3290 ((FlagI.getOpcode() == X86::CMP64ri32 &&
3291 OI.getOpcode() == X86::SUB64ri32) ||
3292 (FlagI.getOpcode() == X86::CMP64ri8 &&
3293 OI.getOpcode() == X86::SUB64ri8) ||
3294 (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
3295 (FlagI.getOpcode() == X86::CMP32ri8 &&
3296 OI.getOpcode() == X86::SUB32ri8) ||
3297 (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
3298 (FlagI.getOpcode() == X86::CMP16ri8 &&
3299 OI.getOpcode() == X86::SUB16ri8) ||
3300 (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
3301 OI.getOperand(1).getReg() == SrcReg &&
3302 OI.getOperand(2).getImm() == ImmValue)
3307 /// Check whether the definition can be converted
3308 /// to remove a comparison against zero.
3309 inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag) {
3312 switch (MI.getOpcode()) {
3313 default: return false;
3315 // The shift instructions only modify ZF if their shift count is non-zero.
3316 // N.B.: The processor truncates the shift count depending on the encoding.
3317 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
3318 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
3319 return getTruncatedShiftCount(MI, 2) != 0;
3321 // Some left shift instructions can be turned into LEA instructions but only
3322 // if their flags aren't used. Avoid transforming such instructions.
3323 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
3324 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3325 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3329 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3330 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3331 return getTruncatedShiftCount(MI, 3) != 0;
3333 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3334 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
3335 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
3336 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
3337 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
3338 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
3339 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3340 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
3341 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
3342 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
3343 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
3344 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
3345 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3346 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
3347 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
3348 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
3349 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
3350 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3351 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
3352 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
3353 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
3354 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
3355 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
3356 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
3357 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
3358 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
3359 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
3360 case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
3361 case X86::ADC32ri8: case X86::ADC16ri: case X86::ADC16ri8:
3362 case X86::ADC8ri: case X86::ADC64rr: case X86::ADC32rr:
3363 case X86::ADC16rr: case X86::ADC8rr: case X86::ADC64rm:
3364 case X86::ADC32rm: case X86::ADC16rm: case X86::ADC8rm:
3365 case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
3366 case X86::SBB32ri8: case X86::SBB16ri: case X86::SBB16ri8:
3367 case X86::SBB8ri: case X86::SBB64rr: case X86::SBB32rr:
3368 case X86::SBB16rr: case X86::SBB8rr: case X86::SBB64rm:
3369 case X86::SBB32rm: case X86::SBB16rm: case X86::SBB8rm:
3370 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
3371 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
3372 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
3373 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
3374 case X86::ANDN32rr: case X86::ANDN32rm:
3375 case X86::ANDN64rr: case X86::ANDN64rm:
3376 case X86::BLSI32rr: case X86::BLSI32rm:
3377 case X86::BLSI64rr: case X86::BLSI64rm:
3378 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3379 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3380 case X86::BLSR32rr: case X86::BLSR32rm:
3381 case X86::BLSR64rr: case X86::BLSR64rm:
3382 case X86::BZHI32rr: case X86::BZHI32rm:
3383 case X86::BZHI64rr: case X86::BZHI64rm:
3384 case X86::LZCNT16rr: case X86::LZCNT16rm:
3385 case X86::LZCNT32rr: case X86::LZCNT32rm:
3386 case X86::LZCNT64rr: case X86::LZCNT64rm:
3387 case X86::POPCNT16rr:case X86::POPCNT16rm:
3388 case X86::POPCNT32rr:case X86::POPCNT32rm:
3389 case X86::POPCNT64rr:case X86::POPCNT64rm:
3390 case X86::TZCNT16rr: case X86::TZCNT16rm:
3391 case X86::TZCNT32rr: case X86::TZCNT32rm:
3392 case X86::TZCNT64rr: case X86::TZCNT64rm:
3393 case X86::BLCFILL32rr: case X86::BLCFILL32rm:
3394 case X86::BLCFILL64rr: case X86::BLCFILL64rm:
3395 case X86::BLCI32rr: case X86::BLCI32rm:
3396 case X86::BLCI64rr: case X86::BLCI64rm:
3397 case X86::BLCIC32rr: case X86::BLCIC32rm:
3398 case X86::BLCIC64rr: case X86::BLCIC64rm:
3399 case X86::BLCMSK32rr: case X86::BLCMSK32rm:
3400 case X86::BLCMSK64rr: case X86::BLCMSK64rm:
3401 case X86::BLCS32rr: case X86::BLCS32rm:
3402 case X86::BLCS64rr: case X86::BLCS64rm:
3403 case X86::BLSFILL32rr: case X86::BLSFILL32rm:
3404 case X86::BLSFILL64rr: case X86::BLSFILL64rm:
3405 case X86::BLSIC32rr: case X86::BLSIC32rm:
3406 case X86::BLSIC64rr: case X86::BLSIC64rm:
3407 case X86::T1MSKC32rr: case X86::T1MSKC32rm:
3408 case X86::T1MSKC64rr: case X86::T1MSKC64rm:
3409 case X86::TZMSK32rr: case X86::TZMSK32rm:
3410 case X86::TZMSK64rr: case X86::TZMSK64rm:
3412 case X86::BEXTR32rr: case X86::BEXTR64rr:
3413 case X86::BEXTR32rm: case X86::BEXTR64rm:
3414 case X86::BEXTRI32ri: case X86::BEXTRI32mi:
3415 case X86::BEXTRI64ri: case X86::BEXTRI64mi:
3416 // BEXTR doesn't update the sign flag so we can't use it.
3422 /// Check whether the use can be converted to remove a comparison against zero.
3423 static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
3424 switch (MI.getOpcode()) {
3425 default: return X86::COND_INVALID;
3430 return X86::COND_AE;
3431 case X86::LZCNT16rr:
3432 case X86::LZCNT32rr:
3433 case X86::LZCNT64rr:
3435 case X86::POPCNT16rr:
3436 case X86::POPCNT32rr:
3437 case X86::POPCNT64rr:
3439 case X86::TZCNT16rr:
3440 case X86::TZCNT32rr:
3441 case X86::TZCNT64rr:
3452 return X86::COND_AE;
3455 case X86::BLSMSK32rr:
3456 case X86::BLSMSK64rr:
3458 // TODO: TBM instructions.
3462 /// Check if there exists an earlier instruction that
3463 /// operates on the same source operands and sets flags in the same way as
3464 /// Compare; remove Compare if possible.
3465 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
3466 unsigned SrcReg2, int CmpMask,
3468 const MachineRegisterInfo *MRI) const {
3469 // Check whether we can replace SUB with CMP.
3470 switch (CmpInstr.getOpcode()) {
3472 case X86::SUB64ri32:
3487 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
3489 // There is no use of the destination register, we can replace SUB with CMP.
3490 unsigned NewOpcode = 0;
3491 switch (CmpInstr.getOpcode()) {
3492 default: llvm_unreachable("Unreachable!");
3493 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
3494 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
3495 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
3496 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
3497 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
3498 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
3499 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
3500 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
3501 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3502 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
3503 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
3504 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
3505 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
3506 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
3507 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
3509 CmpInstr.setDesc(get(NewOpcode));
3510 CmpInstr.RemoveOperand(0);
3511 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3512 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3513 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3518 // Get the unique definition of SrcReg.
3519 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3520 if (!MI) return false;
3522 // CmpInstr is the first instruction of the BB.
3523 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3525 // If we are comparing against zero, check whether we can use MI to update
3526 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3527 bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
3528 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
3531 // If we have a use of the source register between the def and our compare
3532 // instruction we can eliminate the compare iff the use sets EFLAGS in the
3534 bool ShouldUpdateCC = false;
3535 bool NoSignFlag = false;
3536 X86::CondCode NewCC = X86::COND_INVALID;
3537 if (IsCmpZero && !isDefConvertible(*MI, NoSignFlag)) {
3538 // Scan forward from the use until we hit the use we're looking for or the
3539 // compare instruction.
3540 for (MachineBasicBlock::iterator J = MI;; ++J) {
3541 // Do we have a convertible instruction?
3542 NewCC = isUseDefConvertible(*J);
3543 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3544 J->getOperand(1).getReg() == SrcReg) {
3545 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
3546 ShouldUpdateCC = true; // Update CC later on.
3547 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3548 // with the new def.
3559 // We are searching for an earlier instruction that can make CmpInstr
3560 // redundant and that instruction will be saved in Sub.
3561 MachineInstr *Sub = nullptr;
3562 const TargetRegisterInfo *TRI = &getRegisterInfo();
3564 // We iterate backward, starting from the instruction before CmpInstr and
3565 // stop when reaching the definition of a source register or done with the BB.
3566 // RI points to the instruction before CmpInstr.
3567 // If the definition is in this basic block, RE points to the definition;
3568 // otherwise, RE is the rend of the basic block.
3569 MachineBasicBlock::reverse_iterator
3570 RI = ++I.getReverse(),
3571 RE = CmpInstr.getParent() == MI->getParent()
3572 ? Def.getReverse() /* points to MI */
3573 : CmpInstr.getParent()->rend();
3574 MachineInstr *Movr0Inst = nullptr;
3575 for (; RI != RE; ++RI) {
3576 MachineInstr &Instr = *RI;
3577 // Check whether CmpInstr can be made redundant by the current instruction.
3578 if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
3584 if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
3585 Instr.readsRegister(X86::EFLAGS, TRI)) {
3586 // This instruction modifies or uses EFLAGS.
3588 // MOV32r0 etc. are implemented with xor which clobbers condition code.
3589 // They are safe to move up, if the definition to EFLAGS is dead and
3590 // earlier instructions do not read or write EFLAGS.
3591 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
3592 Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
3597 // We can't remove CmpInstr.
3602 // Return false if no candidates exist.
3603 if (!IsCmpZero && !Sub)
3606 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3607 Sub->getOperand(2).getReg() == SrcReg);
3609 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3610 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3611 // If we are done with the basic block, we need to check whether EFLAGS is
3613 bool IsSafe = false;
3614 SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
3615 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
3616 for (++I; I != E; ++I) {
3617 const MachineInstr &Instr = *I;
3618 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3619 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3620 // We should check the usage if this instruction uses and updates EFLAGS.
3621 if (!UseEFLAGS && ModifyEFLAGS) {
3622 // It is safe to remove CmpInstr if EFLAGS is updated again.
3626 if (!UseEFLAGS && !ModifyEFLAGS)
3629 // EFLAGS is used by this instruction.
3630 X86::CondCode OldCC = X86::COND_INVALID;
3631 if (IsCmpZero || IsSwapped) {
3632 // We decode the condition code from opcode.
3633 if (Instr.isBranch())
3634 OldCC = X86::getCondFromBranch(Instr);
3636 OldCC = X86::getCondFromSETCC(Instr);
3637 if (OldCC == X86::COND_INVALID)
3638 OldCC = X86::getCondFromCMov(Instr);
3640 if (OldCC == X86::COND_INVALID) return false;
3642 X86::CondCode ReplacementCC = X86::COND_INVALID;
3646 case X86::COND_A: case X86::COND_AE:
3647 case X86::COND_B: case X86::COND_BE:
3648 case X86::COND_G: case X86::COND_GE:
3649 case X86::COND_L: case X86::COND_LE:
3650 case X86::COND_O: case X86::COND_NO:
3651 // CF and OF are used, we can't perform this optimization.
3653 case X86::COND_S: case X86::COND_NS:
3654 // If SF is used, but the instruction doesn't update the SF, then we
3655 // can't do the optimization.
3661 // If we're updating the condition code check if we have to reverse the
3668 ReplacementCC = NewCC;
3671 ReplacementCC = GetOppositeBranchCondition(NewCC);
3674 } else if (IsSwapped) {
3675 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3676 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3677 // We swap the condition code and synthesize the new opcode.
3678 ReplacementCC = getSwappedCondition(OldCC);
3679 if (ReplacementCC == X86::COND_INVALID) return false;
3682 if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
3683 // Push the MachineInstr to OpsToUpdate.
3684 // If it is safe to remove CmpInstr, the condition code of these
3685 // instructions will be modified.
3686 OpsToUpdate.push_back(std::make_pair(&*I, ReplacementCC));
3688 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3689 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3695 // If EFLAGS is not killed nor re-defined, we should check whether it is
3696 // live-out. If it is live-out, do not optimize.
3697 if ((IsCmpZero || IsSwapped) && !IsSafe) {
3698 MachineBasicBlock *MBB = CmpInstr.getParent();
3699 for (MachineBasicBlock *Successor : MBB->successors())
3700 if (Successor->isLiveIn(X86::EFLAGS))
3704 // The instruction to be updated is either Sub or MI.
3705 Sub = IsCmpZero ? MI : Sub;
3706 // Move Movr0Inst to the appropriate place before Sub.
3708 // Look backwards until we find a def that doesn't use the current EFLAGS.
3710 MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
3711 InsertE = Sub->getParent()->rend();
3712 for (; InsertI != InsertE; ++InsertI) {
3713 MachineInstr *Instr = &*InsertI;
3714 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3715 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3716 Sub->getParent()->remove(Movr0Inst);
3717 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3722 if (InsertI == InsertE)
3726 // Make sure Sub instruction defines EFLAGS and mark the def live.
3727 MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS);
3728 assert(FlagDef && "Unable to locate a def EFLAGS operand");
3729 FlagDef->setIsDead(false);
3731 CmpInstr.eraseFromParent();
3733 // Modify the condition code of instructions in OpsToUpdate.
3734 for (auto &Op : OpsToUpdate) {
3735 Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
3741 /// Try to remove the load by folding it to a register
3742 /// operand at the use. We fold the load instructions if load defines a virtual
3743 /// register, the virtual register is used once in the same BB, and the
3744 /// instructions in-between do not load or store, and have no side effects.
3745 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
3746 const MachineRegisterInfo *MRI,
3747 unsigned &FoldAsLoadDefReg,
3748 MachineInstr *&DefMI) const {
3749 // Check whether we can move DefMI here.
3750 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3752 bool SawStore = false;
3753 if (!DefMI->isSafeToMove(nullptr, SawStore))
3756 // Collect information about virtual register operands of MI.
3757 SmallVector<unsigned, 1> SrcOperandIds;
3758 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
3759 MachineOperand &MO = MI.getOperand(i);
3762 unsigned Reg = MO.getReg();
3763 if (Reg != FoldAsLoadDefReg)
3765 // Do not fold if we have a subreg use or a def.
3766 if (MO.getSubReg() || MO.isDef())
3768 SrcOperandIds.push_back(i);
3770 if (SrcOperandIds.empty())
3773 // Check whether we can fold the def into SrcOperandId.
3774 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
3775 FoldAsLoadDefReg = 0;
3782 /// Expand a single-def pseudo instruction to a two-addr
3783 /// instruction with two undef reads of the register being defined.
3784 /// This is used for mapping:
3787 /// %xmm4 = PXORrr undef %xmm4, undef %xmm4
3789 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
3790 const MCInstrDesc &Desc) {
3791 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3792 unsigned Reg = MIB->getOperand(0).getReg();
3795 // MachineInstr::addOperand() will insert explicit operands before any
3796 // implicit operands.
3797 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3798 // But we don't trust that.
3799 assert(MIB->getOperand(1).getReg() == Reg &&
3800 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3804 /// Expand a single-def pseudo instruction to a two-addr
3805 /// instruction with two %k0 reads.
3806 /// This is used for mapping:
3809 /// %k4 = KXNORrr %k0, %k0
3810 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
3811 const MCInstrDesc &Desc, unsigned Reg) {
3812 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3814 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3818 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
3820 MachineBasicBlock &MBB = *MIB->getParent();
3821 DebugLoc DL = MIB->getDebugLoc();
3822 unsigned Reg = MIB->getOperand(0).getReg();
3825 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
3826 .addReg(Reg, RegState::Undef)
3827 .addReg(Reg, RegState::Undef);
3829 // Turn the pseudo into an INC or DEC.
3830 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
3836 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
3837 const TargetInstrInfo &TII,
3838 const X86Subtarget &Subtarget) {
3839 MachineBasicBlock &MBB = *MIB->getParent();
3840 DebugLoc DL = MIB->getDebugLoc();
3841 int64_t Imm = MIB->getOperand(1).getImm();
3842 assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
3843 MachineBasicBlock::iterator I = MIB.getInstr();
3845 int StackAdjustment;
3847 if (Subtarget.is64Bit()) {
3848 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
3849 MIB->getOpcode() == X86::MOV32ImmSExti8);
3851 // Can't use push/pop lowering if the function might write to the red zone.
3852 X86MachineFunctionInfo *X86FI =
3853 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
3854 if (X86FI->getUsesRedZone()) {
3855 MIB->setDesc(TII.get(MIB->getOpcode() ==
3856 X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
3860 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
3861 // widen the register if necessary.
3862 StackAdjustment = 8;
3863 BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
3864 MIB->setDesc(TII.get(X86::POP64r));
3866 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
3868 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
3869 StackAdjustment = 4;
3870 BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
3871 MIB->setDesc(TII.get(X86::POP32r));
3874 // Build CFI if necessary.
3875 MachineFunction &MF = *MBB.getParent();
3876 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
3877 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
3878 bool NeedsDwarfCFI =
3880 (MF.getMMI().hasDebugInfo() || MF.getFunction().needsUnwindTableEntry());
3881 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
3883 TFL->BuildCFI(MBB, I, DL,
3884 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
3885 TFL->BuildCFI(MBB, std::next(I), DL,
3886 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
3892 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
3893 // code sequence is needed for other targets.
3894 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
3895 const TargetInstrInfo &TII) {
3896 MachineBasicBlock &MBB = *MIB->getParent();
3897 DebugLoc DL = MIB->getDebugLoc();
3898 unsigned Reg = MIB->getOperand(0).getReg();
3899 const GlobalValue *GV =
3900 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
3901 auto Flags = MachineMemOperand::MOLoad |
3902 MachineMemOperand::MODereferenceable |
3903 MachineMemOperand::MOInvariant;
3904 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
3905 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
3906 MachineBasicBlock::iterator I = MIB.getInstr();
3908 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
3909 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
3910 .addMemOperand(MMO);
3911 MIB->setDebugLoc(DL);
3912 MIB->setDesc(TII.get(X86::MOV64rm));
3913 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
3916 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
3917 MachineBasicBlock &MBB = *MIB->getParent();
3918 MachineFunction &MF = *MBB.getParent();
3919 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
3920 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
3922 MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
3923 MIB->setDesc(TII.get(XorOp));
3924 MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
3928 // This is used to handle spills for 128/256-bit registers when we have AVX512,
3929 // but not VLX. If it uses an extended register we need to use an instruction
3930 // that loads the lower 128/256-bit, but is available with only AVX512F.
3931 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
3932 const TargetRegisterInfo *TRI,
3933 const MCInstrDesc &LoadDesc,
3934 const MCInstrDesc &BroadcastDesc,
3936 unsigned DestReg = MIB->getOperand(0).getReg();
3937 // Check if DestReg is XMM16-31 or YMM16-31.
3938 if (TRI->getEncodingValue(DestReg) < 16) {
3939 // We can use a normal VEX encoded load.
3940 MIB->setDesc(LoadDesc);
3942 // Use a 128/256-bit VBROADCAST instruction.
3943 MIB->setDesc(BroadcastDesc);
3944 // Change the destination to a 512-bit register.
3945 DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
3946 MIB->getOperand(0).setReg(DestReg);
3951 // This is used to handle spills for 128/256-bit registers when we have AVX512,
3952 // but not VLX. If it uses an extended register we need to use an instruction
3953 // that stores the lower 128/256-bit, but is available with only AVX512F.
3954 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
3955 const TargetRegisterInfo *TRI,
3956 const MCInstrDesc &StoreDesc,
3957 const MCInstrDesc &ExtractDesc,
3959 unsigned SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
3960 // Check if DestReg is XMM16-31 or YMM16-31.
3961 if (TRI->getEncodingValue(SrcReg) < 16) {
3962 // We can use a normal VEX encoded store.
3963 MIB->setDesc(StoreDesc);
3965 // Use a VEXTRACTF instruction.
3966 MIB->setDesc(ExtractDesc);
3967 // Change the destination to a 512-bit register.
3968 SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
3969 MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
3970 MIB.addImm(0x0); // Append immediate to extract from the lower bits.
3976 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
3978 int64_t ShiftAmt = MIB->getOperand(2).getImm();
3979 // Temporarily remove the immediate so we can add another source register.
3980 MIB->RemoveOperand(2);
3981 // Add the register. Don't copy the kill flag if there is one.
3982 MIB.addReg(MIB->getOperand(1).getReg(),
3983 getUndefRegState(MIB->getOperand(1).isUndef()));
3984 // Add back the immediate.
3985 MIB.addImm(ShiftAmt);
3989 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
3990 bool HasAVX = Subtarget.hasAVX();
3991 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
3992 switch (MI.getOpcode()) {
3994 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
3996 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
3998 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
3999 case X86::MOV32ImmSExti8:
4000 case X86::MOV64ImmSExti8:
4001 return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4003 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4004 case X86::SETB_C16r:
4005 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4006 case X86::SETB_C32r:
4007 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4008 case X86::SETB_C64r:
4009 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4011 return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
4015 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4016 case X86::AVX_SET0: {
4017 assert(HasAVX && "AVX not supported");
4018 const TargetRegisterInfo *TRI = &getRegisterInfo();
4019 unsigned SrcReg = MIB->getOperand(0).getReg();
4020 unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4021 MIB->getOperand(0).setReg(XReg);
4022 Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4023 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4026 case X86::AVX512_128_SET0:
4027 case X86::AVX512_FsFLD0SS:
4028 case X86::AVX512_FsFLD0SD: {
4029 bool HasVLX = Subtarget.hasVLX();
4030 unsigned SrcReg = MIB->getOperand(0).getReg();
4031 const TargetRegisterInfo *TRI = &getRegisterInfo();
4032 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4033 return Expand2AddrUndef(MIB,
4034 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4035 // Extended register without VLX. Use a larger XOR.
4037 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4038 MIB->getOperand(0).setReg(SrcReg);
4039 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4041 case X86::AVX512_256_SET0:
4042 case X86::AVX512_512_SET0: {
4043 bool HasVLX = Subtarget.hasVLX();
4044 unsigned SrcReg = MIB->getOperand(0).getReg();
4045 const TargetRegisterInfo *TRI = &getRegisterInfo();
4046 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4047 unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4048 MIB->getOperand(0).setReg(XReg);
4049 Expand2AddrUndef(MIB,
4050 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4051 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4054 if (MI.getOpcode() == X86::AVX512_256_SET0) {
4055 // No VLX so we must reference a zmm.
4057 TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4058 MIB->getOperand(0).setReg(ZReg);
4060 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4062 case X86::V_SETALLONES:
4063 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4064 case X86::AVX2_SETALLONES:
4065 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4066 case X86::AVX1_SETALLONES: {
4067 unsigned Reg = MIB->getOperand(0).getReg();
4068 // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4069 MIB->setDesc(get(X86::VCMPPSYrri));
4070 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4073 case X86::AVX512_512_SETALLONES: {
4074 unsigned Reg = MIB->getOperand(0).getReg();
4075 MIB->setDesc(get(X86::VPTERNLOGDZrri));
4076 // VPTERNLOGD needs 3 register inputs and an immediate.
4077 // 0xff will return 1s for any input.
4078 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4079 .addReg(Reg, RegState::Undef).addImm(0xff);
4082 case X86::AVX512_512_SEXT_MASK_32:
4083 case X86::AVX512_512_SEXT_MASK_64: {
4084 unsigned Reg = MIB->getOperand(0).getReg();
4085 unsigned MaskReg = MIB->getOperand(1).getReg();
4086 unsigned MaskState = getRegState(MIB->getOperand(1));
4087 unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4088 X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4089 MI.RemoveOperand(1);
4090 MIB->setDesc(get(Opc));
4091 // VPTERNLOG needs 3 register inputs and an immediate.
4092 // 0xff will return 1s for any input.
4093 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4094 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4097 case X86::VMOVAPSZ128rm_NOVLX:
4098 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4099 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4100 case X86::VMOVUPSZ128rm_NOVLX:
4101 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4102 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4103 case X86::VMOVAPSZ256rm_NOVLX:
4104 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4105 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4106 case X86::VMOVUPSZ256rm_NOVLX:
4107 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4108 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4109 case X86::VMOVAPSZ128mr_NOVLX:
4110 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4111 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4112 case X86::VMOVUPSZ128mr_NOVLX:
4113 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4114 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4115 case X86::VMOVAPSZ256mr_NOVLX:
4116 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4117 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4118 case X86::VMOVUPSZ256mr_NOVLX:
4119 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4120 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4121 case X86::MOV32ri64: {
4122 unsigned Reg = MIB->getOperand(0).getReg();
4123 unsigned Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4124 MI.setDesc(get(X86::MOV32ri));
4125 MIB->getOperand(0).setReg(Reg32);
4126 MIB.addReg(Reg, RegState::ImplicitDefine);
4130 // KNL does not recognize dependency-breaking idioms for mask registers,
4131 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4132 // Using %k0 as the undef input register is a performance heuristic based
4133 // on the assumption that %k0 is used less frequently than the other mask
4134 // registers, since it is not usable as a write mask.
4135 // FIXME: A more advanced approach would be to choose the best input mask
4136 // register based on context.
4137 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4138 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4139 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4140 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4141 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4142 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4143 case TargetOpcode::LOAD_STACK_GUARD:
4144 expandLoadStackGuard(MIB, *this);
4148 return expandXorFP(MIB, *this);
4149 case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4150 case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4151 case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4152 case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4153 case X86::ADD8rr_DB: MIB->setDesc(get(X86::OR8rr)); break;
4154 case X86::ADD16rr_DB: MIB->setDesc(get(X86::OR16rr)); break;
4155 case X86::ADD32rr_DB: MIB->setDesc(get(X86::OR32rr)); break;
4156 case X86::ADD64rr_DB: MIB->setDesc(get(X86::OR64rr)); break;
4157 case X86::ADD8ri_DB: MIB->setDesc(get(X86::OR8ri)); break;
4158 case X86::ADD16ri_DB: MIB->setDesc(get(X86::OR16ri)); break;
4159 case X86::ADD32ri_DB: MIB->setDesc(get(X86::OR32ri)); break;
4160 case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4161 case X86::ADD16ri8_DB: MIB->setDesc(get(X86::OR16ri8)); break;
4162 case X86::ADD32ri8_DB: MIB->setDesc(get(X86::OR32ri8)); break;
4163 case X86::ADD64ri8_DB: MIB->setDesc(get(X86::OR64ri8)); break;
4168 /// Return true for all instructions that only update
4169 /// the first 32 or 64-bits of the destination register and leave the rest
4170 /// unmodified. This can be used to avoid folding loads if the instructions
4171 /// only update part of the destination register, and the non-updated part is
4172 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4173 /// instructions breaks the partial register dependency and it can improve
4174 /// performance. e.g.:
4176 /// movss (%rdi), %xmm0
4177 /// cvtss2sd %xmm0, %xmm0
4180 /// cvtss2sd (%rdi), %xmm0
4182 /// FIXME: This should be turned into a TSFlags.
4184 static bool hasPartialRegUpdate(unsigned Opcode,
4185 const X86Subtarget &Subtarget,
4186 bool ForLoadFold = false) {
4188 case X86::CVTSI2SSrr:
4189 case X86::CVTSI2SSrm:
4190 case X86::CVTSI642SSrr:
4191 case X86::CVTSI642SSrm:
4192 case X86::CVTSI2SDrr:
4193 case X86::CVTSI2SDrm:
4194 case X86::CVTSI642SDrr:
4195 case X86::CVTSI642SDrm:
4196 // Load folding won't effect the undef register update since the input is
4198 return !ForLoadFold;
4199 case X86::CVTSD2SSrr:
4200 case X86::CVTSD2SSrm:
4201 case X86::CVTSS2SDrr:
4202 case X86::CVTSS2SDrm:
4209 case X86::RCPSSr_Int:
4210 case X86::RCPSSm_Int:
4217 case X86::RSQRTSSr_Int:
4218 case X86::RSQRTSSm_Int:
4221 case X86::SQRTSSr_Int:
4222 case X86::SQRTSSm_Int:
4225 case X86::SQRTSDr_Int:
4226 case X86::SQRTSDm_Int:
4229 case X86::POPCNT32rm:
4230 case X86::POPCNT32rr:
4231 case X86::POPCNT64rm:
4232 case X86::POPCNT64rr:
4233 return Subtarget.hasPOPCNTFalseDeps();
4234 case X86::LZCNT32rm:
4235 case X86::LZCNT32rr:
4236 case X86::LZCNT64rm:
4237 case X86::LZCNT64rr:
4238 case X86::TZCNT32rm:
4239 case X86::TZCNT32rr:
4240 case X86::TZCNT64rm:
4241 case X86::TZCNT64rr:
4242 return Subtarget.hasLZCNTFalseDeps();
4248 /// Inform the BreakFalseDeps pass how many idle
4249 /// instructions we would like before a partial register update.
4250 unsigned X86InstrInfo::getPartialRegUpdateClearance(
4251 const MachineInstr &MI, unsigned OpNum,
4252 const TargetRegisterInfo *TRI) const {
4253 if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
4256 // If MI is marked as reading Reg, the partial register update is wanted.
4257 const MachineOperand &MO = MI.getOperand(0);
4258 unsigned Reg = MO.getReg();
4259 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4260 if (MO.readsReg() || MI.readsVirtualRegister(Reg))
4263 if (MI.readsRegister(Reg, TRI))
4267 // If any instructions in the clearance range are reading Reg, insert a
4268 // dependency breaking instruction, which is inexpensive and is likely to
4269 // be hidden in other instruction's cycles.
4270 return PartialRegUpdateClearance;
4273 // Return true for any instruction the copies the high bits of the first source
4274 // operand into the unused high bits of the destination operand.
4275 static bool hasUndefRegUpdate(unsigned Opcode, bool ForLoadFold = false) {
4277 case X86::VCVTSI2SSrr:
4278 case X86::VCVTSI2SSrm:
4279 case X86::VCVTSI2SSrr_Int:
4280 case X86::VCVTSI2SSrm_Int:
4281 case X86::VCVTSI642SSrr:
4282 case X86::VCVTSI642SSrm:
4283 case X86::VCVTSI642SSrr_Int:
4284 case X86::VCVTSI642SSrm_Int:
4285 case X86::VCVTSI2SDrr:
4286 case X86::VCVTSI2SDrm:
4287 case X86::VCVTSI2SDrr_Int:
4288 case X86::VCVTSI2SDrm_Int:
4289 case X86::VCVTSI642SDrr:
4290 case X86::VCVTSI642SDrm:
4291 case X86::VCVTSI642SDrr_Int:
4292 case X86::VCVTSI642SDrm_Int:
4294 case X86::VCVTSI2SSZrr:
4295 case X86::VCVTSI2SSZrm:
4296 case X86::VCVTSI2SSZrr_Int:
4297 case X86::VCVTSI2SSZrrb_Int:
4298 case X86::VCVTSI2SSZrm_Int:
4299 case X86::VCVTSI642SSZrr:
4300 case X86::VCVTSI642SSZrm:
4301 case X86::VCVTSI642SSZrr_Int:
4302 case X86::VCVTSI642SSZrrb_Int:
4303 case X86::VCVTSI642SSZrm_Int:
4304 case X86::VCVTSI2SDZrr:
4305 case X86::VCVTSI2SDZrm:
4306 case X86::VCVTSI2SDZrr_Int:
4307 case X86::VCVTSI2SDZrm_Int:
4308 case X86::VCVTSI642SDZrr:
4309 case X86::VCVTSI642SDZrm:
4310 case X86::VCVTSI642SDZrr_Int:
4311 case X86::VCVTSI642SDZrrb_Int:
4312 case X86::VCVTSI642SDZrm_Int:
4313 case X86::VCVTUSI2SSZrr:
4314 case X86::VCVTUSI2SSZrm:
4315 case X86::VCVTUSI2SSZrr_Int:
4316 case X86::VCVTUSI2SSZrrb_Int:
4317 case X86::VCVTUSI2SSZrm_Int:
4318 case X86::VCVTUSI642SSZrr:
4319 case X86::VCVTUSI642SSZrm:
4320 case X86::VCVTUSI642SSZrr_Int:
4321 case X86::VCVTUSI642SSZrrb_Int:
4322 case X86::VCVTUSI642SSZrm_Int:
4323 case X86::VCVTUSI2SDZrr:
4324 case X86::VCVTUSI2SDZrm:
4325 case X86::VCVTUSI2SDZrr_Int:
4326 case X86::VCVTUSI2SDZrm_Int:
4327 case X86::VCVTUSI642SDZrr:
4328 case X86::VCVTUSI642SDZrm:
4329 case X86::VCVTUSI642SDZrr_Int:
4330 case X86::VCVTUSI642SDZrrb_Int:
4331 case X86::VCVTUSI642SDZrm_Int:
4332 // Load folding won't effect the undef register update since the input is
4334 return !ForLoadFold;
4335 case X86::VCVTSD2SSrr:
4336 case X86::VCVTSD2SSrm:
4337 case X86::VCVTSD2SSrr_Int:
4338 case X86::VCVTSD2SSrm_Int:
4339 case X86::VCVTSS2SDrr:
4340 case X86::VCVTSS2SDrm:
4341 case X86::VCVTSS2SDrr_Int:
4342 case X86::VCVTSS2SDrm_Int:
4344 case X86::VRCPSSr_Int:
4346 case X86::VRCPSSm_Int:
4347 case X86::VROUNDSDr:
4348 case X86::VROUNDSDm:
4349 case X86::VROUNDSDr_Int:
4350 case X86::VROUNDSDm_Int:
4351 case X86::VROUNDSSr:
4352 case X86::VROUNDSSm:
4353 case X86::VROUNDSSr_Int:
4354 case X86::VROUNDSSm_Int:
4355 case X86::VRSQRTSSr:
4356 case X86::VRSQRTSSr_Int:
4357 case X86::VRSQRTSSm:
4358 case X86::VRSQRTSSm_Int:
4360 case X86::VSQRTSSr_Int:
4362 case X86::VSQRTSSm_Int:
4364 case X86::VSQRTSDr_Int:
4366 case X86::VSQRTSDm_Int:
4368 case X86::VCVTSD2SSZrr:
4369 case X86::VCVTSD2SSZrr_Int:
4370 case X86::VCVTSD2SSZrrb_Int:
4371 case X86::VCVTSD2SSZrm:
4372 case X86::VCVTSD2SSZrm_Int:
4373 case X86::VCVTSS2SDZrr:
4374 case X86::VCVTSS2SDZrr_Int:
4375 case X86::VCVTSS2SDZrrb_Int:
4376 case X86::VCVTSS2SDZrm:
4377 case X86::VCVTSS2SDZrm_Int:
4378 case X86::VGETEXPSDZr:
4379 case X86::VGETEXPSDZrb:
4380 case X86::VGETEXPSDZm:
4381 case X86::VGETEXPSSZr:
4382 case X86::VGETEXPSSZrb:
4383 case X86::VGETEXPSSZm:
4384 case X86::VGETMANTSDZrri:
4385 case X86::VGETMANTSDZrrib:
4386 case X86::VGETMANTSDZrmi:
4387 case X86::VGETMANTSSZrri:
4388 case X86::VGETMANTSSZrrib:
4389 case X86::VGETMANTSSZrmi:
4390 case X86::VRNDSCALESDZr:
4391 case X86::VRNDSCALESDZr_Int:
4392 case X86::VRNDSCALESDZrb_Int:
4393 case X86::VRNDSCALESDZm:
4394 case X86::VRNDSCALESDZm_Int:
4395 case X86::VRNDSCALESSZr:
4396 case X86::VRNDSCALESSZr_Int:
4397 case X86::VRNDSCALESSZrb_Int:
4398 case X86::VRNDSCALESSZm:
4399 case X86::VRNDSCALESSZm_Int:
4400 case X86::VRCP14SDZrr:
4401 case X86::VRCP14SDZrm:
4402 case X86::VRCP14SSZrr:
4403 case X86::VRCP14SSZrm:
4404 case X86::VRCP28SDZr:
4405 case X86::VRCP28SDZrb:
4406 case X86::VRCP28SDZm:
4407 case X86::VRCP28SSZr:
4408 case X86::VRCP28SSZrb:
4409 case X86::VRCP28SSZm:
4410 case X86::VREDUCESSZrmi:
4411 case X86::VREDUCESSZrri:
4412 case X86::VREDUCESSZrrib:
4413 case X86::VRSQRT14SDZrr:
4414 case X86::VRSQRT14SDZrm:
4415 case X86::VRSQRT14SSZrr:
4416 case X86::VRSQRT14SSZrm:
4417 case X86::VRSQRT28SDZr:
4418 case X86::VRSQRT28SDZrb:
4419 case X86::VRSQRT28SDZm:
4420 case X86::VRSQRT28SSZr:
4421 case X86::VRSQRT28SSZrb:
4422 case X86::VRSQRT28SSZm:
4423 case X86::VSQRTSSZr:
4424 case X86::VSQRTSSZr_Int:
4425 case X86::VSQRTSSZrb_Int:
4426 case X86::VSQRTSSZm:
4427 case X86::VSQRTSSZm_Int:
4428 case X86::VSQRTSDZr:
4429 case X86::VSQRTSDZr_Int:
4430 case X86::VSQRTSDZrb_Int:
4431 case X86::VSQRTSDZm:
4432 case X86::VSQRTSDZm_Int:
4439 /// Inform the BreakFalseDeps pass how many idle instructions we would like
4440 /// before certain undef register reads.
4442 /// This catches the VCVTSI2SD family of instructions:
4444 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
4446 /// We should to be careful *not* to catch VXOR idioms which are presumably
4447 /// handled specially in the pipeline:
4449 /// vxorps undef %xmm1, undef %xmm1, %xmm1
4451 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4452 /// high bits that are passed-through are not live.
4454 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
4455 const TargetRegisterInfo *TRI) const {
4456 if (!hasUndefRegUpdate(MI.getOpcode()))
4459 // Set the OpNum parameter to the first source operand.
4462 const MachineOperand &MO = MI.getOperand(OpNum);
4463 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4464 return UndefRegClearance;
4469 void X86InstrInfo::breakPartialRegDependency(
4470 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
4471 unsigned Reg = MI.getOperand(OpNum).getReg();
4472 // If MI kills this register, the false dependence is already broken.
4473 if (MI.killsRegister(Reg, TRI))
4476 if (X86::VR128RegClass.contains(Reg)) {
4477 // These instructions are all floating point domain, so xorps is the best
4479 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
4480 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
4481 .addReg(Reg, RegState::Undef)
4482 .addReg(Reg, RegState::Undef);
4483 MI.addRegisterKilled(Reg, TRI, true);
4484 } else if (X86::VR256RegClass.contains(Reg)) {
4485 // Use vxorps to clear the full ymm register.
4486 // It wants to read and write the xmm sub-register.
4487 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4488 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
4489 .addReg(XReg, RegState::Undef)
4490 .addReg(XReg, RegState::Undef)
4491 .addReg(Reg, RegState::ImplicitDefine);
4492 MI.addRegisterKilled(Reg, TRI, true);
4493 } else if (X86::GR64RegClass.contains(Reg)) {
4494 // Using XOR32rr because it has shorter encoding and zeros up the upper bits
4496 unsigned XReg = TRI->getSubReg(Reg, X86::sub_32bit);
4497 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
4498 .addReg(XReg, RegState::Undef)
4499 .addReg(XReg, RegState::Undef)
4500 .addReg(Reg, RegState::ImplicitDefine);
4501 MI.addRegisterKilled(Reg, TRI, true);
4502 } else if (X86::GR32RegClass.contains(Reg)) {
4503 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
4504 .addReg(Reg, RegState::Undef)
4505 .addReg(Reg, RegState::Undef);
4506 MI.addRegisterKilled(Reg, TRI, true);
4510 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
4511 int PtrOffset = 0) {
4512 unsigned NumAddrOps = MOs.size();
4514 if (NumAddrOps < 4) {
4515 // FrameIndex only - add an immediate offset (whether its zero or not).
4516 for (unsigned i = 0; i != NumAddrOps; ++i)
4518 addOffset(MIB, PtrOffset);
4520 // General Memory Addressing - we need to add any offset to an existing
4522 assert(MOs.size() == 5 && "Unexpected memory operand list length");
4523 for (unsigned i = 0; i != NumAddrOps; ++i) {
4524 const MachineOperand &MO = MOs[i];
4525 if (i == 3 && PtrOffset != 0) {
4526 MIB.addDisp(MO, PtrOffset);
4534 static void updateOperandRegConstraints(MachineFunction &MF,
4535 MachineInstr &NewMI,
4536 const TargetInstrInfo &TII) {
4537 MachineRegisterInfo &MRI = MF.getRegInfo();
4538 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
4540 for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
4541 MachineOperand &MO = NewMI.getOperand(Idx);
4542 // We only need to update constraints on virtual register operands.
4545 unsigned Reg = MO.getReg();
4546 if (!TRI.isVirtualRegister(Reg))
4549 auto *NewRC = MRI.constrainRegClass(
4550 Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
4553 dbgs() << "WARNING: Unable to update register constraint for operand "
4554 << Idx << " of instruction:\n";
4555 NewMI.dump(); dbgs() << "\n");
4560 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4561 ArrayRef<MachineOperand> MOs,
4562 MachineBasicBlock::iterator InsertPt,
4564 const TargetInstrInfo &TII) {
4565 // Create the base instruction with the memory operand as the first part.
4566 // Omit the implicit operands, something BuildMI can't do.
4567 MachineInstr *NewMI =
4568 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4569 MachineInstrBuilder MIB(MF, NewMI);
4570 addOperands(MIB, MOs);
4572 // Loop over the rest of the ri operands, converting them over.
4573 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
4574 for (unsigned i = 0; i != NumOps; ++i) {
4575 MachineOperand &MO = MI.getOperand(i + 2);
4578 for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
4579 MachineOperand &MO = MI.getOperand(i);
4583 updateOperandRegConstraints(MF, *NewMI, TII);
4585 MachineBasicBlock *MBB = InsertPt->getParent();
4586 MBB->insert(InsertPt, NewMI);
4591 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
4592 unsigned OpNo, ArrayRef<MachineOperand> MOs,
4593 MachineBasicBlock::iterator InsertPt,
4594 MachineInstr &MI, const TargetInstrInfo &TII,
4595 int PtrOffset = 0) {
4596 // Omit the implicit operands, something BuildMI can't do.
4597 MachineInstr *NewMI =
4598 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4599 MachineInstrBuilder MIB(MF, NewMI);
4601 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4602 MachineOperand &MO = MI.getOperand(i);
4604 assert(MO.isReg() && "Expected to fold into reg operand!");
4605 addOperands(MIB, MOs, PtrOffset);
4611 updateOperandRegConstraints(MF, *NewMI, TII);
4613 MachineBasicBlock *MBB = InsertPt->getParent();
4614 MBB->insert(InsertPt, NewMI);
4619 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4620 ArrayRef<MachineOperand> MOs,
4621 MachineBasicBlock::iterator InsertPt,
4623 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
4624 MI.getDebugLoc(), TII.get(Opcode));
4625 addOperands(MIB, MOs);
4626 return MIB.addImm(0);
4629 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
4630 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4631 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4632 unsigned Size, unsigned Align) const {
4633 switch (MI.getOpcode()) {
4634 case X86::INSERTPSrr:
4635 case X86::VINSERTPSrr:
4636 case X86::VINSERTPSZrr:
4637 // Attempt to convert the load of inserted vector into a fold load
4638 // of a single float.
4640 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
4641 unsigned ZMask = Imm & 15;
4642 unsigned DstIdx = (Imm >> 4) & 3;
4643 unsigned SrcIdx = (Imm >> 6) & 3;
4645 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4646 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4647 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4648 if ((Size == 0 || Size >= 16) && RCSize >= 16 && 4 <= Align) {
4649 int PtrOffset = SrcIdx * 4;
4650 unsigned NewImm = (DstIdx << 4) | ZMask;
4651 unsigned NewOpCode =
4652 (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
4653 (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm :
4655 MachineInstr *NewMI =
4656 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
4657 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
4662 case X86::MOVHLPSrr:
4663 case X86::VMOVHLPSrr:
4664 case X86::VMOVHLPSZrr:
4665 // Move the upper 64-bits of the second operand to the lower 64-bits.
4666 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
4667 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
4669 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4670 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4671 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4672 if ((Size == 0 || Size >= 16) && RCSize >= 16 && 8 <= Align) {
4673 unsigned NewOpCode =
4674 (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
4675 (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm :
4677 MachineInstr *NewMI =
4678 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
4683 case X86::UNPCKLPDrr:
4684 // If we won't be able to fold this to the memory form of UNPCKL, use
4685 // MOVHPD instead. Done as custom because we can't have this in the load
4688 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4689 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4690 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4691 if ((Size == 0 || Size >= 16) && RCSize >= 16 && Align < 16) {
4692 MachineInstr *NewMI =
4693 FuseInst(MF, X86::MOVHPDrm, OpNum, MOs, InsertPt, MI, *this);
4703 static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
4705 if (!hasUndefRegUpdate(MI.getOpcode(), /*ForLoadFold*/true) ||
4706 !MI.getOperand(1).isReg())
4709 // The are two cases we need to handle depending on where in the pipeline
4710 // the folding attempt is being made.
4711 // -Register has the undef flag set.
4712 // -Register is produced by the IMPLICIT_DEF instruction.
4714 if (MI.getOperand(1).isUndef())
4717 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4718 MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
4719 return VRegDef && VRegDef->isImplicitDef();
4723 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
4724 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4725 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4726 unsigned Size, unsigned Align, bool AllowCommute) const {
4727 bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
4728 bool isTwoAddrFold = false;
4730 // For CPUs that favor the register form of a call or push,
4731 // do not fold loads into calls or pushes, unless optimizing for size
4733 if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
4734 (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
4735 MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
4736 MI.getOpcode() == X86::PUSH64r))
4739 // Avoid partial and undef register update stalls unless optimizing for size.
4740 if (!MF.getFunction().hasOptSize() &&
4741 (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
4742 shouldPreventUndefRegUpdateMemFold(MF, MI)))
4745 unsigned NumOps = MI.getDesc().getNumOperands();
4747 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4749 // FIXME: AsmPrinter doesn't know how to handle
4750 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4751 if (MI.getOpcode() == X86::ADD32ri &&
4752 MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4755 // GOTTPOFF relocation loads can only be folded into add instructions.
4756 // FIXME: Need to exclude other relocations that only support specific
4758 if (MOs.size() == X86::AddrNumOperands &&
4759 MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
4760 MI.getOpcode() != X86::ADD64rr)
4763 MachineInstr *NewMI = nullptr;
4765 // Attempt to fold any custom cases we have.
4766 if (MachineInstr *CustomMI =
4767 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
4770 const X86MemoryFoldTableEntry *I = nullptr;
4772 // Folding a memory location into the two-address part of a two-address
4773 // instruction is different than folding it other places. It requires
4774 // replacing the *two* registers with the memory location.
4775 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
4776 MI.getOperand(1).isReg() &&
4777 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
4778 I = lookupTwoAddrFoldTable(MI.getOpcode());
4779 isTwoAddrFold = true;
4782 if (MI.getOpcode() == X86::MOV32r0) {
4783 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
4789 I = lookupFoldTable(MI.getOpcode(), OpNum);
4793 unsigned Opcode = I->DstOp;
4794 unsigned MinAlign = (I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4795 if (Align < MinAlign)
4797 bool NarrowToMOV32rm = false;
4799 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4800 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
4802 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4803 if (Size < RCSize) {
4804 // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
4805 // Check if it's safe to fold the load. If the size of the object is
4806 // narrower than the load width, then it's not.
4807 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4809 // If this is a 64-bit load, but the spill slot is 32, then we can do
4810 // a 32-bit load which is implicitly zero-extended. This likely is
4811 // due to live interval analysis remat'ing a load from stack slot.
4812 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
4814 Opcode = X86::MOV32rm;
4815 NarrowToMOV32rm = true;
4820 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
4822 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
4824 if (NarrowToMOV32rm) {
4825 // If this is the special case where we use a MOV32rm to load a 32-bit
4826 // value and zero-extend the top bits. Change the destination register
4828 unsigned DstReg = NewMI->getOperand(0).getReg();
4829 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4830 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4832 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4837 // If the instruction and target operand are commutable, commute the
4838 // instruction and try again.
4840 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
4841 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4842 bool HasDef = MI.getDesc().getNumDefs();
4843 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
4844 Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
4845 Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
4847 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4849 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4851 // If either of the commutable operands are tied to the destination
4852 // then we can not commute + fold.
4853 if ((HasDef && Reg0 == Reg1 && Tied1) ||
4854 (HasDef && Reg0 == Reg2 && Tied2))
4857 MachineInstr *CommutedMI =
4858 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4860 // Unable to commute.
4863 if (CommutedMI != &MI) {
4864 // New instruction. We can't fold from this.
4865 CommutedMI->eraseFromParent();
4869 // Attempt to fold with the commuted version of the instruction.
4870 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
4871 Size, Align, /*AllowCommute=*/false);
4875 // Folding failed again - undo the commute before returning.
4876 MachineInstr *UncommutedMI =
4877 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4878 if (!UncommutedMI) {
4879 // Unable to commute.
4882 if (UncommutedMI != &MI) {
4883 // New instruction. It doesn't need to be kept.
4884 UncommutedMI->eraseFromParent();
4888 // Return here to prevent duplicate fuse failure report.
4894 if (PrintFailedFusing && !MI.isCopy())
4895 dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
4900 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
4901 ArrayRef<unsigned> Ops,
4902 MachineBasicBlock::iterator InsertPt,
4903 int FrameIndex, LiveIntervals *LIS,
4904 VirtRegMap *VRM) const {
4905 // Check switch flag
4909 // Avoid partial and undef register update stalls unless optimizing for size.
4910 if (!MF.getFunction().hasOptSize() &&
4911 (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
4912 shouldPreventUndefRegUpdateMemFold(MF, MI)))
4915 // Don't fold subreg spills, or reloads that use a high subreg.
4916 for (auto Op : Ops) {
4917 MachineOperand &MO = MI.getOperand(Op);
4918 auto SubReg = MO.getSubReg();
4919 if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
4923 const MachineFrameInfo &MFI = MF.getFrameInfo();
4924 unsigned Size = MFI.getObjectSize(FrameIndex);
4925 unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
4926 // If the function stack isn't realigned we don't want to fold instructions
4927 // that need increased alignment.
4928 if (!RI.needsStackRealignment(MF))
4930 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
4931 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4932 unsigned NewOpc = 0;
4933 unsigned RCSize = 0;
4934 switch (MI.getOpcode()) {
4935 default: return nullptr;
4936 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
4937 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4938 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
4939 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
4941 // Check if it's safe to fold the load. If the size of the object is
4942 // narrower than the load width, then it's not.
4945 // Change to CMPXXri r, 0 first.
4946 MI.setDesc(get(NewOpc));
4947 MI.getOperand(1).ChangeToImmediate(0);
4948 } else if (Ops.size() != 1)
4951 return foldMemoryOperandImpl(MF, MI, Ops[0],
4952 MachineOperand::CreateFI(FrameIndex), InsertPt,
4953 Size, Alignment, /*AllowCommute=*/true);
4956 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
4957 /// because the latter uses contents that wouldn't be defined in the folded
4958 /// version. For instance, this transformation isn't legal:
4959 /// movss (%rdi), %xmm0
4960 /// addps %xmm0, %xmm0
4962 /// addps (%rdi), %xmm0
4964 /// But this one is:
4965 /// movss (%rdi), %xmm0
4966 /// addss %xmm0, %xmm0
4968 /// addss (%rdi), %xmm0
4970 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
4971 const MachineInstr &UserMI,
4972 const MachineFunction &MF) {
4973 unsigned Opc = LoadMI.getOpcode();
4974 unsigned UserOpc = UserMI.getOpcode();
4975 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4976 const TargetRegisterClass *RC =
4977 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
4978 unsigned RegSize = TRI.getRegSizeInBits(*RC);
4980 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
4981 Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
4982 Opc == X86::VMOVSSZrm_alt) &&
4984 // These instructions only load 32 bits, we can't fold them if the
4985 // destination register is wider than 32 bits (4 bytes), and its user
4986 // instruction isn't scalar (SS).
4988 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
4989 case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
4990 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
4991 case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
4992 case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
4993 case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
4994 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
4995 case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
4996 case X86::VCMPSSZrr_Intk:
4997 case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
4998 case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
4999 case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
5000 case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
5001 case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
5002 case X86::VFMADDSS4rr_Int: case X86::VFNMADDSS4rr_Int:
5003 case X86::VFMSUBSS4rr_Int: case X86::VFNMSUBSS4rr_Int:
5004 case X86::VFMADD132SSr_Int: case X86::VFNMADD132SSr_Int:
5005 case X86::VFMADD213SSr_Int: case X86::VFNMADD213SSr_Int:
5006 case X86::VFMADD231SSr_Int: case X86::VFNMADD231SSr_Int:
5007 case X86::VFMSUB132SSr_Int: case X86::VFNMSUB132SSr_Int:
5008 case X86::VFMSUB213SSr_Int: case X86::VFNMSUB213SSr_Int:
5009 case X86::VFMSUB231SSr_Int: case X86::VFNMSUB231SSr_Int:
5010 case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
5011 case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
5012 case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
5013 case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
5014 case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
5015 case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
5016 case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
5017 case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
5018 case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
5019 case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
5020 case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
5021 case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
5022 case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
5023 case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
5024 case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
5025 case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
5026 case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
5027 case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
5034 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
5035 Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
5036 Opc == X86::VMOVSDZrm_alt) &&
5038 // These instructions only load 64 bits, we can't fold them if the
5039 // destination register is wider than 64 bits (8 bytes), and its user
5040 // instruction isn't scalar (SD).
5042 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
5043 case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
5044 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
5045 case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
5046 case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
5047 case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
5048 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
5049 case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
5050 case X86::VCMPSDZrr_Intk:
5051 case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
5052 case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
5053 case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
5054 case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
5055 case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
5056 case X86::VFMADDSD4rr_Int: case X86::VFNMADDSD4rr_Int:
5057 case X86::VFMSUBSD4rr_Int: case X86::VFNMSUBSD4rr_Int:
5058 case X86::VFMADD132SDr_Int: case X86::VFNMADD132SDr_Int:
5059 case X86::VFMADD213SDr_Int: case X86::VFNMADD213SDr_Int:
5060 case X86::VFMADD231SDr_Int: case X86::VFNMADD231SDr_Int:
5061 case X86::VFMSUB132SDr_Int: case X86::VFNMSUB132SDr_Int:
5062 case X86::VFMSUB213SDr_Int: case X86::VFNMSUB213SDr_Int:
5063 case X86::VFMSUB231SDr_Int: case X86::VFNMSUB231SDr_Int:
5064 case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
5065 case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
5066 case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
5067 case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
5068 case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
5069 case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
5070 case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
5071 case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
5072 case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
5073 case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
5074 case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
5075 case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
5076 case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
5077 case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
5078 case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
5079 case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
5080 case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
5081 case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
5091 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5092 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
5093 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
5094 LiveIntervals *LIS) const {
5096 // TODO: Support the case where LoadMI loads a wide register, but MI
5097 // only uses a subreg.
5098 for (auto Op : Ops) {
5099 if (MI.getOperand(Op).getSubReg())
5103 // If loading from a FrameIndex, fold directly from the FrameIndex.
5104 unsigned NumOps = LoadMI.getDesc().getNumOperands();
5106 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5107 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5109 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
5112 // Check switch flag
5113 if (NoFusing) return nullptr;
5115 // Avoid partial and undef register update stalls unless optimizing for size.
5116 if (!MF.getFunction().hasOptSize() &&
5117 (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5118 shouldPreventUndefRegUpdateMemFold(MF, MI)))
5121 // Determine the alignment of the load.
5122 unsigned Alignment = 0;
5123 if (LoadMI.hasOneMemOperand())
5124 Alignment = (*LoadMI.memoperands_begin())->getAlignment();
5126 switch (LoadMI.getOpcode()) {
5127 case X86::AVX512_512_SET0:
5128 case X86::AVX512_512_SETALLONES:
5131 case X86::AVX2_SETALLONES:
5132 case X86::AVX1_SETALLONES:
5134 case X86::AVX512_256_SET0:
5138 case X86::V_SETALLONES:
5139 case X86::AVX512_128_SET0:
5144 case X86::AVX512_FsFLD0SD:
5148 case X86::AVX512_FsFLD0SS:
5154 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5155 unsigned NewOpc = 0;
5156 switch (MI.getOpcode()) {
5157 default: return nullptr;
5158 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
5159 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5160 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5161 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
5163 // Change to CMPXXri r, 0 first.
5164 MI.setDesc(get(NewOpc));
5165 MI.getOperand(1).ChangeToImmediate(0);
5166 } else if (Ops.size() != 1)
5169 // Make sure the subregisters match.
5170 // Otherwise we risk changing the size of the load.
5171 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
5174 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
5175 switch (LoadMI.getOpcode()) {
5178 case X86::V_SETALLONES:
5179 case X86::AVX2_SETALLONES:
5180 case X86::AVX1_SETALLONES:
5182 case X86::AVX512_128_SET0:
5183 case X86::AVX512_256_SET0:
5184 case X86::AVX512_512_SET0:
5185 case X86::AVX512_512_SETALLONES:
5187 case X86::AVX512_FsFLD0SD:
5189 case X86::AVX512_FsFLD0SS: {
5190 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
5191 // Create a constant-pool entry and operands to load from it.
5193 // Medium and large mode can't fold loads this way.
5194 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5195 MF.getTarget().getCodeModel() != CodeModel::Kernel)
5198 // x86-32 PIC requires a PIC base register for constant pools.
5199 unsigned PICBase = 0;
5200 if (MF.getTarget().isPositionIndependent()) {
5201 if (Subtarget.is64Bit())
5204 // FIXME: PICBase = getGlobalBaseReg(&MF);
5205 // This doesn't work for several reasons.
5206 // 1. GlobalBaseReg may have been spilled.
5207 // 2. It may not be live at MI.
5211 // Create a constant-pool entry.
5212 MachineConstantPool &MCP = *MF.getConstantPool();
5214 unsigned Opc = LoadMI.getOpcode();
5215 if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
5216 Ty = Type::getFloatTy(MF.getFunction().getContext());
5217 else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
5218 Ty = Type::getDoubleTy(MF.getFunction().getContext());
5219 else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
5220 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),16);
5221 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
5222 Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
5223 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 8);
5224 else if (Opc == X86::MMX_SET0)
5225 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 2);
5227 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 4);
5229 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
5230 Opc == X86::AVX512_512_SETALLONES ||
5231 Opc == X86::AVX1_SETALLONES);
5232 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5233 Constant::getNullValue(Ty);
5234 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
5236 // Create operands to load from the constant pool entry.
5237 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5238 MOs.push_back(MachineOperand::CreateImm(1));
5239 MOs.push_back(MachineOperand::CreateReg(0, false));
5240 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
5241 MOs.push_back(MachineOperand::CreateReg(0, false));
5245 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5248 // Folding a normal load. Just copy the load's address operands.
5249 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
5250 LoadMI.operands_begin() + NumOps);
5254 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
5255 /*Size=*/0, Alignment, /*AllowCommute=*/true);
5258 static SmallVector<MachineMemOperand *, 2>
5259 extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5260 SmallVector<MachineMemOperand *, 2> LoadMMOs;
5262 for (MachineMemOperand *MMO : MMOs) {
5266 if (!MMO->isStore()) {
5268 LoadMMOs.push_back(MMO);
5270 // Clone the MMO and unset the store flag.
5271 LoadMMOs.push_back(MF.getMachineMemOperand(
5272 MMO, MMO->getFlags() & ~MachineMemOperand::MOStore));
5279 static SmallVector<MachineMemOperand *, 2>
5280 extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5281 SmallVector<MachineMemOperand *, 2> StoreMMOs;
5283 for (MachineMemOperand *MMO : MMOs) {
5284 if (!MMO->isStore())
5287 if (!MMO->isLoad()) {
5289 StoreMMOs.push_back(MMO);
5291 // Clone the MMO and unset the load flag.
5292 StoreMMOs.push_back(MF.getMachineMemOperand(
5293 MMO, MMO->getFlags() & ~MachineMemOperand::MOLoad));
5300 bool X86InstrInfo::unfoldMemoryOperand(
5301 MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
5302 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
5303 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(MI.getOpcode());
5306 unsigned Opc = I->DstOp;
5307 unsigned Index = I->Flags & TB_INDEX_MASK;
5308 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5309 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5310 if (UnfoldLoad && !FoldedLoad)
5312 UnfoldLoad &= FoldedLoad;
5313 if (UnfoldStore && !FoldedStore)
5315 UnfoldStore &= FoldedStore;
5317 const MCInstrDesc &MCID = get(Opc);
5318 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5319 // TODO: Check if 32-byte or greater accesses are slow too?
5320 if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
5321 Subtarget.isUnalignedMem16Slow())
5322 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
5323 // conservatively assume the address is unaligned. That's bad for
5326 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
5327 SmallVector<MachineOperand,2> BeforeOps;
5328 SmallVector<MachineOperand,2> AfterOps;
5329 SmallVector<MachineOperand,4> ImpOps;
5330 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5331 MachineOperand &Op = MI.getOperand(i);
5332 if (i >= Index && i < Index + X86::AddrNumOperands)
5333 AddrOps.push_back(Op);
5334 else if (Op.isReg() && Op.isImplicit())
5335 ImpOps.push_back(Op);
5337 BeforeOps.push_back(Op);
5339 AfterOps.push_back(Op);
5342 // Emit the load instruction.
5344 auto MMOs = extractLoadMMOs(MI.memoperands(), MF);
5345 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs, NewMIs);
5347 // Address operands cannot be marked isKill.
5348 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
5349 MachineOperand &MO = NewMIs[0]->getOperand(i);
5351 MO.setIsKill(false);
5356 // Emit the data processing instruction.
5357 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
5358 MachineInstrBuilder MIB(MF, DataMI);
5361 MIB.addReg(Reg, RegState::Define);
5362 for (MachineOperand &BeforeOp : BeforeOps)
5366 for (MachineOperand &AfterOp : AfterOps)
5368 for (MachineOperand &ImpOp : ImpOps) {
5369 MIB.addReg(ImpOp.getReg(),
5370 getDefRegState(ImpOp.isDef()) |
5371 RegState::Implicit |
5372 getKillRegState(ImpOp.isKill()) |
5373 getDeadRegState(ImpOp.isDead()) |
5374 getUndefRegState(ImpOp.isUndef()));
5376 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5377 switch (DataMI->getOpcode()) {
5379 case X86::CMP64ri32:
5386 MachineOperand &MO0 = DataMI->getOperand(0);
5387 MachineOperand &MO1 = DataMI->getOperand(1);
5388 if (MO1.getImm() == 0) {
5390 switch (DataMI->getOpcode()) {
5391 default: llvm_unreachable("Unreachable!");
5393 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
5395 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
5397 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
5398 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
5400 DataMI->setDesc(get(NewOpc));
5401 MO1.ChangeToRegister(MO0.getReg(), false);
5405 NewMIs.push_back(DataMI);
5407 // Emit the store instruction.
5409 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
5410 auto MMOs = extractStoreMMOs(MI.memoperands(), MF);
5411 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs, NewMIs);
5418 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
5419 SmallVectorImpl<SDNode*> &NewNodes) const {
5420 if (!N->isMachineOpcode())
5423 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
5426 unsigned Opc = I->DstOp;
5427 unsigned Index = I->Flags & TB_INDEX_MASK;
5428 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5429 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5430 const MCInstrDesc &MCID = get(Opc);
5431 MachineFunction &MF = DAG.getMachineFunction();
5432 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5433 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5434 unsigned NumDefs = MCID.NumDefs;
5435 std::vector<SDValue> AddrOps;
5436 std::vector<SDValue> BeforeOps;
5437 std::vector<SDValue> AfterOps;
5439 unsigned NumOps = N->getNumOperands();
5440 for (unsigned i = 0; i != NumOps-1; ++i) {
5441 SDValue Op = N->getOperand(i);
5442 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
5443 AddrOps.push_back(Op);
5444 else if (i < Index-NumDefs)
5445 BeforeOps.push_back(Op);
5446 else if (i > Index-NumDefs)
5447 AfterOps.push_back(Op);
5449 SDValue Chain = N->getOperand(NumOps-1);
5450 AddrOps.push_back(Chain);
5452 // Emit the load instruction.
5453 SDNode *Load = nullptr;
5455 EVT VT = *TRI.legalclasstypes_begin(*RC);
5456 auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
5457 if (MMOs.empty() && RC == &X86::VR128RegClass &&
5458 Subtarget.isUnalignedMem16Slow())
5459 // Do not introduce a slow unaligned load.
5461 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5462 // memory access is slow above.
5463 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5464 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5465 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
5466 VT, MVT::Other, AddrOps);
5467 NewNodes.push_back(Load);
5469 // Preserve memory reference information.
5470 DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
5473 // Emit the data processing instruction.
5474 std::vector<EVT> VTs;
5475 const TargetRegisterClass *DstRC = nullptr;
5476 if (MCID.getNumDefs() > 0) {
5477 DstRC = getRegClass(MCID, 0, &RI, MF);
5478 VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
5480 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
5481 EVT VT = N->getValueType(i);
5482 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
5486 BeforeOps.push_back(SDValue(Load, 0));
5487 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
5488 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5491 case X86::CMP64ri32:
5498 if (isNullConstant(BeforeOps[1])) {
5500 default: llvm_unreachable("Unreachable!");
5502 case X86::CMP64ri32: Opc = X86::TEST64rr; break;
5504 case X86::CMP32ri: Opc = X86::TEST32rr; break;
5506 case X86::CMP16ri: Opc = X86::TEST16rr; break;
5507 case X86::CMP8ri: Opc = X86::TEST8rr; break;
5509 BeforeOps[1] = BeforeOps[0];
5512 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
5513 NewNodes.push_back(NewNode);
5515 // Emit the store instruction.
5518 AddrOps.push_back(SDValue(NewNode, 0));
5519 AddrOps.push_back(Chain);
5520 auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
5521 if (MMOs.empty() && RC == &X86::VR128RegClass &&
5522 Subtarget.isUnalignedMem16Slow())
5523 // Do not introduce a slow unaligned store.
5525 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5526 // memory access is slow above.
5527 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5528 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5530 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5531 dl, MVT::Other, AddrOps);
5532 NewNodes.push_back(Store);
5534 // Preserve memory reference information.
5535 DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
5541 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
5542 bool UnfoldLoad, bool UnfoldStore,
5543 unsigned *LoadRegIndex) const {
5544 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(Opc);
5547 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5548 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5549 if (UnfoldLoad && !FoldedLoad)
5551 if (UnfoldStore && !FoldedStore)
5554 *LoadRegIndex = I->Flags & TB_INDEX_MASK;
5559 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5560 int64_t &Offset1, int64_t &Offset2) const {
5561 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5563 unsigned Opc1 = Load1->getMachineOpcode();
5564 unsigned Opc2 = Load2->getMachineOpcode();
5566 default: return false;
5575 case X86::MOVSSrm_alt:
5577 case X86::MOVSDrm_alt:
5578 case X86::MMX_MOVD64rm:
5579 case X86::MMX_MOVQ64rm:
5586 // AVX load instructions
5588 case X86::VMOVSSrm_alt:
5590 case X86::VMOVSDrm_alt:
5591 case X86::VMOVAPSrm:
5592 case X86::VMOVUPSrm:
5593 case X86::VMOVAPDrm:
5594 case X86::VMOVUPDrm:
5595 case X86::VMOVDQArm:
5596 case X86::VMOVDQUrm:
5597 case X86::VMOVAPSYrm:
5598 case X86::VMOVUPSYrm:
5599 case X86::VMOVAPDYrm:
5600 case X86::VMOVUPDYrm:
5601 case X86::VMOVDQAYrm:
5602 case X86::VMOVDQUYrm:
5603 // AVX512 load instructions
5604 case X86::VMOVSSZrm:
5605 case X86::VMOVSSZrm_alt:
5606 case X86::VMOVSDZrm:
5607 case X86::VMOVSDZrm_alt:
5608 case X86::VMOVAPSZ128rm:
5609 case X86::VMOVUPSZ128rm:
5610 case X86::VMOVAPSZ128rm_NOVLX:
5611 case X86::VMOVUPSZ128rm_NOVLX:
5612 case X86::VMOVAPDZ128rm:
5613 case X86::VMOVUPDZ128rm:
5614 case X86::VMOVDQU8Z128rm:
5615 case X86::VMOVDQU16Z128rm:
5616 case X86::VMOVDQA32Z128rm:
5617 case X86::VMOVDQU32Z128rm:
5618 case X86::VMOVDQA64Z128rm:
5619 case X86::VMOVDQU64Z128rm:
5620 case X86::VMOVAPSZ256rm:
5621 case X86::VMOVUPSZ256rm:
5622 case X86::VMOVAPSZ256rm_NOVLX:
5623 case X86::VMOVUPSZ256rm_NOVLX:
5624 case X86::VMOVAPDZ256rm:
5625 case X86::VMOVUPDZ256rm:
5626 case X86::VMOVDQU8Z256rm:
5627 case X86::VMOVDQU16Z256rm:
5628 case X86::VMOVDQA32Z256rm:
5629 case X86::VMOVDQU32Z256rm:
5630 case X86::VMOVDQA64Z256rm:
5631 case X86::VMOVDQU64Z256rm:
5632 case X86::VMOVAPSZrm:
5633 case X86::VMOVUPSZrm:
5634 case X86::VMOVAPDZrm:
5635 case X86::VMOVUPDZrm:
5636 case X86::VMOVDQU8Zrm:
5637 case X86::VMOVDQU16Zrm:
5638 case X86::VMOVDQA32Zrm:
5639 case X86::VMOVDQU32Zrm:
5640 case X86::VMOVDQA64Zrm:
5641 case X86::VMOVDQU64Zrm:
5649 default: return false;
5658 case X86::MOVSSrm_alt:
5660 case X86::MOVSDrm_alt:
5661 case X86::MMX_MOVD64rm:
5662 case X86::MMX_MOVQ64rm:
5669 // AVX load instructions
5671 case X86::VMOVSSrm_alt:
5673 case X86::VMOVSDrm_alt:
5674 case X86::VMOVAPSrm:
5675 case X86::VMOVUPSrm:
5676 case X86::VMOVAPDrm:
5677 case X86::VMOVUPDrm:
5678 case X86::VMOVDQArm:
5679 case X86::VMOVDQUrm:
5680 case X86::VMOVAPSYrm:
5681 case X86::VMOVUPSYrm:
5682 case X86::VMOVAPDYrm:
5683 case X86::VMOVUPDYrm:
5684 case X86::VMOVDQAYrm:
5685 case X86::VMOVDQUYrm:
5686 // AVX512 load instructions
5687 case X86::VMOVSSZrm:
5688 case X86::VMOVSSZrm_alt:
5689 case X86::VMOVSDZrm:
5690 case X86::VMOVSDZrm_alt:
5691 case X86::VMOVAPSZ128rm:
5692 case X86::VMOVUPSZ128rm:
5693 case X86::VMOVAPSZ128rm_NOVLX:
5694 case X86::VMOVUPSZ128rm_NOVLX:
5695 case X86::VMOVAPDZ128rm:
5696 case X86::VMOVUPDZ128rm:
5697 case X86::VMOVDQU8Z128rm:
5698 case X86::VMOVDQU16Z128rm:
5699 case X86::VMOVDQA32Z128rm:
5700 case X86::VMOVDQU32Z128rm:
5701 case X86::VMOVDQA64Z128rm:
5702 case X86::VMOVDQU64Z128rm:
5703 case X86::VMOVAPSZ256rm:
5704 case X86::VMOVUPSZ256rm:
5705 case X86::VMOVAPSZ256rm_NOVLX:
5706 case X86::VMOVUPSZ256rm_NOVLX:
5707 case X86::VMOVAPDZ256rm:
5708 case X86::VMOVUPDZ256rm:
5709 case X86::VMOVDQU8Z256rm:
5710 case X86::VMOVDQU16Z256rm:
5711 case X86::VMOVDQA32Z256rm:
5712 case X86::VMOVDQU32Z256rm:
5713 case X86::VMOVDQA64Z256rm:
5714 case X86::VMOVDQU64Z256rm:
5715 case X86::VMOVAPSZrm:
5716 case X86::VMOVUPSZrm:
5717 case X86::VMOVAPDZrm:
5718 case X86::VMOVUPDZrm:
5719 case X86::VMOVDQU8Zrm:
5720 case X86::VMOVDQU16Zrm:
5721 case X86::VMOVDQA32Zrm:
5722 case X86::VMOVDQU32Zrm:
5723 case X86::VMOVDQA64Zrm:
5724 case X86::VMOVDQU64Zrm:
5732 // Lambda to check if both the loads have the same value for an operand index.
5733 auto HasSameOp = [&](int I) {
5734 return Load1->getOperand(I) == Load2->getOperand(I);
5737 // All operands except the displacement should match.
5738 if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
5739 !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
5742 // Chain Operand must be the same.
5746 // Now let's examine if the displacements are constants.
5747 auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
5748 auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
5749 if (!Disp1 || !Disp2)
5752 Offset1 = Disp1->getSExtValue();
5753 Offset2 = Disp2->getSExtValue();
5757 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5758 int64_t Offset1, int64_t Offset2,
5759 unsigned NumLoads) const {
5760 assert(Offset2 > Offset1);
5761 if ((Offset2 - Offset1) / 8 > 64)
5764 unsigned Opc1 = Load1->getMachineOpcode();
5765 unsigned Opc2 = Load2->getMachineOpcode();
5767 return false; // FIXME: overly conservative?
5774 case X86::MMX_MOVD64rm:
5775 case X86::MMX_MOVQ64rm:
5779 EVT VT = Load1->getValueType(0);
5780 switch (VT.getSimpleVT().SimpleTy) {
5782 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5783 // have 16 of them to play with.
5784 if (Subtarget.is64Bit()) {
5787 } else if (NumLoads) {
5806 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5807 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5808 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5809 Cond[0].setImm(GetOppositeBranchCondition(CC));
5814 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5815 // FIXME: Return false for x87 stack register classes for now. We can't
5816 // allow any loads of these registers before FpGet_ST0_80.
5817 return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
5818 RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
5819 RC == &X86::RFP80RegClass);
5822 /// Return a virtual register initialized with the
5823 /// the global base register value. Output instructions required to
5824 /// initialize the register in the function entry block, if necessary.
5826 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5828 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
5829 assert((!Subtarget.is64Bit() ||
5830 MF->getTarget().getCodeModel() == CodeModel::Medium ||
5831 MF->getTarget().getCodeModel() == CodeModel::Large) &&
5832 "X86-64 PIC uses RIP relative addressing");
5834 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5835 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5836 if (GlobalBaseReg != 0)
5837 return GlobalBaseReg;
5839 // Create the register. The code to initialize it is inserted
5840 // later, by the CGBR pass (below).
5841 MachineRegisterInfo &RegInfo = MF->getRegInfo();
5842 GlobalBaseReg = RegInfo.createVirtualRegister(
5843 Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
5844 X86FI->setGlobalBaseReg(GlobalBaseReg);
5845 return GlobalBaseReg;
5848 // These are the replaceable SSE instructions. Some of these have Int variants
5849 // that we don't include here. We don't want to replace instructions selected
5851 static const uint16_t ReplaceableInstrs[][3] = {
5852 //PackedSingle PackedDouble PackedInt
5853 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
5854 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
5855 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
5856 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
5857 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
5858 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
5859 { X86::MOVSDmr, X86::MOVSDmr, X86::MOVPQI2QImr },
5860 { X86::MOVSSmr, X86::MOVSSmr, X86::MOVPDI2DImr },
5861 { X86::MOVSDrm, X86::MOVSDrm, X86::MOVQI2PQIrm },
5862 { X86::MOVSDrm_alt,X86::MOVSDrm_alt,X86::MOVQI2PQIrm },
5863 { X86::MOVSSrm, X86::MOVSSrm, X86::MOVDI2PDIrm },
5864 { X86::MOVSSrm_alt,X86::MOVSSrm_alt,X86::MOVDI2PDIrm },
5865 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
5866 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
5867 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
5868 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
5869 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
5870 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
5871 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
5872 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
5873 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
5874 { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
5875 { X86::MOVLHPSrr, X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
5876 { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
5877 { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
5878 { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
5879 { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
5880 { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
5881 { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
5882 { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
5883 { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
5884 // AVX 128-bit support
5885 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
5886 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
5887 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
5888 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
5889 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
5890 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
5891 { X86::VMOVSDmr, X86::VMOVSDmr, X86::VMOVPQI2QImr },
5892 { X86::VMOVSSmr, X86::VMOVSSmr, X86::VMOVPDI2DImr },
5893 { X86::VMOVSDrm, X86::VMOVSDrm, X86::VMOVQI2PQIrm },
5894 { X86::VMOVSDrm_alt,X86::VMOVSDrm_alt,X86::VMOVQI2PQIrm },
5895 { X86::VMOVSSrm, X86::VMOVSSrm, X86::VMOVDI2PDIrm },
5896 { X86::VMOVSSrm_alt,X86::VMOVSSrm_alt,X86::VMOVDI2PDIrm },
5897 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5898 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
5899 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
5900 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
5901 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
5902 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
5903 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
5904 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
5905 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
5906 { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
5907 { X86::VMOVLHPSrr, X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
5908 { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
5909 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
5910 { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
5911 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
5912 { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
5913 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
5914 { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
5915 { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
5916 // AVX 256-bit support
5917 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
5918 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
5919 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
5920 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
5921 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
5922 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr },
5923 { X86::VPERMPSYrm, X86::VPERMPSYrm, X86::VPERMDYrm },
5924 { X86::VPERMPSYrr, X86::VPERMPSYrr, X86::VPERMDYrr },
5925 { X86::VPERMPDYmi, X86::VPERMPDYmi, X86::VPERMQYmi },
5926 { X86::VPERMPDYri, X86::VPERMPDYri, X86::VPERMQYri },
5928 { X86::VMOVLPSZ128mr, X86::VMOVLPDZ128mr, X86::VMOVPQI2QIZmr },
5929 { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
5930 { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
5931 { X86::VMOVNTPSZmr, X86::VMOVNTPDZmr, X86::VMOVNTDQZmr },
5932 { X86::VMOVSDZmr, X86::VMOVSDZmr, X86::VMOVPQI2QIZmr },
5933 { X86::VMOVSSZmr, X86::VMOVSSZmr, X86::VMOVPDI2DIZmr },
5934 { X86::VMOVSDZrm, X86::VMOVSDZrm, X86::VMOVQI2PQIZrm },
5935 { X86::VMOVSDZrm_alt, X86::VMOVSDZrm_alt, X86::VMOVQI2PQIZrm },
5936 { X86::VMOVSSZrm, X86::VMOVSSZrm, X86::VMOVDI2PDIZrm },
5937 { X86::VMOVSSZrm_alt, X86::VMOVSSZrm_alt, X86::VMOVDI2PDIZrm },
5938 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128r, X86::VPBROADCASTDZ128r },
5939 { X86::VBROADCASTSSZ128m, X86::VBROADCASTSSZ128m, X86::VPBROADCASTDZ128m },
5940 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256r, X86::VPBROADCASTDZ256r },
5941 { X86::VBROADCASTSSZ256m, X86::VBROADCASTSSZ256m, X86::VPBROADCASTDZ256m },
5942 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZr, X86::VPBROADCASTDZr },
5943 { X86::VBROADCASTSSZm, X86::VBROADCASTSSZm, X86::VPBROADCASTDZm },
5944 { X86::VMOVDDUPZ128rr, X86::VMOVDDUPZ128rr, X86::VPBROADCASTQZ128r },
5945 { X86::VMOVDDUPZ128rm, X86::VMOVDDUPZ128rm, X86::VPBROADCASTQZ128m },
5946 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256r, X86::VPBROADCASTQZ256r },
5947 { X86::VBROADCASTSDZ256m, X86::VBROADCASTSDZ256m, X86::VPBROADCASTQZ256m },
5948 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZr, X86::VPBROADCASTQZr },
5949 { X86::VBROADCASTSDZm, X86::VBROADCASTSDZm, X86::VPBROADCASTQZm },
5950 { X86::VINSERTF32x4Zrr, X86::VINSERTF32x4Zrr, X86::VINSERTI32x4Zrr },
5951 { X86::VINSERTF32x4Zrm, X86::VINSERTF32x4Zrm, X86::VINSERTI32x4Zrm },
5952 { X86::VINSERTF32x8Zrr, X86::VINSERTF32x8Zrr, X86::VINSERTI32x8Zrr },
5953 { X86::VINSERTF32x8Zrm, X86::VINSERTF32x8Zrm, X86::VINSERTI32x8Zrm },
5954 { X86::VINSERTF64x2Zrr, X86::VINSERTF64x2Zrr, X86::VINSERTI64x2Zrr },
5955 { X86::VINSERTF64x2Zrm, X86::VINSERTF64x2Zrm, X86::VINSERTI64x2Zrm },
5956 { X86::VINSERTF64x4Zrr, X86::VINSERTF64x4Zrr, X86::VINSERTI64x4Zrr },
5957 { X86::VINSERTF64x4Zrm, X86::VINSERTF64x4Zrm, X86::VINSERTI64x4Zrm },
5958 { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
5959 { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
5960 { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
5961 { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
5962 { X86::VEXTRACTF32x4Zrr, X86::VEXTRACTF32x4Zrr, X86::VEXTRACTI32x4Zrr },
5963 { X86::VEXTRACTF32x4Zmr, X86::VEXTRACTF32x4Zmr, X86::VEXTRACTI32x4Zmr },
5964 { X86::VEXTRACTF32x8Zrr, X86::VEXTRACTF32x8Zrr, X86::VEXTRACTI32x8Zrr },
5965 { X86::VEXTRACTF32x8Zmr, X86::VEXTRACTF32x8Zmr, X86::VEXTRACTI32x8Zmr },
5966 { X86::VEXTRACTF64x2Zrr, X86::VEXTRACTF64x2Zrr, X86::VEXTRACTI64x2Zrr },
5967 { X86::VEXTRACTF64x2Zmr, X86::VEXTRACTF64x2Zmr, X86::VEXTRACTI64x2Zmr },
5968 { X86::VEXTRACTF64x4Zrr, X86::VEXTRACTF64x4Zrr, X86::VEXTRACTI64x4Zrr },
5969 { X86::VEXTRACTF64x4Zmr, X86::VEXTRACTF64x4Zmr, X86::VEXTRACTI64x4Zmr },
5970 { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
5971 { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
5972 { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
5973 { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
5974 { X86::VPERMILPSmi, X86::VPERMILPSmi, X86::VPSHUFDmi },
5975 { X86::VPERMILPSri, X86::VPERMILPSri, X86::VPSHUFDri },
5976 { X86::VPERMILPSZ128mi, X86::VPERMILPSZ128mi, X86::VPSHUFDZ128mi },
5977 { X86::VPERMILPSZ128ri, X86::VPERMILPSZ128ri, X86::VPSHUFDZ128ri },
5978 { X86::VPERMILPSZ256mi, X86::VPERMILPSZ256mi, X86::VPSHUFDZ256mi },
5979 { X86::VPERMILPSZ256ri, X86::VPERMILPSZ256ri, X86::VPSHUFDZ256ri },
5980 { X86::VPERMILPSZmi, X86::VPERMILPSZmi, X86::VPSHUFDZmi },
5981 { X86::VPERMILPSZri, X86::VPERMILPSZri, X86::VPSHUFDZri },
5982 { X86::VPERMPSZ256rm, X86::VPERMPSZ256rm, X86::VPERMDZ256rm },
5983 { X86::VPERMPSZ256rr, X86::VPERMPSZ256rr, X86::VPERMDZ256rr },
5984 { X86::VPERMPDZ256mi, X86::VPERMPDZ256mi, X86::VPERMQZ256mi },
5985 { X86::VPERMPDZ256ri, X86::VPERMPDZ256ri, X86::VPERMQZ256ri },
5986 { X86::VPERMPDZ256rm, X86::VPERMPDZ256rm, X86::VPERMQZ256rm },
5987 { X86::VPERMPDZ256rr, X86::VPERMPDZ256rr, X86::VPERMQZ256rr },
5988 { X86::VPERMPSZrm, X86::VPERMPSZrm, X86::VPERMDZrm },
5989 { X86::VPERMPSZrr, X86::VPERMPSZrr, X86::VPERMDZrr },
5990 { X86::VPERMPDZmi, X86::VPERMPDZmi, X86::VPERMQZmi },
5991 { X86::VPERMPDZri, X86::VPERMPDZri, X86::VPERMQZri },
5992 { X86::VPERMPDZrm, X86::VPERMPDZrm, X86::VPERMQZrm },
5993 { X86::VPERMPDZrr, X86::VPERMPDZrr, X86::VPERMQZrr },
5994 { X86::VUNPCKLPDZ256rm, X86::VUNPCKLPDZ256rm, X86::VPUNPCKLQDQZ256rm },
5995 { X86::VUNPCKLPDZ256rr, X86::VUNPCKLPDZ256rr, X86::VPUNPCKLQDQZ256rr },
5996 { X86::VUNPCKHPDZ256rm, X86::VUNPCKHPDZ256rm, X86::VPUNPCKHQDQZ256rm },
5997 { X86::VUNPCKHPDZ256rr, X86::VUNPCKHPDZ256rr, X86::VPUNPCKHQDQZ256rr },
5998 { X86::VUNPCKLPSZ256rm, X86::VUNPCKLPSZ256rm, X86::VPUNPCKLDQZ256rm },
5999 { X86::VUNPCKLPSZ256rr, X86::VUNPCKLPSZ256rr, X86::VPUNPCKLDQZ256rr },
6000 { X86::VUNPCKHPSZ256rm, X86::VUNPCKHPSZ256rm, X86::VPUNPCKHDQZ256rm },
6001 { X86::VUNPCKHPSZ256rr, X86::VUNPCKHPSZ256rr, X86::VPUNPCKHDQZ256rr },
6002 { X86::VUNPCKLPDZ128rm, X86::VUNPCKLPDZ128rm, X86::VPUNPCKLQDQZ128rm },
6003 { X86::VMOVLHPSZrr, X86::VUNPCKLPDZ128rr, X86::VPUNPCKLQDQZ128rr },
6004 { X86::VUNPCKHPDZ128rm, X86::VUNPCKHPDZ128rm, X86::VPUNPCKHQDQZ128rm },
6005 { X86::VUNPCKHPDZ128rr, X86::VUNPCKHPDZ128rr, X86::VPUNPCKHQDQZ128rr },
6006 { X86::VUNPCKLPSZ128rm, X86::VUNPCKLPSZ128rm, X86::VPUNPCKLDQZ128rm },
6007 { X86::VUNPCKLPSZ128rr, X86::VUNPCKLPSZ128rr, X86::VPUNPCKLDQZ128rr },
6008 { X86::VUNPCKHPSZ128rm, X86::VUNPCKHPSZ128rm, X86::VPUNPCKHDQZ128rm },
6009 { X86::VUNPCKHPSZ128rr, X86::VUNPCKHPSZ128rr, X86::VPUNPCKHDQZ128rr },
6010 { X86::VUNPCKLPDZrm, X86::VUNPCKLPDZrm, X86::VPUNPCKLQDQZrm },
6011 { X86::VUNPCKLPDZrr, X86::VUNPCKLPDZrr, X86::VPUNPCKLQDQZrr },
6012 { X86::VUNPCKHPDZrm, X86::VUNPCKHPDZrm, X86::VPUNPCKHQDQZrm },
6013 { X86::VUNPCKHPDZrr, X86::VUNPCKHPDZrr, X86::VPUNPCKHQDQZrr },
6014 { X86::VUNPCKLPSZrm, X86::VUNPCKLPSZrm, X86::VPUNPCKLDQZrm },
6015 { X86::VUNPCKLPSZrr, X86::VUNPCKLPSZrr, X86::VPUNPCKLDQZrr },
6016 { X86::VUNPCKHPSZrm, X86::VUNPCKHPSZrm, X86::VPUNPCKHDQZrm },
6017 { X86::VUNPCKHPSZrr, X86::VUNPCKHPSZrr, X86::VPUNPCKHDQZrr },
6018 { X86::VEXTRACTPSZmr, X86::VEXTRACTPSZmr, X86::VPEXTRDZmr },
6019 { X86::VEXTRACTPSZrr, X86::VEXTRACTPSZrr, X86::VPEXTRDZrr },
6022 static const uint16_t ReplaceableInstrsAVX2[][3] = {
6023 //PackedSingle PackedDouble PackedInt
6024 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
6025 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
6026 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
6027 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
6028 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
6029 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
6030 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
6031 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
6032 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
6033 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
6034 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6035 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6036 { X86::VMOVDDUPrm, X86::VMOVDDUPrm, X86::VPBROADCASTQrm},
6037 { X86::VMOVDDUPrr, X86::VMOVDDUPrr, X86::VPBROADCASTQrr},
6038 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6039 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6040 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6041 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
6042 { X86::VBROADCASTF128, X86::VBROADCASTF128, X86::VBROADCASTI128 },
6043 { X86::VBLENDPSYrri, X86::VBLENDPSYrri, X86::VPBLENDDYrri },
6044 { X86::VBLENDPSYrmi, X86::VBLENDPSYrmi, X86::VPBLENDDYrmi },
6045 { X86::VPERMILPSYmi, X86::VPERMILPSYmi, X86::VPSHUFDYmi },
6046 { X86::VPERMILPSYri, X86::VPERMILPSYri, X86::VPSHUFDYri },
6047 { X86::VUNPCKLPDYrm, X86::VUNPCKLPDYrm, X86::VPUNPCKLQDQYrm },
6048 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrr, X86::VPUNPCKLQDQYrr },
6049 { X86::VUNPCKHPDYrm, X86::VUNPCKHPDYrm, X86::VPUNPCKHQDQYrm },
6050 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrr, X86::VPUNPCKHQDQYrr },
6051 { X86::VUNPCKLPSYrm, X86::VUNPCKLPSYrm, X86::VPUNPCKLDQYrm },
6052 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrr, X86::VPUNPCKLDQYrr },
6053 { X86::VUNPCKHPSYrm, X86::VUNPCKHPSYrm, X86::VPUNPCKHDQYrm },
6054 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrr, X86::VPUNPCKHDQYrr },
6057 static const uint16_t ReplaceableInstrsFP[][3] = {
6058 //PackedSingle PackedDouble
6059 { X86::MOVLPSrm, X86::MOVLPDrm, X86::INSTRUCTION_LIST_END },
6060 { X86::MOVHPSrm, X86::MOVHPDrm, X86::INSTRUCTION_LIST_END },
6061 { X86::MOVHPSmr, X86::MOVHPDmr, X86::INSTRUCTION_LIST_END },
6062 { X86::VMOVLPSrm, X86::VMOVLPDrm, X86::INSTRUCTION_LIST_END },
6063 { X86::VMOVHPSrm, X86::VMOVHPDrm, X86::INSTRUCTION_LIST_END },
6064 { X86::VMOVHPSmr, X86::VMOVHPDmr, X86::INSTRUCTION_LIST_END },
6065 { X86::VMOVLPSZ128rm, X86::VMOVLPDZ128rm, X86::INSTRUCTION_LIST_END },
6066 { X86::VMOVHPSZ128rm, X86::VMOVHPDZ128rm, X86::INSTRUCTION_LIST_END },
6067 { X86::VMOVHPSZ128mr, X86::VMOVHPDZ128mr, X86::INSTRUCTION_LIST_END },
6070 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
6071 //PackedSingle PackedDouble PackedInt
6072 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6073 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6074 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
6075 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
6078 static const uint16_t ReplaceableInstrsAVX512[][4] = {
6079 // Two integer columns for 64-bit and 32-bit elements.
6080 //PackedSingle PackedDouble PackedInt PackedInt
6081 { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr },
6082 { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm },
6083 { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr },
6084 { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr },
6085 { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm },
6086 { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr },
6087 { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm },
6088 { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr },
6089 { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr },
6090 { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm },
6091 { X86::VMOVAPSZmr, X86::VMOVAPDZmr, X86::VMOVDQA64Zmr, X86::VMOVDQA32Zmr },
6092 { X86::VMOVAPSZrm, X86::VMOVAPDZrm, X86::VMOVDQA64Zrm, X86::VMOVDQA32Zrm },
6093 { X86::VMOVAPSZrr, X86::VMOVAPDZrr, X86::VMOVDQA64Zrr, X86::VMOVDQA32Zrr },
6094 { X86::VMOVUPSZmr, X86::VMOVUPDZmr, X86::VMOVDQU64Zmr, X86::VMOVDQU32Zmr },
6095 { X86::VMOVUPSZrm, X86::VMOVUPDZrm, X86::VMOVDQU64Zrm, X86::VMOVDQU32Zrm },
6098 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
6099 // Two integer columns for 64-bit and 32-bit elements.
6100 //PackedSingle PackedDouble PackedInt PackedInt
6101 { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
6102 { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
6103 { X86::VANDPSZ128rm, X86::VANDPDZ128rm, X86::VPANDQZ128rm, X86::VPANDDZ128rm },
6104 { X86::VANDPSZ128rr, X86::VANDPDZ128rr, X86::VPANDQZ128rr, X86::VPANDDZ128rr },
6105 { X86::VORPSZ128rm, X86::VORPDZ128rm, X86::VPORQZ128rm, X86::VPORDZ128rm },
6106 { X86::VORPSZ128rr, X86::VORPDZ128rr, X86::VPORQZ128rr, X86::VPORDZ128rr },
6107 { X86::VXORPSZ128rm, X86::VXORPDZ128rm, X86::VPXORQZ128rm, X86::VPXORDZ128rm },
6108 { X86::VXORPSZ128rr, X86::VXORPDZ128rr, X86::VPXORQZ128rr, X86::VPXORDZ128rr },
6109 { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
6110 { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
6111 { X86::VANDPSZ256rm, X86::VANDPDZ256rm, X86::VPANDQZ256rm, X86::VPANDDZ256rm },
6112 { X86::VANDPSZ256rr, X86::VANDPDZ256rr, X86::VPANDQZ256rr, X86::VPANDDZ256rr },
6113 { X86::VORPSZ256rm, X86::VORPDZ256rm, X86::VPORQZ256rm, X86::VPORDZ256rm },
6114 { X86::VORPSZ256rr, X86::VORPDZ256rr, X86::VPORQZ256rr, X86::VPORDZ256rr },
6115 { X86::VXORPSZ256rm, X86::VXORPDZ256rm, X86::VPXORQZ256rm, X86::VPXORDZ256rm },
6116 { X86::VXORPSZ256rr, X86::VXORPDZ256rr, X86::VPXORQZ256rr, X86::VPXORDZ256rr },
6117 { X86::VANDNPSZrm, X86::VANDNPDZrm, X86::VPANDNQZrm, X86::VPANDNDZrm },
6118 { X86::VANDNPSZrr, X86::VANDNPDZrr, X86::VPANDNQZrr, X86::VPANDNDZrr },
6119 { X86::VANDPSZrm, X86::VANDPDZrm, X86::VPANDQZrm, X86::VPANDDZrm },
6120 { X86::VANDPSZrr, X86::VANDPDZrr, X86::VPANDQZrr, X86::VPANDDZrr },
6121 { X86::VORPSZrm, X86::VORPDZrm, X86::VPORQZrm, X86::VPORDZrm },
6122 { X86::VORPSZrr, X86::VORPDZrr, X86::VPORQZrr, X86::VPORDZrr },
6123 { X86::VXORPSZrm, X86::VXORPDZrm, X86::VPXORQZrm, X86::VPXORDZrm },
6124 { X86::VXORPSZrr, X86::VXORPDZrr, X86::VPXORQZrr, X86::VPXORDZrr },
6127 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
6128 // Two integer columns for 64-bit and 32-bit elements.
6129 //PackedSingle PackedDouble
6130 //PackedInt PackedInt
6131 { X86::VANDNPSZ128rmk, X86::VANDNPDZ128rmk,
6132 X86::VPANDNQZ128rmk, X86::VPANDNDZ128rmk },
6133 { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
6134 X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
6135 { X86::VANDNPSZ128rrk, X86::VANDNPDZ128rrk,
6136 X86::VPANDNQZ128rrk, X86::VPANDNDZ128rrk },
6137 { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
6138 X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
6139 { X86::VANDPSZ128rmk, X86::VANDPDZ128rmk,
6140 X86::VPANDQZ128rmk, X86::VPANDDZ128rmk },
6141 { X86::VANDPSZ128rmkz, X86::VANDPDZ128rmkz,
6142 X86::VPANDQZ128rmkz, X86::VPANDDZ128rmkz },
6143 { X86::VANDPSZ128rrk, X86::VANDPDZ128rrk,
6144 X86::VPANDQZ128rrk, X86::VPANDDZ128rrk },
6145 { X86::VANDPSZ128rrkz, X86::VANDPDZ128rrkz,
6146 X86::VPANDQZ128rrkz, X86::VPANDDZ128rrkz },
6147 { X86::VORPSZ128rmk, X86::VORPDZ128rmk,
6148 X86::VPORQZ128rmk, X86::VPORDZ128rmk },
6149 { X86::VORPSZ128rmkz, X86::VORPDZ128rmkz,
6150 X86::VPORQZ128rmkz, X86::VPORDZ128rmkz },
6151 { X86::VORPSZ128rrk, X86::VORPDZ128rrk,
6152 X86::VPORQZ128rrk, X86::VPORDZ128rrk },
6153 { X86::VORPSZ128rrkz, X86::VORPDZ128rrkz,
6154 X86::VPORQZ128rrkz, X86::VPORDZ128rrkz },
6155 { X86::VXORPSZ128rmk, X86::VXORPDZ128rmk,
6156 X86::VPXORQZ128rmk, X86::VPXORDZ128rmk },
6157 { X86::VXORPSZ128rmkz, X86::VXORPDZ128rmkz,
6158 X86::VPXORQZ128rmkz, X86::VPXORDZ128rmkz },
6159 { X86::VXORPSZ128rrk, X86::VXORPDZ128rrk,
6160 X86::VPXORQZ128rrk, X86::VPXORDZ128rrk },
6161 { X86::VXORPSZ128rrkz, X86::VXORPDZ128rrkz,
6162 X86::VPXORQZ128rrkz, X86::VPXORDZ128rrkz },
6163 { X86::VANDNPSZ256rmk, X86::VANDNPDZ256rmk,
6164 X86::VPANDNQZ256rmk, X86::VPANDNDZ256rmk },
6165 { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
6166 X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
6167 { X86::VANDNPSZ256rrk, X86::VANDNPDZ256rrk,
6168 X86::VPANDNQZ256rrk, X86::VPANDNDZ256rrk },
6169 { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
6170 X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
6171 { X86::VANDPSZ256rmk, X86::VANDPDZ256rmk,
6172 X86::VPANDQZ256rmk, X86::VPANDDZ256rmk },
6173 { X86::VANDPSZ256rmkz, X86::VANDPDZ256rmkz,
6174 X86::VPANDQZ256rmkz, X86::VPANDDZ256rmkz },
6175 { X86::VANDPSZ256rrk, X86::VANDPDZ256rrk,
6176 X86::VPANDQZ256rrk, X86::VPANDDZ256rrk },
6177 { X86::VANDPSZ256rrkz, X86::VANDPDZ256rrkz,
6178 X86::VPANDQZ256rrkz, X86::VPANDDZ256rrkz },
6179 { X86::VORPSZ256rmk, X86::VORPDZ256rmk,
6180 X86::VPORQZ256rmk, X86::VPORDZ256rmk },
6181 { X86::VORPSZ256rmkz, X86::VORPDZ256rmkz,
6182 X86::VPORQZ256rmkz, X86::VPORDZ256rmkz },
6183 { X86::VORPSZ256rrk, X86::VORPDZ256rrk,
6184 X86::VPORQZ256rrk, X86::VPORDZ256rrk },
6185 { X86::VORPSZ256rrkz, X86::VORPDZ256rrkz,
6186 X86::VPORQZ256rrkz, X86::VPORDZ256rrkz },
6187 { X86::VXORPSZ256rmk, X86::VXORPDZ256rmk,
6188 X86::VPXORQZ256rmk, X86::VPXORDZ256rmk },
6189 { X86::VXORPSZ256rmkz, X86::VXORPDZ256rmkz,
6190 X86::VPXORQZ256rmkz, X86::VPXORDZ256rmkz },
6191 { X86::VXORPSZ256rrk, X86::VXORPDZ256rrk,
6192 X86::VPXORQZ256rrk, X86::VPXORDZ256rrk },
6193 { X86::VXORPSZ256rrkz, X86::VXORPDZ256rrkz,
6194 X86::VPXORQZ256rrkz, X86::VPXORDZ256rrkz },
6195 { X86::VANDNPSZrmk, X86::VANDNPDZrmk,
6196 X86::VPANDNQZrmk, X86::VPANDNDZrmk },
6197 { X86::VANDNPSZrmkz, X86::VANDNPDZrmkz,
6198 X86::VPANDNQZrmkz, X86::VPANDNDZrmkz },
6199 { X86::VANDNPSZrrk, X86::VANDNPDZrrk,
6200 X86::VPANDNQZrrk, X86::VPANDNDZrrk },
6201 { X86::VANDNPSZrrkz, X86::VANDNPDZrrkz,
6202 X86::VPANDNQZrrkz, X86::VPANDNDZrrkz },
6203 { X86::VANDPSZrmk, X86::VANDPDZrmk,
6204 X86::VPANDQZrmk, X86::VPANDDZrmk },
6205 { X86::VANDPSZrmkz, X86::VANDPDZrmkz,
6206 X86::VPANDQZrmkz, X86::VPANDDZrmkz },
6207 { X86::VANDPSZrrk, X86::VANDPDZrrk,
6208 X86::VPANDQZrrk, X86::VPANDDZrrk },
6209 { X86::VANDPSZrrkz, X86::VANDPDZrrkz,
6210 X86::VPANDQZrrkz, X86::VPANDDZrrkz },
6211 { X86::VORPSZrmk, X86::VORPDZrmk,
6212 X86::VPORQZrmk, X86::VPORDZrmk },
6213 { X86::VORPSZrmkz, X86::VORPDZrmkz,
6214 X86::VPORQZrmkz, X86::VPORDZrmkz },
6215 { X86::VORPSZrrk, X86::VORPDZrrk,
6216 X86::VPORQZrrk, X86::VPORDZrrk },
6217 { X86::VORPSZrrkz, X86::VORPDZrrkz,
6218 X86::VPORQZrrkz, X86::VPORDZrrkz },
6219 { X86::VXORPSZrmk, X86::VXORPDZrmk,
6220 X86::VPXORQZrmk, X86::VPXORDZrmk },
6221 { X86::VXORPSZrmkz, X86::VXORPDZrmkz,
6222 X86::VPXORQZrmkz, X86::VPXORDZrmkz },
6223 { X86::VXORPSZrrk, X86::VXORPDZrrk,
6224 X86::VPXORQZrrk, X86::VPXORDZrrk },
6225 { X86::VXORPSZrrkz, X86::VXORPDZrrkz,
6226 X86::VPXORQZrrkz, X86::VPXORDZrrkz },
6227 // Broadcast loads can be handled the same as masked operations to avoid
6228 // changing element size.
6229 { X86::VANDNPSZ128rmb, X86::VANDNPDZ128rmb,
6230 X86::VPANDNQZ128rmb, X86::VPANDNDZ128rmb },
6231 { X86::VANDPSZ128rmb, X86::VANDPDZ128rmb,
6232 X86::VPANDQZ128rmb, X86::VPANDDZ128rmb },
6233 { X86::VORPSZ128rmb, X86::VORPDZ128rmb,
6234 X86::VPORQZ128rmb, X86::VPORDZ128rmb },
6235 { X86::VXORPSZ128rmb, X86::VXORPDZ128rmb,
6236 X86::VPXORQZ128rmb, X86::VPXORDZ128rmb },
6237 { X86::VANDNPSZ256rmb, X86::VANDNPDZ256rmb,
6238 X86::VPANDNQZ256rmb, X86::VPANDNDZ256rmb },
6239 { X86::VANDPSZ256rmb, X86::VANDPDZ256rmb,
6240 X86::VPANDQZ256rmb, X86::VPANDDZ256rmb },
6241 { X86::VORPSZ256rmb, X86::VORPDZ256rmb,
6242 X86::VPORQZ256rmb, X86::VPORDZ256rmb },
6243 { X86::VXORPSZ256rmb, X86::VXORPDZ256rmb,
6244 X86::VPXORQZ256rmb, X86::VPXORDZ256rmb },
6245 { X86::VANDNPSZrmb, X86::VANDNPDZrmb,
6246 X86::VPANDNQZrmb, X86::VPANDNDZrmb },
6247 { X86::VANDPSZrmb, X86::VANDPDZrmb,
6248 X86::VPANDQZrmb, X86::VPANDDZrmb },
6249 { X86::VANDPSZrmb, X86::VANDPDZrmb,
6250 X86::VPANDQZrmb, X86::VPANDDZrmb },
6251 { X86::VORPSZrmb, X86::VORPDZrmb,
6252 X86::VPORQZrmb, X86::VPORDZrmb },
6253 { X86::VXORPSZrmb, X86::VXORPDZrmb,
6254 X86::VPXORQZrmb, X86::VPXORDZrmb },
6255 { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
6256 X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
6257 { X86::VANDPSZ128rmbk, X86::VANDPDZ128rmbk,
6258 X86::VPANDQZ128rmbk, X86::VPANDDZ128rmbk },
6259 { X86::VORPSZ128rmbk, X86::VORPDZ128rmbk,
6260 X86::VPORQZ128rmbk, X86::VPORDZ128rmbk },
6261 { X86::VXORPSZ128rmbk, X86::VXORPDZ128rmbk,
6262 X86::VPXORQZ128rmbk, X86::VPXORDZ128rmbk },
6263 { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
6264 X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
6265 { X86::VANDPSZ256rmbk, X86::VANDPDZ256rmbk,
6266 X86::VPANDQZ256rmbk, X86::VPANDDZ256rmbk },
6267 { X86::VORPSZ256rmbk, X86::VORPDZ256rmbk,
6268 X86::VPORQZ256rmbk, X86::VPORDZ256rmbk },
6269 { X86::VXORPSZ256rmbk, X86::VXORPDZ256rmbk,
6270 X86::VPXORQZ256rmbk, X86::VPXORDZ256rmbk },
6271 { X86::VANDNPSZrmbk, X86::VANDNPDZrmbk,
6272 X86::VPANDNQZrmbk, X86::VPANDNDZrmbk },
6273 { X86::VANDPSZrmbk, X86::VANDPDZrmbk,
6274 X86::VPANDQZrmbk, X86::VPANDDZrmbk },
6275 { X86::VANDPSZrmbk, X86::VANDPDZrmbk,
6276 X86::VPANDQZrmbk, X86::VPANDDZrmbk },
6277 { X86::VORPSZrmbk, X86::VORPDZrmbk,
6278 X86::VPORQZrmbk, X86::VPORDZrmbk },
6279 { X86::VXORPSZrmbk, X86::VXORPDZrmbk,
6280 X86::VPXORQZrmbk, X86::VPXORDZrmbk },
6281 { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
6282 X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
6283 { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
6284 X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
6285 { X86::VORPSZ128rmbkz, X86::VORPDZ128rmbkz,
6286 X86::VPORQZ128rmbkz, X86::VPORDZ128rmbkz },
6287 { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
6288 X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
6289 { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
6290 X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
6291 { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
6292 X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
6293 { X86::VORPSZ256rmbkz, X86::VORPDZ256rmbkz,
6294 X86::VPORQZ256rmbkz, X86::VPORDZ256rmbkz },
6295 { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
6296 X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
6297 { X86::VANDNPSZrmbkz, X86::VANDNPDZrmbkz,
6298 X86::VPANDNQZrmbkz, X86::VPANDNDZrmbkz },
6299 { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz,
6300 X86::VPANDQZrmbkz, X86::VPANDDZrmbkz },
6301 { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz,
6302 X86::VPANDQZrmbkz, X86::VPANDDZrmbkz },
6303 { X86::VORPSZrmbkz, X86::VORPDZrmbkz,
6304 X86::VPORQZrmbkz, X86::VPORDZrmbkz },
6305 { X86::VXORPSZrmbkz, X86::VXORPDZrmbkz,
6306 X86::VPXORQZrmbkz, X86::VPXORDZrmbkz },
6309 // NOTE: These should only be used by the custom domain methods.
6310 static const uint16_t ReplaceableBlendInstrs[][3] = {
6311 //PackedSingle PackedDouble PackedInt
6312 { X86::BLENDPSrmi, X86::BLENDPDrmi, X86::PBLENDWrmi },
6313 { X86::BLENDPSrri, X86::BLENDPDrri, X86::PBLENDWrri },
6314 { X86::VBLENDPSrmi, X86::VBLENDPDrmi, X86::VPBLENDWrmi },
6315 { X86::VBLENDPSrri, X86::VBLENDPDrri, X86::VPBLENDWrri },
6316 { X86::VBLENDPSYrmi, X86::VBLENDPDYrmi, X86::VPBLENDWYrmi },
6317 { X86::VBLENDPSYrri, X86::VBLENDPDYrri, X86::VPBLENDWYrri },
6319 static const uint16_t ReplaceableBlendAVX2Instrs[][3] = {
6320 //PackedSingle PackedDouble PackedInt
6321 { X86::VBLENDPSrmi, X86::VBLENDPDrmi, X86::VPBLENDDrmi },
6322 { X86::VBLENDPSrri, X86::VBLENDPDrri, X86::VPBLENDDrri },
6323 { X86::VBLENDPSYrmi, X86::VBLENDPDYrmi, X86::VPBLENDDYrmi },
6324 { X86::VBLENDPSYrri, X86::VBLENDPDYrri, X86::VPBLENDDYrri },
6327 // Special table for changing EVEX logic instructions to VEX.
6328 // TODO: Should we run EVEX->VEX earlier?
6329 static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = {
6330 // Two integer columns for 64-bit and 32-bit elements.
6331 //PackedSingle PackedDouble PackedInt PackedInt
6332 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
6333 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
6334 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDQZ128rm, X86::VPANDDZ128rm },
6335 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDQZ128rr, X86::VPANDDZ128rr },
6336 { X86::VORPSrm, X86::VORPDrm, X86::VPORQZ128rm, X86::VPORDZ128rm },
6337 { X86::VORPSrr, X86::VORPDrr, X86::VPORQZ128rr, X86::VPORDZ128rr },
6338 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORQZ128rm, X86::VPXORDZ128rm },
6339 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORQZ128rr, X86::VPXORDZ128rr },
6340 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
6341 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
6342 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDQZ256rm, X86::VPANDDZ256rm },
6343 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDQZ256rr, X86::VPANDDZ256rr },
6344 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORQZ256rm, X86::VPORDZ256rm },
6345 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORQZ256rr, X86::VPORDZ256rr },
6346 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORQZ256rm, X86::VPXORDZ256rm },
6347 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORQZ256rr, X86::VPXORDZ256rr },
6350 // FIXME: Some shuffle and unpack instructions have equivalents in different
6351 // domains, but they require a bit more work than just switching opcodes.
6353 static const uint16_t *lookup(unsigned opcode, unsigned domain,
6354 ArrayRef<uint16_t[3]> Table) {
6355 for (const uint16_t (&Row)[3] : Table)
6356 if (Row[domain-1] == opcode)
6361 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
6362 ArrayRef<uint16_t[4]> Table) {
6363 // If this is the integer domain make sure to check both integer columns.
6364 for (const uint16_t (&Row)[4] : Table)
6365 if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
6370 // Helper to attempt to widen/narrow blend masks.
6371 static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
6372 unsigned NewWidth, unsigned *pNewMask = nullptr) {
6373 assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
6374 "Illegal blend mask scale");
6375 unsigned NewMask = 0;
6377 if ((OldWidth % NewWidth) == 0) {
6378 unsigned Scale = OldWidth / NewWidth;
6379 unsigned SubMask = (1u << Scale) - 1;
6380 for (unsigned i = 0; i != NewWidth; ++i) {
6381 unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
6383 NewMask |= (1u << i);
6384 else if (Sub != 0x0)
6388 unsigned Scale = NewWidth / OldWidth;
6389 unsigned SubMask = (1u << Scale) - 1;
6390 for (unsigned i = 0; i != OldWidth; ++i) {
6391 if (OldMask & (1 << i)) {
6392 NewMask |= (SubMask << (i * Scale));
6398 *pNewMask = NewMask;
6402 uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
6403 unsigned Opcode = MI.getOpcode();
6404 unsigned NumOperands = MI.getDesc().getNumOperands();
6406 auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
6407 uint16_t validDomains = 0;
6408 if (MI.getOperand(NumOperands - 1).isImm()) {
6409 unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
6410 if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4))
6411 validDomains |= 0x2; // PackedSingle
6412 if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2))
6413 validDomains |= 0x4; // PackedDouble
6414 if (!Is256 || Subtarget.hasAVX2())
6415 validDomains |= 0x8; // PackedInt
6417 return validDomains;
6421 case X86::BLENDPDrmi:
6422 case X86::BLENDPDrri:
6423 case X86::VBLENDPDrmi:
6424 case X86::VBLENDPDrri:
6425 return GetBlendDomains(2, false);
6426 case X86::VBLENDPDYrmi:
6427 case X86::VBLENDPDYrri:
6428 return GetBlendDomains(4, true);
6429 case X86::BLENDPSrmi:
6430 case X86::BLENDPSrri:
6431 case X86::VBLENDPSrmi:
6432 case X86::VBLENDPSrri:
6433 case X86::VPBLENDDrmi:
6434 case X86::VPBLENDDrri:
6435 return GetBlendDomains(4, false);
6436 case X86::VBLENDPSYrmi:
6437 case X86::VBLENDPSYrri:
6438 case X86::VPBLENDDYrmi:
6439 case X86::VPBLENDDYrri:
6440 return GetBlendDomains(8, true);
6441 case X86::PBLENDWrmi:
6442 case X86::PBLENDWrri:
6443 case X86::VPBLENDWrmi:
6444 case X86::VPBLENDWrri:
6445 // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
6446 case X86::VPBLENDWYrmi:
6447 case X86::VPBLENDWYrri:
6448 return GetBlendDomains(8, false);
6449 case X86::VPANDDZ128rr: case X86::VPANDDZ128rm:
6450 case X86::VPANDDZ256rr: case X86::VPANDDZ256rm:
6451 case X86::VPANDQZ128rr: case X86::VPANDQZ128rm:
6452 case X86::VPANDQZ256rr: case X86::VPANDQZ256rm:
6453 case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
6454 case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
6455 case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
6456 case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
6457 case X86::VPORDZ128rr: case X86::VPORDZ128rm:
6458 case X86::VPORDZ256rr: case X86::VPORDZ256rm:
6459 case X86::VPORQZ128rr: case X86::VPORQZ128rm:
6460 case X86::VPORQZ256rr: case X86::VPORQZ256rm:
6461 case X86::VPXORDZ128rr: case X86::VPXORDZ128rm:
6462 case X86::VPXORDZ256rr: case X86::VPXORDZ256rm:
6463 case X86::VPXORQZ128rr: case X86::VPXORQZ128rm:
6464 case X86::VPXORQZ256rr: case X86::VPXORQZ256rm:
6465 // If we don't have DQI see if we can still switch from an EVEX integer
6466 // instruction to a VEX floating point instruction.
6467 if (Subtarget.hasDQI())
6470 if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
6472 if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
6474 // Register forms will have 3 operands. Memory form will have more.
6475 if (NumOperands == 3 &&
6476 RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
6479 // All domains are valid.
6481 case X86::MOVHLPSrr:
6482 // We can swap domains when both inputs are the same register.
6483 // FIXME: This doesn't catch all the cases we would like. If the input
6484 // register isn't KILLed by the instruction, the two address instruction
6485 // pass puts a COPY on one input. The other input uses the original
6486 // register. This prevents the same physical register from being used by
6488 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6489 MI.getOperand(0).getSubReg() == 0 &&
6490 MI.getOperand(1).getSubReg() == 0 &&
6491 MI.getOperand(2).getSubReg() == 0)
6494 case X86::SHUFPDrri:
6500 bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
6501 unsigned Domain) const {
6502 assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
6503 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6504 assert(dom && "Not an SSE instruction");
6506 unsigned Opcode = MI.getOpcode();
6507 unsigned NumOperands = MI.getDesc().getNumOperands();
6509 auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
6510 if (MI.getOperand(NumOperands - 1).isImm()) {
6511 unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
6512 Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
6513 unsigned NewImm = Imm;
6515 const uint16_t *table = lookup(Opcode, dom, ReplaceableBlendInstrs);
6517 table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
6519 if (Domain == 1) { // PackedSingle
6520 AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
6521 } else if (Domain == 2) { // PackedDouble
6522 AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2, &NewImm);
6523 } else if (Domain == 3) { // PackedInt
6524 if (Subtarget.hasAVX2()) {
6525 // If we are already VPBLENDW use that, else use VPBLENDD.
6526 if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
6527 table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
6528 AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
6531 assert(!Is256 && "128-bit vector expected");
6532 AdjustBlendMask(Imm, ImmWidth, 8, &NewImm);
6536 assert(table && table[Domain - 1] && "Unknown domain op");
6537 MI.setDesc(get(table[Domain - 1]));
6538 MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
6544 case X86::BLENDPDrmi:
6545 case X86::BLENDPDrri:
6546 case X86::VBLENDPDrmi:
6547 case X86::VBLENDPDrri:
6548 return SetBlendDomain(2, false);
6549 case X86::VBLENDPDYrmi:
6550 case X86::VBLENDPDYrri:
6551 return SetBlendDomain(4, true);
6552 case X86::BLENDPSrmi:
6553 case X86::BLENDPSrri:
6554 case X86::VBLENDPSrmi:
6555 case X86::VBLENDPSrri:
6556 case X86::VPBLENDDrmi:
6557 case X86::VPBLENDDrri:
6558 return SetBlendDomain(4, false);
6559 case X86::VBLENDPSYrmi:
6560 case X86::VBLENDPSYrri:
6561 case X86::VPBLENDDYrmi:
6562 case X86::VPBLENDDYrri:
6563 return SetBlendDomain(8, true);
6564 case X86::PBLENDWrmi:
6565 case X86::PBLENDWrri:
6566 case X86::VPBLENDWrmi:
6567 case X86::VPBLENDWrri:
6568 return SetBlendDomain(8, false);
6569 case X86::VPBLENDWYrmi:
6570 case X86::VPBLENDWYrri:
6571 return SetBlendDomain(16, true);
6572 case X86::VPANDDZ128rr: case X86::VPANDDZ128rm:
6573 case X86::VPANDDZ256rr: case X86::VPANDDZ256rm:
6574 case X86::VPANDQZ128rr: case X86::VPANDQZ128rm:
6575 case X86::VPANDQZ256rr: case X86::VPANDQZ256rm:
6576 case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
6577 case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
6578 case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
6579 case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
6580 case X86::VPORDZ128rr: case X86::VPORDZ128rm:
6581 case X86::VPORDZ256rr: case X86::VPORDZ256rm:
6582 case X86::VPORQZ128rr: case X86::VPORQZ128rm:
6583 case X86::VPORQZ256rr: case X86::VPORQZ256rm:
6584 case X86::VPXORDZ128rr: case X86::VPXORDZ128rm:
6585 case X86::VPXORDZ256rr: case X86::VPXORDZ256rm:
6586 case X86::VPXORQZ128rr: case X86::VPXORQZ128rm:
6587 case X86::VPXORQZ256rr: case X86::VPXORQZ256rm: {
6588 // Without DQI, convert EVEX instructions to VEX instructions.
6589 if (Subtarget.hasDQI())
6592 const uint16_t *table = lookupAVX512(MI.getOpcode(), dom,
6593 ReplaceableCustomAVX512LogicInstrs);
6594 assert(table && "Instruction not found in table?");
6595 // Don't change integer Q instructions to D instructions and
6596 // use D intructions if we started with a PS instruction.
6597 if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6599 MI.setDesc(get(table[Domain - 1]));
6602 case X86::UNPCKHPDrr:
6603 case X86::MOVHLPSrr:
6604 // We just need to commute the instruction which will switch the domains.
6605 if (Domain != dom && Domain != 3 &&
6606 MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6607 MI.getOperand(0).getSubReg() == 0 &&
6608 MI.getOperand(1).getSubReg() == 0 &&
6609 MI.getOperand(2).getSubReg() == 0) {
6610 commuteInstruction(MI, false);
6613 // We must always return true for MOVHLPSrr.
6614 if (Opcode == X86::MOVHLPSrr)
6617 case X86::SHUFPDrri: {
6619 unsigned Imm = MI.getOperand(3).getImm();
6620 unsigned NewImm = 0x44;
6621 if (Imm & 1) NewImm |= 0x0a;
6622 if (Imm & 2) NewImm |= 0xa0;
6623 MI.getOperand(3).setImm(NewImm);
6624 MI.setDesc(get(X86::SHUFPSrri));
6632 std::pair<uint16_t, uint16_t>
6633 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
6634 uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6635 unsigned opcode = MI.getOpcode();
6636 uint16_t validDomains = 0;
6638 // Attempt to match for custom instructions.
6639 validDomains = getExecutionDomainCustom(MI);
6641 return std::make_pair(domain, validDomains);
6643 if (lookup(opcode, domain, ReplaceableInstrs)) {
6645 } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
6646 validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
6647 } else if (lookup(opcode, domain, ReplaceableInstrsFP)) {
6649 } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
6650 // Insert/extract instructions should only effect domain if AVX2
6652 if (!Subtarget.hasAVX2())
6653 return std::make_pair(0, 0);
6655 } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
6657 } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
6658 ReplaceableInstrsAVX512DQ)) {
6660 } else if (Subtarget.hasDQI()) {
6661 if (const uint16_t *table = lookupAVX512(opcode, domain,
6662 ReplaceableInstrsAVX512DQMasked)) {
6663 if (domain == 1 || (domain == 3 && table[3] == opcode))
6670 return std::make_pair(domain, validDomains);
6673 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
6674 assert(Domain>0 && Domain<4 && "Invalid execution domain");
6675 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6676 assert(dom && "Not an SSE instruction");
6678 // Attempt to match for custom instructions.
6679 if (setExecutionDomainCustom(MI, Domain))
6682 const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
6683 if (!table) { // try the other table
6684 assert((Subtarget.hasAVX2() || Domain < 3) &&
6685 "256-bit vector operations only available in AVX2");
6686 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
6688 if (!table) { // try the FP table
6689 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsFP);
6690 assert((!table || Domain < 3) &&
6691 "Can only select PackedSingle or PackedDouble");
6693 if (!table) { // try the other table
6694 assert(Subtarget.hasAVX2() &&
6695 "256-bit insert/extract only available in AVX2");
6696 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
6698 if (!table) { // try the AVX512 table
6699 assert(Subtarget.hasAVX512() && "Requires AVX-512");
6700 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
6701 // Don't change integer Q instructions to D instructions.
6702 if (table && Domain == 3 && table[3] == MI.getOpcode())
6705 if (!table) { // try the AVX512DQ table
6706 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
6707 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
6708 // Don't change integer Q instructions to D instructions and
6709 // use D intructions if we started with a PS instruction.
6710 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6713 if (!table) { // try the AVX512DQMasked table
6714 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
6715 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
6716 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6719 assert(table && "Cannot change domain");
6720 MI.setDesc(get(table[Domain - 1]));
6723 /// Return the noop instruction to use for a noop.
6724 void X86InstrInfo::getNoop(MCInst &NopInst) const {
6725 NopInst.setOpcode(X86::NOOP);
6728 bool X86InstrInfo::isHighLatencyDef(int opc) const {
6730 default: return false;
6736 case X86::DIVSDrm_Int:
6738 case X86::DIVSDrr_Int:
6740 case X86::DIVSSrm_Int:
6742 case X86::DIVSSrr_Int:
6748 case X86::SQRTSDm_Int:
6750 case X86::SQRTSDr_Int:
6752 case X86::SQRTSSm_Int:
6754 case X86::SQRTSSr_Int:
6755 // AVX instructions with high latency
6758 case X86::VDIVPDYrm:
6759 case X86::VDIVPDYrr:
6762 case X86::VDIVPSYrm:
6763 case X86::VDIVPSYrr:
6765 case X86::VDIVSDrm_Int:
6767 case X86::VDIVSDrr_Int:
6769 case X86::VDIVSSrm_Int:
6771 case X86::VDIVSSrr_Int:
6774 case X86::VSQRTPDYm:
6775 case X86::VSQRTPDYr:
6778 case X86::VSQRTPSYm:
6779 case X86::VSQRTPSYr:
6781 case X86::VSQRTSDm_Int:
6783 case X86::VSQRTSDr_Int:
6785 case X86::VSQRTSSm_Int:
6787 case X86::VSQRTSSr_Int:
6788 // AVX512 instructions with high latency
6789 case X86::VDIVPDZ128rm:
6790 case X86::VDIVPDZ128rmb:
6791 case X86::VDIVPDZ128rmbk:
6792 case X86::VDIVPDZ128rmbkz:
6793 case X86::VDIVPDZ128rmk:
6794 case X86::VDIVPDZ128rmkz:
6795 case X86::VDIVPDZ128rr:
6796 case X86::VDIVPDZ128rrk:
6797 case X86::VDIVPDZ128rrkz:
6798 case X86::VDIVPDZ256rm:
6799 case X86::VDIVPDZ256rmb:
6800 case X86::VDIVPDZ256rmbk:
6801 case X86::VDIVPDZ256rmbkz:
6802 case X86::VDIVPDZ256rmk:
6803 case X86::VDIVPDZ256rmkz:
6804 case X86::VDIVPDZ256rr:
6805 case X86::VDIVPDZ256rrk:
6806 case X86::VDIVPDZ256rrkz:
6807 case X86::VDIVPDZrrb:
6808 case X86::VDIVPDZrrbk:
6809 case X86::VDIVPDZrrbkz:
6810 case X86::VDIVPDZrm:
6811 case X86::VDIVPDZrmb:
6812 case X86::VDIVPDZrmbk:
6813 case X86::VDIVPDZrmbkz:
6814 case X86::VDIVPDZrmk:
6815 case X86::VDIVPDZrmkz:
6816 case X86::VDIVPDZrr:
6817 case X86::VDIVPDZrrk:
6818 case X86::VDIVPDZrrkz:
6819 case X86::VDIVPSZ128rm:
6820 case X86::VDIVPSZ128rmb:
6821 case X86::VDIVPSZ128rmbk:
6822 case X86::VDIVPSZ128rmbkz:
6823 case X86::VDIVPSZ128rmk:
6824 case X86::VDIVPSZ128rmkz:
6825 case X86::VDIVPSZ128rr:
6826 case X86::VDIVPSZ128rrk:
6827 case X86::VDIVPSZ128rrkz:
6828 case X86::VDIVPSZ256rm:
6829 case X86::VDIVPSZ256rmb:
6830 case X86::VDIVPSZ256rmbk:
6831 case X86::VDIVPSZ256rmbkz:
6832 case X86::VDIVPSZ256rmk:
6833 case X86::VDIVPSZ256rmkz:
6834 case X86::VDIVPSZ256rr:
6835 case X86::VDIVPSZ256rrk:
6836 case X86::VDIVPSZ256rrkz:
6837 case X86::VDIVPSZrrb:
6838 case X86::VDIVPSZrrbk:
6839 case X86::VDIVPSZrrbkz:
6840 case X86::VDIVPSZrm:
6841 case X86::VDIVPSZrmb:
6842 case X86::VDIVPSZrmbk:
6843 case X86::VDIVPSZrmbkz:
6844 case X86::VDIVPSZrmk:
6845 case X86::VDIVPSZrmkz:
6846 case X86::VDIVPSZrr:
6847 case X86::VDIVPSZrrk:
6848 case X86::VDIVPSZrrkz:
6849 case X86::VDIVSDZrm:
6850 case X86::VDIVSDZrr:
6851 case X86::VDIVSDZrm_Int:
6852 case X86::VDIVSDZrm_Intk:
6853 case X86::VDIVSDZrm_Intkz:
6854 case X86::VDIVSDZrr_Int:
6855 case X86::VDIVSDZrr_Intk:
6856 case X86::VDIVSDZrr_Intkz:
6857 case X86::VDIVSDZrrb_Int:
6858 case X86::VDIVSDZrrb_Intk:
6859 case X86::VDIVSDZrrb_Intkz:
6860 case X86::VDIVSSZrm:
6861 case X86::VDIVSSZrr:
6862 case X86::VDIVSSZrm_Int:
6863 case X86::VDIVSSZrm_Intk:
6864 case X86::VDIVSSZrm_Intkz:
6865 case X86::VDIVSSZrr_Int:
6866 case X86::VDIVSSZrr_Intk:
6867 case X86::VDIVSSZrr_Intkz:
6868 case X86::VDIVSSZrrb_Int:
6869 case X86::VDIVSSZrrb_Intk:
6870 case X86::VDIVSSZrrb_Intkz:
6871 case X86::VSQRTPDZ128m:
6872 case X86::VSQRTPDZ128mb:
6873 case X86::VSQRTPDZ128mbk:
6874 case X86::VSQRTPDZ128mbkz:
6875 case X86::VSQRTPDZ128mk:
6876 case X86::VSQRTPDZ128mkz:
6877 case X86::VSQRTPDZ128r:
6878 case X86::VSQRTPDZ128rk:
6879 case X86::VSQRTPDZ128rkz:
6880 case X86::VSQRTPDZ256m:
6881 case X86::VSQRTPDZ256mb:
6882 case X86::VSQRTPDZ256mbk:
6883 case X86::VSQRTPDZ256mbkz:
6884 case X86::VSQRTPDZ256mk:
6885 case X86::VSQRTPDZ256mkz:
6886 case X86::VSQRTPDZ256r:
6887 case X86::VSQRTPDZ256rk:
6888 case X86::VSQRTPDZ256rkz:
6889 case X86::VSQRTPDZm:
6890 case X86::VSQRTPDZmb:
6891 case X86::VSQRTPDZmbk:
6892 case X86::VSQRTPDZmbkz:
6893 case X86::VSQRTPDZmk:
6894 case X86::VSQRTPDZmkz:
6895 case X86::VSQRTPDZr:
6896 case X86::VSQRTPDZrb:
6897 case X86::VSQRTPDZrbk:
6898 case X86::VSQRTPDZrbkz:
6899 case X86::VSQRTPDZrk:
6900 case X86::VSQRTPDZrkz:
6901 case X86::VSQRTPSZ128m:
6902 case X86::VSQRTPSZ128mb:
6903 case X86::VSQRTPSZ128mbk:
6904 case X86::VSQRTPSZ128mbkz:
6905 case X86::VSQRTPSZ128mk:
6906 case X86::VSQRTPSZ128mkz:
6907 case X86::VSQRTPSZ128r:
6908 case X86::VSQRTPSZ128rk:
6909 case X86::VSQRTPSZ128rkz:
6910 case X86::VSQRTPSZ256m:
6911 case X86::VSQRTPSZ256mb:
6912 case X86::VSQRTPSZ256mbk:
6913 case X86::VSQRTPSZ256mbkz:
6914 case X86::VSQRTPSZ256mk:
6915 case X86::VSQRTPSZ256mkz:
6916 case X86::VSQRTPSZ256r:
6917 case X86::VSQRTPSZ256rk:
6918 case X86::VSQRTPSZ256rkz:
6919 case X86::VSQRTPSZm:
6920 case X86::VSQRTPSZmb:
6921 case X86::VSQRTPSZmbk:
6922 case X86::VSQRTPSZmbkz:
6923 case X86::VSQRTPSZmk:
6924 case X86::VSQRTPSZmkz:
6925 case X86::VSQRTPSZr:
6926 case X86::VSQRTPSZrb:
6927 case X86::VSQRTPSZrbk:
6928 case X86::VSQRTPSZrbkz:
6929 case X86::VSQRTPSZrk:
6930 case X86::VSQRTPSZrkz:
6931 case X86::VSQRTSDZm:
6932 case X86::VSQRTSDZm_Int:
6933 case X86::VSQRTSDZm_Intk:
6934 case X86::VSQRTSDZm_Intkz:
6935 case X86::VSQRTSDZr:
6936 case X86::VSQRTSDZr_Int:
6937 case X86::VSQRTSDZr_Intk:
6938 case X86::VSQRTSDZr_Intkz:
6939 case X86::VSQRTSDZrb_Int:
6940 case X86::VSQRTSDZrb_Intk:
6941 case X86::VSQRTSDZrb_Intkz:
6942 case X86::VSQRTSSZm:
6943 case X86::VSQRTSSZm_Int:
6944 case X86::VSQRTSSZm_Intk:
6945 case X86::VSQRTSSZm_Intkz:
6946 case X86::VSQRTSSZr:
6947 case X86::VSQRTSSZr_Int:
6948 case X86::VSQRTSSZr_Intk:
6949 case X86::VSQRTSSZr_Intkz:
6950 case X86::VSQRTSSZrb_Int:
6951 case X86::VSQRTSSZrb_Intk:
6952 case X86::VSQRTSSZrb_Intkz:
6954 case X86::VGATHERDPDYrm:
6955 case X86::VGATHERDPDZ128rm:
6956 case X86::VGATHERDPDZ256rm:
6957 case X86::VGATHERDPDZrm:
6958 case X86::VGATHERDPDrm:
6959 case X86::VGATHERDPSYrm:
6960 case X86::VGATHERDPSZ128rm:
6961 case X86::VGATHERDPSZ256rm:
6962 case X86::VGATHERDPSZrm:
6963 case X86::VGATHERDPSrm:
6964 case X86::VGATHERPF0DPDm:
6965 case X86::VGATHERPF0DPSm:
6966 case X86::VGATHERPF0QPDm:
6967 case X86::VGATHERPF0QPSm:
6968 case X86::VGATHERPF1DPDm:
6969 case X86::VGATHERPF1DPSm:
6970 case X86::VGATHERPF1QPDm:
6971 case X86::VGATHERPF1QPSm:
6972 case X86::VGATHERQPDYrm:
6973 case X86::VGATHERQPDZ128rm:
6974 case X86::VGATHERQPDZ256rm:
6975 case X86::VGATHERQPDZrm:
6976 case X86::VGATHERQPDrm:
6977 case X86::VGATHERQPSYrm:
6978 case X86::VGATHERQPSZ128rm:
6979 case X86::VGATHERQPSZ256rm:
6980 case X86::VGATHERQPSZrm:
6981 case X86::VGATHERQPSrm:
6982 case X86::VPGATHERDDYrm:
6983 case X86::VPGATHERDDZ128rm:
6984 case X86::VPGATHERDDZ256rm:
6985 case X86::VPGATHERDDZrm:
6986 case X86::VPGATHERDDrm:
6987 case X86::VPGATHERDQYrm:
6988 case X86::VPGATHERDQZ128rm:
6989 case X86::VPGATHERDQZ256rm:
6990 case X86::VPGATHERDQZrm:
6991 case X86::VPGATHERDQrm:
6992 case X86::VPGATHERQDYrm:
6993 case X86::VPGATHERQDZ128rm:
6994 case X86::VPGATHERQDZ256rm:
6995 case X86::VPGATHERQDZrm:
6996 case X86::VPGATHERQDrm:
6997 case X86::VPGATHERQQYrm:
6998 case X86::VPGATHERQQZ128rm:
6999 case X86::VPGATHERQQZ256rm:
7000 case X86::VPGATHERQQZrm:
7001 case X86::VPGATHERQQrm:
7002 case X86::VSCATTERDPDZ128mr:
7003 case X86::VSCATTERDPDZ256mr:
7004 case X86::VSCATTERDPDZmr:
7005 case X86::VSCATTERDPSZ128mr:
7006 case X86::VSCATTERDPSZ256mr:
7007 case X86::VSCATTERDPSZmr:
7008 case X86::VSCATTERPF0DPDm:
7009 case X86::VSCATTERPF0DPSm:
7010 case X86::VSCATTERPF0QPDm:
7011 case X86::VSCATTERPF0QPSm:
7012 case X86::VSCATTERPF1DPDm:
7013 case X86::VSCATTERPF1DPSm:
7014 case X86::VSCATTERPF1QPDm:
7015 case X86::VSCATTERPF1QPSm:
7016 case X86::VSCATTERQPDZ128mr:
7017 case X86::VSCATTERQPDZ256mr:
7018 case X86::VSCATTERQPDZmr:
7019 case X86::VSCATTERQPSZ128mr:
7020 case X86::VSCATTERQPSZ256mr:
7021 case X86::VSCATTERQPSZmr:
7022 case X86::VPSCATTERDDZ128mr:
7023 case X86::VPSCATTERDDZ256mr:
7024 case X86::VPSCATTERDDZmr:
7025 case X86::VPSCATTERDQZ128mr:
7026 case X86::VPSCATTERDQZ256mr:
7027 case X86::VPSCATTERDQZmr:
7028 case X86::VPSCATTERQDZ128mr:
7029 case X86::VPSCATTERQDZ256mr:
7030 case X86::VPSCATTERQDZmr:
7031 case X86::VPSCATTERQQZ128mr:
7032 case X86::VPSCATTERQQZ256mr:
7033 case X86::VPSCATTERQQZmr:
7038 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
7039 const MachineRegisterInfo *MRI,
7040 const MachineInstr &DefMI,
7042 const MachineInstr &UseMI,
7043 unsigned UseIdx) const {
7044 return isHighLatencyDef(DefMI.getOpcode());
7047 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
7048 const MachineBasicBlock *MBB) const {
7049 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
7050 "Reassociation needs binary operators");
7052 // Integer binary math/logic instructions have a third source operand:
7053 // the EFLAGS register. That operand must be both defined here and never
7054 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7055 // not change anything because rearranging the operands could affect other
7056 // instructions that depend on the exact status flags (zero, sign, etc.)
7057 // that are set by using these particular operands with this operation.
7058 if (Inst.getNumOperands() == 4) {
7059 assert(Inst.getOperand(3).isReg() &&
7060 Inst.getOperand(3).getReg() == X86::EFLAGS &&
7061 "Unexpected operand in reassociable instruction");
7062 if (!Inst.getOperand(3).isDead())
7066 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
7069 // TODO: There are many more machine instruction opcodes to match:
7070 // 1. Other data types (integer, vectors)
7071 // 2. Other math / logic operations (xor, or)
7072 // 3. Other forms of the same operation (intrinsics and other variants)
7073 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
7074 switch (Inst.getOpcode()) {
7119 case X86::VPANDDZ128rr:
7120 case X86::VPANDDZ256rr:
7121 case X86::VPANDDZrr:
7122 case X86::VPANDQZ128rr:
7123 case X86::VPANDQZ256rr:
7124 case X86::VPANDQZrr:
7127 case X86::VPORDZ128rr:
7128 case X86::VPORDZ256rr:
7130 case X86::VPORQZ128rr:
7131 case X86::VPORQZ256rr:
7135 case X86::VPXORDZ128rr:
7136 case X86::VPXORDZ256rr:
7137 case X86::VPXORDZrr:
7138 case X86::VPXORQZ128rr:
7139 case X86::VPXORQZ256rr:
7140 case X86::VPXORQZrr:
7143 case X86::VANDPDYrr:
7144 case X86::VANDPSYrr:
7145 case X86::VANDPDZ128rr:
7146 case X86::VANDPSZ128rr:
7147 case X86::VANDPDZ256rr:
7148 case X86::VANDPSZ256rr:
7149 case X86::VANDPDZrr:
7150 case X86::VANDPSZrr:
7155 case X86::VORPDZ128rr:
7156 case X86::VORPSZ128rr:
7157 case X86::VORPDZ256rr:
7158 case X86::VORPSZ256rr:
7163 case X86::VXORPDYrr:
7164 case X86::VXORPSYrr:
7165 case X86::VXORPDZ128rr:
7166 case X86::VXORPSZ128rr:
7167 case X86::VXORPDZ256rr:
7168 case X86::VXORPSZ256rr:
7169 case X86::VXORPDZrr:
7170 case X86::VXORPSZrr:
7191 case X86::VPADDBYrr:
7192 case X86::VPADDWYrr:
7193 case X86::VPADDDYrr:
7194 case X86::VPADDQYrr:
7195 case X86::VPADDBZ128rr:
7196 case X86::VPADDWZ128rr:
7197 case X86::VPADDDZ128rr:
7198 case X86::VPADDQZ128rr:
7199 case X86::VPADDBZ256rr:
7200 case X86::VPADDWZ256rr:
7201 case X86::VPADDDZ256rr:
7202 case X86::VPADDQZ256rr:
7203 case X86::VPADDBZrr:
7204 case X86::VPADDWZrr:
7205 case X86::VPADDDZrr:
7206 case X86::VPADDQZrr:
7207 case X86::VPMULLWrr:
7208 case X86::VPMULLWYrr:
7209 case X86::VPMULLWZ128rr:
7210 case X86::VPMULLWZ256rr:
7211 case X86::VPMULLWZrr:
7212 case X86::VPMULLDrr:
7213 case X86::VPMULLDYrr:
7214 case X86::VPMULLDZ128rr:
7215 case X86::VPMULLDZ256rr:
7216 case X86::VPMULLDZrr:
7217 case X86::VPMULLQZ128rr:
7218 case X86::VPMULLQZ256rr:
7219 case X86::VPMULLQZrr:
7220 case X86::VPMAXSBrr:
7221 case X86::VPMAXSBYrr:
7222 case X86::VPMAXSBZ128rr:
7223 case X86::VPMAXSBZ256rr:
7224 case X86::VPMAXSBZrr:
7225 case X86::VPMAXSDrr:
7226 case X86::VPMAXSDYrr:
7227 case X86::VPMAXSDZ128rr:
7228 case X86::VPMAXSDZ256rr:
7229 case X86::VPMAXSDZrr:
7230 case X86::VPMAXSQZ128rr:
7231 case X86::VPMAXSQZ256rr:
7232 case X86::VPMAXSQZrr:
7233 case X86::VPMAXSWrr:
7234 case X86::VPMAXSWYrr:
7235 case X86::VPMAXSWZ128rr:
7236 case X86::VPMAXSWZ256rr:
7237 case X86::VPMAXSWZrr:
7238 case X86::VPMAXUBrr:
7239 case X86::VPMAXUBYrr:
7240 case X86::VPMAXUBZ128rr:
7241 case X86::VPMAXUBZ256rr:
7242 case X86::VPMAXUBZrr:
7243 case X86::VPMAXUDrr:
7244 case X86::VPMAXUDYrr:
7245 case X86::VPMAXUDZ128rr:
7246 case X86::VPMAXUDZ256rr:
7247 case X86::VPMAXUDZrr:
7248 case X86::VPMAXUQZ128rr:
7249 case X86::VPMAXUQZ256rr:
7250 case X86::VPMAXUQZrr:
7251 case X86::VPMAXUWrr:
7252 case X86::VPMAXUWYrr:
7253 case X86::VPMAXUWZ128rr:
7254 case X86::VPMAXUWZ256rr:
7255 case X86::VPMAXUWZrr:
7256 case X86::VPMINSBrr:
7257 case X86::VPMINSBYrr:
7258 case X86::VPMINSBZ128rr:
7259 case X86::VPMINSBZ256rr:
7260 case X86::VPMINSBZrr:
7261 case X86::VPMINSDrr:
7262 case X86::VPMINSDYrr:
7263 case X86::VPMINSDZ128rr:
7264 case X86::VPMINSDZ256rr:
7265 case X86::VPMINSDZrr:
7266 case X86::VPMINSQZ128rr:
7267 case X86::VPMINSQZ256rr:
7268 case X86::VPMINSQZrr:
7269 case X86::VPMINSWrr:
7270 case X86::VPMINSWYrr:
7271 case X86::VPMINSWZ128rr:
7272 case X86::VPMINSWZ256rr:
7273 case X86::VPMINSWZrr:
7274 case X86::VPMINUBrr:
7275 case X86::VPMINUBYrr:
7276 case X86::VPMINUBZ128rr:
7277 case X86::VPMINUBZ256rr:
7278 case X86::VPMINUBZrr:
7279 case X86::VPMINUDrr:
7280 case X86::VPMINUDYrr:
7281 case X86::VPMINUDZ128rr:
7282 case X86::VPMINUDZ256rr:
7283 case X86::VPMINUDZrr:
7284 case X86::VPMINUQZ128rr:
7285 case X86::VPMINUQZ256rr:
7286 case X86::VPMINUQZrr:
7287 case X86::VPMINUWrr:
7288 case X86::VPMINUWYrr:
7289 case X86::VPMINUWZ128rr:
7290 case X86::VPMINUWZ256rr:
7291 case X86::VPMINUWZrr:
7292 // Normal min/max instructions are not commutative because of NaN and signed
7293 // zero semantics, but these are. Thus, there's no need to check for global
7294 // relaxed math; the instructions themselves have the properties we need.
7303 case X86::VMAXCPDrr:
7304 case X86::VMAXCPSrr:
7305 case X86::VMAXCPDYrr:
7306 case X86::VMAXCPSYrr:
7307 case X86::VMAXCPDZ128rr:
7308 case X86::VMAXCPSZ128rr:
7309 case X86::VMAXCPDZ256rr:
7310 case X86::VMAXCPSZ256rr:
7311 case X86::VMAXCPDZrr:
7312 case X86::VMAXCPSZrr:
7313 case X86::VMAXCSDrr:
7314 case X86::VMAXCSSrr:
7315 case X86::VMAXCSDZrr:
7316 case X86::VMAXCSSZrr:
7317 case X86::VMINCPDrr:
7318 case X86::VMINCPSrr:
7319 case X86::VMINCPDYrr:
7320 case X86::VMINCPSYrr:
7321 case X86::VMINCPDZ128rr:
7322 case X86::VMINCPSZ128rr:
7323 case X86::VMINCPDZ256rr:
7324 case X86::VMINCPSZ256rr:
7325 case X86::VMINCPDZrr:
7326 case X86::VMINCPSZrr:
7327 case X86::VMINCSDrr:
7328 case X86::VMINCSSrr:
7329 case X86::VMINCSDZrr:
7330 case X86::VMINCSSZrr:
7342 case X86::VADDPDYrr:
7343 case X86::VADDPSYrr:
7344 case X86::VADDPDZ128rr:
7345 case X86::VADDPSZ128rr:
7346 case X86::VADDPDZ256rr:
7347 case X86::VADDPSZ256rr:
7348 case X86::VADDPDZrr:
7349 case X86::VADDPSZrr:
7352 case X86::VADDSDZrr:
7353 case X86::VADDSSZrr:
7356 case X86::VMULPDYrr:
7357 case X86::VMULPSYrr:
7358 case X86::VMULPDZ128rr:
7359 case X86::VMULPSZ128rr:
7360 case X86::VMULPDZ256rr:
7361 case X86::VMULPSZ256rr:
7362 case X86::VMULPDZrr:
7363 case X86::VMULPSZrr:
7366 case X86::VMULSDZrr:
7367 case X86::VMULSSZrr:
7368 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
7374 /// This is an architecture-specific helper function of reassociateOps.
7375 /// Set special operand attributes for new instructions after reassociation.
7376 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7377 MachineInstr &OldMI2,
7378 MachineInstr &NewMI1,
7379 MachineInstr &NewMI2) const {
7380 // Integer instructions define an implicit EFLAGS source register operand as
7381 // the third source (fourth total) operand.
7382 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7385 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
7386 "Unexpected instruction type for reassociation");
7388 MachineOperand &OldOp1 = OldMI1.getOperand(3);
7389 MachineOperand &OldOp2 = OldMI2.getOperand(3);
7390 MachineOperand &NewOp1 = NewMI1.getOperand(3);
7391 MachineOperand &NewOp2 = NewMI2.getOperand(3);
7393 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7394 "Must have dead EFLAGS operand in reassociable instruction");
7395 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7396 "Must have dead EFLAGS operand in reassociable instruction");
7401 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7402 "Unexpected operand in reassociable instruction");
7403 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
7404 "Unexpected operand in reassociable instruction");
7406 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7407 // of this pass or other passes. The EFLAGS operands must be dead in these new
7408 // instructions because the EFLAGS operands in the original instructions must
7409 // be dead in order for reassociation to occur.
7414 std::pair<unsigned, unsigned>
7415 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7416 return std::make_pair(TF, 0u);
7419 ArrayRef<std::pair<unsigned, const char *>>
7420 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7421 using namespace X86II;
7422 static const std::pair<unsigned, const char *> TargetFlags[] = {
7423 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7424 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7425 {MO_GOT, "x86-got"},
7426 {MO_GOTOFF, "x86-gotoff"},
7427 {MO_GOTPCREL, "x86-gotpcrel"},
7428 {MO_PLT, "x86-plt"},
7429 {MO_TLSGD, "x86-tlsgd"},
7430 {MO_TLSLD, "x86-tlsld"},
7431 {MO_TLSLDM, "x86-tlsldm"},
7432 {MO_GOTTPOFF, "x86-gottpoff"},
7433 {MO_INDNTPOFF, "x86-indntpoff"},
7434 {MO_TPOFF, "x86-tpoff"},
7435 {MO_DTPOFF, "x86-dtpoff"},
7436 {MO_NTPOFF, "x86-ntpoff"},
7437 {MO_GOTNTPOFF, "x86-gotntpoff"},
7438 {MO_DLLIMPORT, "x86-dllimport"},
7439 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7440 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
7441 {MO_TLVP, "x86-tlvp"},
7442 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7443 {MO_SECREL, "x86-secrel"},
7444 {MO_COFFSTUB, "x86-coffstub"}};
7445 return makeArrayRef(TargetFlags);
7449 /// Create Global Base Reg pass. This initializes the PIC
7450 /// global base register for x86-32.
7451 struct CGBR : public MachineFunctionPass {
7453 CGBR() : MachineFunctionPass(ID) {}
7455 bool runOnMachineFunction(MachineFunction &MF) override {
7456 const X86TargetMachine *TM =
7457 static_cast<const X86TargetMachine *>(&MF.getTarget());
7458 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
7460 // Don't do anything in the 64-bit small and kernel code models. They use
7461 // RIP-relative addressing for everything.
7462 if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small ||
7463 TM->getCodeModel() == CodeModel::Kernel))
7466 // Only emit a global base reg in PIC mode.
7467 if (!TM->isPositionIndependent())
7470 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7471 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7473 // If we didn't need a GlobalBaseReg, don't insert code.
7474 if (GlobalBaseReg == 0)
7477 // Insert the set of GlobalBaseReg into the first MBB of the function
7478 MachineBasicBlock &FirstMBB = MF.front();
7479 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7480 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7481 MachineRegisterInfo &RegInfo = MF.getRegInfo();
7482 const X86InstrInfo *TII = STI.getInstrInfo();
7485 if (STI.isPICStyleGOT())
7486 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
7490 if (STI.is64Bit()) {
7491 if (TM->getCodeModel() == CodeModel::Medium) {
7492 // In the medium code model, use a RIP-relative LEA to materialize the
7494 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
7498 .addExternalSymbol("_GLOBAL_OFFSET_TABLE_")
7500 } else if (TM->getCodeModel() == CodeModel::Large) {
7501 // In the large code model, we are aiming for this code, though the
7502 // register allocation may vary:
7503 // leaq .LN$pb(%rip), %rax
7504 // movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx
7506 // RAX now holds address of _GLOBAL_OFFSET_TABLE_.
7507 unsigned PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
7509 RegInfo.createVirtualRegister(&X86::GR64RegClass);
7510 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
7514 .addSym(MF.getPICBaseSymbol())
7516 std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol());
7517 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
7518 .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7519 X86II::MO_PIC_BASE_OFFSET);
7520 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
7521 .addReg(PBReg, RegState::Kill)
7522 .addReg(GOTReg, RegState::Kill);
7524 llvm_unreachable("unexpected code model");
7527 // Operand of MovePCtoStack is completely ignored by asm printer. It's
7528 // only used in JIT code emission as displacement to pc.
7529 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
7531 // If we're using vanilla 'GOT' PIC style, we should use relative
7532 // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
7533 if (STI.isPICStyleGOT()) {
7534 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel],
7536 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7538 .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7539 X86II::MO_GOT_ABSOLUTE_ADDRESS);
7546 StringRef getPassName() const override {
7547 return "X86 PIC Global Base Reg Initialization";
7550 void getAnalysisUsage(AnalysisUsage &AU) const override {
7551 AU.setPreservesCFG();
7552 MachineFunctionPass::getAnalysisUsage(AU);
7559 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
7562 struct LDTLSCleanup : public MachineFunctionPass {
7564 LDTLSCleanup() : MachineFunctionPass(ID) {}
7566 bool runOnMachineFunction(MachineFunction &MF) override {
7567 if (skipFunction(MF.getFunction()))
7570 X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
7571 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
7572 // No point folding accesses if there isn't at least two.
7576 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
7577 return VisitNode(DT->getRootNode(), 0);
7580 // Visit the dominator subtree rooted at Node in pre-order.
7581 // If TLSBaseAddrReg is non-null, then use that to replace any
7582 // TLS_base_addr instructions. Otherwise, create the register
7583 // when the first such instruction is seen, and then use it
7584 // as we encounter more instructions.
7585 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
7586 MachineBasicBlock *BB = Node->getBlock();
7587 bool Changed = false;
7589 // Traverse the current block.
7590 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
7592 switch (I->getOpcode()) {
7593 case X86::TLS_base_addr32:
7594 case X86::TLS_base_addr64:
7596 I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
7598 I = SetRegister(*I, &TLSBaseAddrReg);
7606 // Visit the children of this block in the dominator tree.
7607 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
7609 Changed |= VisitNode(*I, TLSBaseAddrReg);
7615 // Replace the TLS_base_addr instruction I with a copy from
7616 // TLSBaseAddrReg, returning the new instruction.
7617 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
7618 unsigned TLSBaseAddrReg) {
7619 MachineFunction *MF = I.getParent()->getParent();
7620 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7621 const bool is64Bit = STI.is64Bit();
7622 const X86InstrInfo *TII = STI.getInstrInfo();
7624 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
7625 MachineInstr *Copy =
7626 BuildMI(*I.getParent(), I, I.getDebugLoc(),
7627 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
7628 .addReg(TLSBaseAddrReg);
7630 // Erase the TLS_base_addr instruction.
7631 I.eraseFromParent();
7636 // Create a virtual register in *TLSBaseAddrReg, and populate it by
7637 // inserting a copy instruction after I. Returns the new instruction.
7638 MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
7639 MachineFunction *MF = I.getParent()->getParent();
7640 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7641 const bool is64Bit = STI.is64Bit();
7642 const X86InstrInfo *TII = STI.getInstrInfo();
7644 // Create a virtual register for the TLS base address.
7645 MachineRegisterInfo &RegInfo = MF->getRegInfo();
7646 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
7647 ? &X86::GR64RegClass
7648 : &X86::GR32RegClass);
7650 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
7651 MachineInstr *Next = I.getNextNode();
7652 MachineInstr *Copy =
7653 BuildMI(*I.getParent(), Next, I.getDebugLoc(),
7654 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
7655 .addReg(is64Bit ? X86::RAX : X86::EAX);
7660 StringRef getPassName() const override {
7661 return "Local Dynamic TLS Access Clean-up";
7664 void getAnalysisUsage(AnalysisUsage &AU) const override {
7665 AU.setPreservesCFG();
7666 AU.addRequired<MachineDominatorTree>();
7667 MachineFunctionPass::getAnalysisUsage(AU);
7672 char LDTLSCleanup::ID = 0;
7674 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
7676 /// Constants defining how certain sequences should be outlined.
7678 /// \p MachineOutlinerDefault implies that the function is called with a call
7679 /// instruction, and a return must be emitted for the outlined function frame.
7683 /// I1 OUTLINED_FUNCTION:
7684 /// I2 --> call OUTLINED_FUNCTION I1
7689 /// * Call construction overhead: 1 (call instruction)
7690 /// * Frame construction overhead: 1 (return instruction)
7692 /// \p MachineOutlinerTailCall implies that the function is being tail called.
7693 /// A jump is emitted instead of a call, and the return is already present in
7694 /// the outlined sequence. That is,
7696 /// I1 OUTLINED_FUNCTION:
7697 /// I2 --> jmp OUTLINED_FUNCTION I1
7701 /// * Call construction overhead: 1 (jump instruction)
7702 /// * Frame construction overhead: 0 (don't need to return)
7704 enum MachineOutlinerClass {
7705 MachineOutlinerDefault,
7706 MachineOutlinerTailCall
7709 outliner::OutlinedFunction X86InstrInfo::getOutliningCandidateInfo(
7710 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
7711 unsigned SequenceSize =
7712 std::accumulate(RepeatedSequenceLocs[0].front(),
7713 std::next(RepeatedSequenceLocs[0].back()), 0,
7714 [](unsigned Sum, const MachineInstr &MI) {
7715 // FIXME: x86 doesn't implement getInstSizeInBytes, so
7716 // we can't tell the cost. Just assume each instruction
7718 if (MI.isDebugInstr() || MI.isKill())
7723 // FIXME: Use real size in bytes for call and ret instructions.
7724 if (RepeatedSequenceLocs[0].back()->isTerminator()) {
7725 for (outliner::Candidate &C : RepeatedSequenceLocs)
7726 C.setCallInfo(MachineOutlinerTailCall, 1);
7728 return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
7729 0, // Number of bytes to emit frame.
7730 MachineOutlinerTailCall // Type of frame.
7734 for (outliner::Candidate &C : RepeatedSequenceLocs)
7735 C.setCallInfo(MachineOutlinerDefault, 1);
7737 return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1,
7738 MachineOutlinerDefault);
7741 bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
7742 bool OutlineFromLinkOnceODRs) const {
7743 const Function &F = MF.getFunction();
7745 // Does the function use a red zone? If it does, then we can't risk messing
7747 if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
7748 // It could have a red zone. If it does, then we don't want to touch it.
7749 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7750 if (!X86FI || X86FI->getUsesRedZone())
7754 // If we *don't* want to outline from things that could potentially be deduped
7755 // then return false.
7756 if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
7759 // This function is viable for outlining, so return true.
7764 X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
7765 MachineInstr &MI = *MIT;
7766 // Don't allow debug values to impact outlining type.
7767 if (MI.isDebugInstr() || MI.isIndirectDebugValue())
7768 return outliner::InstrType::Invisible;
7770 // At this point, KILL instructions don't really tell us much so we can go
7771 // ahead and skip over them.
7773 return outliner::InstrType::Invisible;
7775 // Is this a tail call? If yes, we can outline as a tail call.
7777 return outliner::InstrType::Legal;
7779 // Is this the terminator of a basic block?
7780 if (MI.isTerminator() || MI.isReturn()) {
7782 // Does its parent have any successors in its MachineFunction?
7783 if (MI.getParent()->succ_empty())
7784 return outliner::InstrType::Legal;
7786 // It does, so we can't tail call it.
7787 return outliner::InstrType::Illegal;
7790 // Don't outline anything that modifies or reads from the stack pointer.
7792 // FIXME: There are instructions which are being manually built without
7793 // explicit uses/defs so we also have to check the MCInstrDesc. We should be
7794 // able to remove the extra checks once those are fixed up. For example,
7795 // sometimes we might get something like %rax = POP64r 1. This won't be
7796 // caught by modifiesRegister or readsRegister even though the instruction
7797 // really ought to be formed so that modifiesRegister/readsRegister would
7799 if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
7800 MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
7801 MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
7802 return outliner::InstrType::Illegal;
7804 // Outlined calls change the instruction pointer, so don't read from it.
7805 if (MI.readsRegister(X86::RIP, &RI) ||
7806 MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
7807 MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
7808 return outliner::InstrType::Illegal;
7810 // Positions can't safely be outlined.
7811 if (MI.isPosition())
7812 return outliner::InstrType::Illegal;
7814 // Make sure none of the operands of this instruction do anything tricky.
7815 for (const MachineOperand &MOP : MI.operands())
7816 if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
7817 MOP.isTargetIndex())
7818 return outliner::InstrType::Illegal;
7820 return outliner::InstrType::Legal;
7823 void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
7824 MachineFunction &MF,
7825 const outliner::OutlinedFunction &OF)
7827 // If we're a tail call, we already have a return, so don't do anything.
7828 if (OF.FrameConstructionID == MachineOutlinerTailCall)
7831 // We're a normal call, so our sequence doesn't have a return instruction.
7833 MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ));
7834 MBB.insert(MBB.end(), retq);
7837 MachineBasicBlock::iterator
7838 X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
7839 MachineBasicBlock::iterator &It,
7840 MachineFunction &MF,
7841 const outliner::Candidate &C) const {
7842 // Is it a tail call?
7843 if (C.CallConstructionID == MachineOutlinerTailCall) {
7844 // Yes, just insert a JMP.
7846 BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
7847 .addGlobalAddress(M.getNamedValue(MF.getName())));
7849 // No, insert a call.
7851 BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
7852 .addGlobalAddress(M.getNamedValue(MF.getName())));
7858 #define GET_INSTRINFO_HELPERS
7859 #include "X86GenInstrInfo.inc"