1 //===- X86RegisterBankInfo ---------------------------------------*- C++ -*-==//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 /// This file declares the targeting of the RegisterBankInfo class for X86.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_X86_X86REGISTERBANKINFO_H
14 #define LLVM_LIB_TARGET_X86_X86REGISTERBANKINFO_H
16 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
18 #define GET_REGBANK_DECLARATIONS
19 #include "X86GenRegisterBank.inc"
25 class X86GenRegisterBankInfo : public RegisterBankInfo {
27 #define GET_TARGET_REGBANK_CLASS
28 #include "X86GenRegisterBank.inc"
29 #define GET_TARGET_REGBANK_INFO_CLASS
30 #include "X86GenRegisterBankInfo.def"
32 static RegisterBankInfo::PartialMapping PartMappings[];
33 static RegisterBankInfo::ValueMapping ValMappings[];
35 static PartialMappingIdx getPartialMappingIdx(const LLT &Ty, bool isFP);
36 static const RegisterBankInfo::ValueMapping *
37 getValueMapping(PartialMappingIdx Idx, unsigned NumOperands);
40 class TargetRegisterInfo;
42 /// This class provides the information for the target register banks.
43 class X86RegisterBankInfo final : public X86GenRegisterBankInfo {
45 /// Get an instruction mapping.
46 /// \return An InstructionMappings with a statically allocated
48 const InstructionMapping &getSameOperandsMapping(const MachineInstr &MI,
51 /// Track the bank of each instruction operand(register)
53 getInstrPartialMappingIdxs(const MachineInstr &MI,
54 const MachineRegisterInfo &MRI, const bool isFP,
55 SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx);
57 /// Construct the instruction ValueMapping from PartialMappingIdxs
58 /// \return true if mapping succeeded.
60 getInstrValueMapping(const MachineInstr &MI,
61 const SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx,
62 SmallVectorImpl<const ValueMapping *> &OpdsMapping);
65 X86RegisterBankInfo(const TargetRegisterInfo &TRI);
68 getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
71 getInstrAlternativeMappings(const MachineInstr &MI) const override;
73 /// See RegisterBankInfo::applyMapping.
74 void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
76 const InstructionMapping &
77 getInstrMapping(const MachineInstr &MI) const override;