1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the X86 implementation of the TargetRegisterInfo class.
10 // This file is responsible for the frame pointer elimination optimization
13 //===----------------------------------------------------------------------===//
15 #include "X86RegisterInfo.h"
16 #include "X86FrameLowering.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/TargetFrameLowering.h"
26 #include "llvm/CodeGen/TargetInstrInfo.h"
27 #include "llvm/IR/Constants.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
37 #define GET_REGINFO_TARGET_DESC
38 #include "X86GenRegisterInfo.inc"
41 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
42 cl::desc("Enable use of a base pointer for complex stack frames"));
44 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
45 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
46 X86_MC::getDwarfRegFlavour(TT, false),
47 X86_MC::getDwarfRegFlavour(TT, true),
48 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
49 X86_MC::initLLVMToSEHAndCVRegMapping(this);
51 // Cache some information.
52 Is64Bit = TT.isArch64Bit();
53 IsWin64 = Is64Bit && TT.isOSWindows();
55 // Use a callee-saved register as the base pointer. These registers must
56 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
57 // requires GOT in the EBX register before function calls via PLT GOT pointer.
60 // This matches the simplified 32-bit pointer code in the data layout
62 // FIXME: Should use the data layout?
63 bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
64 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
65 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
66 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
76 X86RegisterInfo::getSEHRegNum(unsigned i) const {
77 return getEncodingValue(i);
80 const TargetRegisterClass *
81 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
83 // The sub_8bit sub-register index is more constrained in 32-bit mode.
84 // It behaves just like the sub_8bit_hi index.
85 if (!Is64Bit && Idx == X86::sub_8bit)
86 Idx = X86::sub_8bit_hi;
88 // Forward to TableGen's default version.
89 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
92 const TargetRegisterClass *
93 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
94 const TargetRegisterClass *B,
95 unsigned SubIdx) const {
96 // The sub_8bit sub-register index is more constrained in 32-bit mode.
97 if (!Is64Bit && SubIdx == X86::sub_8bit) {
98 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
102 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
105 const TargetRegisterClass *
106 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
107 const MachineFunction &MF) const {
108 // Don't allow super-classes of GR8_NOREX. This class is only used after
109 // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
110 // to the full GR8 register class in 64-bit mode, so we cannot allow the
111 // reigster class inflation.
113 // The GR8_NOREX class is always used in a way that won't be constrained to a
114 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
116 if (RC == &X86::GR8_NOREXRegClass)
119 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
121 const TargetRegisterClass *Super = RC;
122 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
124 switch (Super->getID()) {
125 case X86::FR32RegClassID:
126 case X86::FR64RegClassID:
127 // If AVX-512 isn't supported we should only inflate to these classes.
128 if (!Subtarget.hasAVX512() &&
129 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
132 case X86::VR128RegClassID:
133 case X86::VR256RegClassID:
134 // If VLX isn't supported we should only inflate to these classes.
135 if (!Subtarget.hasVLX() &&
136 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
139 case X86::VR128XRegClassID:
140 case X86::VR256XRegClassID:
141 // If VLX isn't support we shouldn't inflate to these classes.
142 if (Subtarget.hasVLX() &&
143 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
146 case X86::FR32XRegClassID:
147 case X86::FR64XRegClassID:
148 // If AVX-512 isn't support we shouldn't inflate to these classes.
149 if (Subtarget.hasAVX512() &&
150 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
153 case X86::GR8RegClassID:
154 case X86::GR16RegClassID:
155 case X86::GR32RegClassID:
156 case X86::GR64RegClassID:
157 case X86::RFP32RegClassID:
158 case X86::RFP64RegClassID:
159 case X86::RFP80RegClassID:
160 case X86::VR512_0_15RegClassID:
161 case X86::VR512RegClassID:
162 // Don't return a super-class that would shrink the spill size.
163 // That can happen with the vector and float classes.
164 if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
172 const TargetRegisterClass *
173 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
174 unsigned Kind) const {
175 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
177 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
178 case 0: // Normal GPRs.
179 if (Subtarget.isTarget64BitLP64())
180 return &X86::GR64RegClass;
181 // If the target is 64bit but we have been told to use 32bit addresses,
182 // we can still use 64-bit register as long as we know the high bits
184 // Reflect that in the returned register class.
186 // When the target also allows 64-bit frame pointer and we do have a
187 // frame, this is fine to use it for the address accesses as well.
188 const X86FrameLowering *TFI = getFrameLowering(MF);
189 return TFI->hasFP(MF) && TFI->Uses64BitFramePtr
190 ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
191 : &X86::LOW32_ADDR_ACCESSRegClass;
193 return &X86::GR32RegClass;
194 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
195 if (Subtarget.isTarget64BitLP64())
196 return &X86::GR64_NOSPRegClass;
197 // NOSP does not contain RIP, so no special case here.
198 return &X86::GR32_NOSPRegClass;
199 case 2: // NOREX GPRs.
200 if (Subtarget.isTarget64BitLP64())
201 return &X86::GR64_NOREXRegClass;
202 return &X86::GR32_NOREXRegClass;
203 case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
204 if (Subtarget.isTarget64BitLP64())
205 return &X86::GR64_NOREX_NOSPRegClass;
206 // NOSP does not contain RIP, so no special case here.
207 return &X86::GR32_NOREX_NOSPRegClass;
208 case 4: // Available for tailcall (not callee-saved GPRs).
209 return getGPRsForTailCall(MF);
213 bool X86RegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
215 const TargetRegisterClass *SrcRC,
216 unsigned SrcSubReg) const {
217 // Prevent rewriting a copy where the destination size is larger than the
218 // input size. See PR41619.
219 // FIXME: Should this be factored into the base implementation somehow.
220 if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 &&
221 SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit)
224 return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg,
228 const TargetRegisterClass *
229 X86RegisterInfo::getGPRsForTailCall(const MachineFunction &MF) const {
230 const Function &F = MF.getFunction();
231 if (IsWin64 || (F.getCallingConv() == CallingConv::Win64))
232 return &X86::GR64_TCW64RegClass;
234 return &X86::GR64_TCRegClass;
236 bool hasHipeCC = (F.getCallingConv() == CallingConv::HiPE);
238 return &X86::GR32RegClass;
239 return &X86::GR32_TCRegClass;
242 const TargetRegisterClass *
243 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
244 if (RC == &X86::CCRRegClass) {
246 return &X86::GR64RegClass;
248 return &X86::GR32RegClass;
254 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
255 MachineFunction &MF) const {
256 const X86FrameLowering *TFI = getFrameLowering(MF);
258 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
259 switch (RC->getID()) {
262 case X86::GR32RegClassID:
264 case X86::GR64RegClassID:
266 case X86::VR128RegClassID:
267 return Is64Bit ? 10 : 4;
268 case X86::VR64RegClassID:
274 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
275 assert(MF && "MachineFunction required");
277 const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
278 const Function &F = MF->getFunction();
279 bool HasSSE = Subtarget.hasSSE1();
280 bool HasAVX = Subtarget.hasAVX();
281 bool HasAVX512 = Subtarget.hasAVX512();
282 bool CallsEHReturn = MF->callsEHReturn();
284 CallingConv::ID CC = F.getCallingConv();
286 // If attribute NoCallerSavedRegisters exists then we set X86_INTR calling
287 // convention because it has the CSR list.
288 if (MF->getFunction().hasFnAttribute("no_caller_saved_registers"))
289 CC = CallingConv::X86_INTR;
292 case CallingConv::GHC:
293 case CallingConv::HiPE:
294 return CSR_NoRegs_SaveList;
295 case CallingConv::AnyReg:
297 return CSR_64_AllRegs_AVX_SaveList;
298 return CSR_64_AllRegs_SaveList;
299 case CallingConv::PreserveMost:
300 return CSR_64_RT_MostRegs_SaveList;
301 case CallingConv::PreserveAll:
303 return CSR_64_RT_AllRegs_AVX_SaveList;
304 return CSR_64_RT_AllRegs_SaveList;
305 case CallingConv::CXX_FAST_TLS:
307 return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
308 CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
310 case CallingConv::Intel_OCL_BI: {
311 if (HasAVX512 && IsWin64)
312 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
313 if (HasAVX512 && Is64Bit)
314 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
315 if (HasAVX && IsWin64)
316 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
317 if (HasAVX && Is64Bit)
318 return CSR_64_Intel_OCL_BI_AVX_SaveList;
319 if (!HasAVX && !IsWin64 && Is64Bit)
320 return CSR_64_Intel_OCL_BI_SaveList;
323 case CallingConv::HHVM:
324 return CSR_64_HHVM_SaveList;
325 case CallingConv::X86_RegCall:
328 return (HasSSE ? CSR_Win64_RegCall_SaveList :
329 CSR_Win64_RegCall_NoSSE_SaveList);
331 return (HasSSE ? CSR_SysV64_RegCall_SaveList :
332 CSR_SysV64_RegCall_NoSSE_SaveList);
335 return (HasSSE ? CSR_32_RegCall_SaveList :
336 CSR_32_RegCall_NoSSE_SaveList);
338 case CallingConv::CFGuard_Check:
339 assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86");
340 return (HasSSE ? CSR_Win32_CFGuard_Check_SaveList
341 : CSR_Win32_CFGuard_Check_NoSSE_SaveList);
342 case CallingConv::Cold:
344 return CSR_64_MostRegs_SaveList;
346 case CallingConv::Win64:
348 return CSR_Win64_NoSSE_SaveList;
349 return CSR_Win64_SaveList;
350 case CallingConv::X86_64_SysV:
352 return CSR_64EHRet_SaveList;
353 return CSR_64_SaveList;
354 case CallingConv::X86_INTR:
357 return CSR_64_AllRegs_AVX512_SaveList;
359 return CSR_64_AllRegs_AVX_SaveList;
361 return CSR_64_AllRegs_SaveList;
362 return CSR_64_AllRegs_NoSSE_SaveList;
365 return CSR_32_AllRegs_AVX512_SaveList;
367 return CSR_32_AllRegs_AVX_SaveList;
369 return CSR_32_AllRegs_SSE_SaveList;
370 return CSR_32_AllRegs_SaveList;
377 bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
378 F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
380 return IsWin64 ? CSR_Win64_SwiftError_SaveList
381 : CSR_64_SwiftError_SaveList;
384 return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList;
386 return CSR_64EHRet_SaveList;
387 return CSR_64_SaveList;
390 return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
393 const MCPhysReg *X86RegisterInfo::getCalleeSavedRegsViaCopy(
394 const MachineFunction *MF) const {
395 assert(MF && "Invalid MachineFunction pointer.");
396 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
397 MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR())
398 return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
403 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
404 CallingConv::ID CC) const {
405 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
406 bool HasSSE = Subtarget.hasSSE1();
407 bool HasAVX = Subtarget.hasAVX();
408 bool HasAVX512 = Subtarget.hasAVX512();
411 case CallingConv::GHC:
412 case CallingConv::HiPE:
413 return CSR_NoRegs_RegMask;
414 case CallingConv::AnyReg:
416 return CSR_64_AllRegs_AVX_RegMask;
417 return CSR_64_AllRegs_RegMask;
418 case CallingConv::PreserveMost:
419 return CSR_64_RT_MostRegs_RegMask;
420 case CallingConv::PreserveAll:
422 return CSR_64_RT_AllRegs_AVX_RegMask;
423 return CSR_64_RT_AllRegs_RegMask;
424 case CallingConv::CXX_FAST_TLS:
426 return CSR_64_TLS_Darwin_RegMask;
428 case CallingConv::Intel_OCL_BI: {
429 if (HasAVX512 && IsWin64)
430 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
431 if (HasAVX512 && Is64Bit)
432 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
433 if (HasAVX && IsWin64)
434 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
435 if (HasAVX && Is64Bit)
436 return CSR_64_Intel_OCL_BI_AVX_RegMask;
437 if (!HasAVX && !IsWin64 && Is64Bit)
438 return CSR_64_Intel_OCL_BI_RegMask;
441 case CallingConv::HHVM:
442 return CSR_64_HHVM_RegMask;
443 case CallingConv::X86_RegCall:
446 return (HasSSE ? CSR_Win64_RegCall_RegMask :
447 CSR_Win64_RegCall_NoSSE_RegMask);
449 return (HasSSE ? CSR_SysV64_RegCall_RegMask :
450 CSR_SysV64_RegCall_NoSSE_RegMask);
453 return (HasSSE ? CSR_32_RegCall_RegMask :
454 CSR_32_RegCall_NoSSE_RegMask);
456 case CallingConv::CFGuard_Check:
457 assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86");
458 return (HasSSE ? CSR_Win32_CFGuard_Check_RegMask
459 : CSR_Win32_CFGuard_Check_NoSSE_RegMask);
460 case CallingConv::Cold:
462 return CSR_64_MostRegs_RegMask;
464 case CallingConv::Win64:
465 return CSR_Win64_RegMask;
466 case CallingConv::X86_64_SysV:
467 return CSR_64_RegMask;
468 case CallingConv::X86_INTR:
471 return CSR_64_AllRegs_AVX512_RegMask;
473 return CSR_64_AllRegs_AVX_RegMask;
475 return CSR_64_AllRegs_RegMask;
476 return CSR_64_AllRegs_NoSSE_RegMask;
479 return CSR_32_AllRegs_AVX512_RegMask;
481 return CSR_32_AllRegs_AVX_RegMask;
483 return CSR_32_AllRegs_SSE_RegMask;
484 return CSR_32_AllRegs_RegMask;
490 // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
493 const Function &F = MF.getFunction();
494 bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
495 F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
497 return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask;
498 return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask;
501 return CSR_32_RegMask;
505 X86RegisterInfo::getNoPreservedMask() const {
506 return CSR_NoRegs_RegMask;
509 const uint32_t *X86RegisterInfo::getDarwinTLSCallPreservedMask() const {
510 return CSR_64_TLS_Darwin_RegMask;
513 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
514 BitVector Reserved(getNumRegs());
515 const X86FrameLowering *TFI = getFrameLowering(MF);
517 // Set the floating point control register as reserved.
518 Reserved.set(X86::FPCW);
520 // Set the floating point status register as reserved.
521 Reserved.set(X86::FPSW);
523 // Set the SIMD floating point control register as reserved.
524 Reserved.set(X86::MXCSR);
526 // Set the stack-pointer register and its aliases as reserved.
527 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP))
528 Reserved.set(SubReg);
530 // Set the Shadow Stack Pointer as reserved.
531 Reserved.set(X86::SSP);
533 // Set the instruction pointer register and its aliases as reserved.
534 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP))
535 Reserved.set(SubReg);
537 // Set the frame-pointer register and its aliases as reserved if needed.
538 if (TFI->hasFP(MF)) {
539 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RBP))
540 Reserved.set(SubReg);
543 // Set the base-pointer register and its aliases as reserved if needed.
544 if (hasBasePointer(MF)) {
545 CallingConv::ID CC = MF.getFunction().getCallingConv();
546 const uint32_t *RegMask = getCallPreservedMask(MF, CC);
547 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
549 "Stack realignment in presence of dynamic allocas is not supported with"
550 "this calling convention.");
552 Register BasePtr = getX86SubSuperRegister(getBaseRegister(), 64);
553 for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr))
554 Reserved.set(SubReg);
557 // Mark the segment registers as reserved.
558 Reserved.set(X86::CS);
559 Reserved.set(X86::SS);
560 Reserved.set(X86::DS);
561 Reserved.set(X86::ES);
562 Reserved.set(X86::FS);
563 Reserved.set(X86::GS);
565 // Mark the floating point stack registers as reserved.
566 for (unsigned n = 0; n != 8; ++n)
567 Reserved.set(X86::ST0 + n);
569 // Reserve the registers that only exist in 64-bit mode.
571 // These 8-bit registers are part of the x86-64 extension even though their
572 // super-registers are old 32-bits.
573 Reserved.set(X86::SIL);
574 Reserved.set(X86::DIL);
575 Reserved.set(X86::BPL);
576 Reserved.set(X86::SPL);
577 Reserved.set(X86::SIH);
578 Reserved.set(X86::DIH);
579 Reserved.set(X86::BPH);
580 Reserved.set(X86::SPH);
582 for (unsigned n = 0; n != 8; ++n) {
584 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
588 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
592 if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
593 for (unsigned n = 16; n != 32; ++n) {
594 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
599 assert(checkAllSuperRegsMarked(Reserved,
600 {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
601 X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
605 void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
606 // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
607 // because the calling convention defines the EFLAGS register as NOT
610 // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
611 // an assert to track this and clear the register afterwards to avoid
612 // unnecessary crashes during release builds.
613 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
614 "EFLAGS are not live-out from a patchpoint.");
616 // Also clean other registers that don't need preserving (IP).
617 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
618 Mask[Reg / 32] &= ~(1U << (Reg % 32));
621 //===----------------------------------------------------------------------===//
622 // Stack Frame Processing methods
623 //===----------------------------------------------------------------------===//
625 static bool CantUseSP(const MachineFrameInfo &MFI) {
626 return MFI.hasVarSizedObjects() || MFI.hasOpaqueSPAdjustment();
629 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
630 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
631 if (X86FI->hasPreallocatedCall())
634 const MachineFrameInfo &MFI = MF.getFrameInfo();
636 if (!EnableBasePointer)
639 // When we need stack realignment, we can't address the stack from the frame
640 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
641 // can't address variables from the stack pointer. MS inline asm can
642 // reference locals while also adjusting the stack pointer. When we can't
643 // use both the SP and the FP, we need a separate base pointer register.
644 bool CantUseFP = needsStackRealignment(MF);
645 return CantUseFP && CantUseSP(MFI);
648 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
649 if (!TargetRegisterInfo::canRealignStack(MF))
652 const MachineFrameInfo &MFI = MF.getFrameInfo();
653 const MachineRegisterInfo *MRI = &MF.getRegInfo();
655 // Stack realignment requires a frame pointer. If we already started
656 // register allocation with frame pointer elimination, it is too late now.
657 if (!MRI->canReserveReg(FramePtr))
660 // If a base pointer is necessary. Check that it isn't too late to reserve
663 return MRI->canReserveReg(BasePtr);
667 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
668 Register Reg, int &FrameIdx) const {
669 // Since X86 defines assignCalleeSavedSpillSlots which always return true
670 // this function neither used nor tested.
671 llvm_unreachable("Unused function on X86. Otherwise need a test case.");
674 // tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
675 // of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
676 // TODO: In this case we should be really trying first to entirely eliminate
677 // this instruction which is a plain copy.
678 static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II) {
679 MachineInstr &MI = *II;
680 unsigned Opc = II->getOpcode();
681 // Check if this is a LEA of the form 'lea (%esp), %ebx'
682 if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
683 MI.getOperand(2).getImm() != 1 ||
684 MI.getOperand(3).getReg() != X86::NoRegister ||
685 MI.getOperand(4).getImm() != 0 ||
686 MI.getOperand(5).getReg() != X86::NoRegister)
688 Register BasePtr = MI.getOperand(1).getReg();
689 // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
690 // be replaced with a 32-bit operand MOV which will zero extend the upper
691 // 32-bits of the super register.
692 if (Opc == X86::LEA64_32r)
693 BasePtr = getX86SubSuperRegister(BasePtr, 32);
694 Register NewDestReg = MI.getOperand(0).getReg();
695 const X86InstrInfo *TII =
696 MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
697 TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr,
698 MI.getOperand(1).isKill());
699 MI.eraseFromParent();
703 static bool isFuncletReturnInstr(MachineInstr &MI) {
704 switch (MI.getOpcode()) {
706 case X86::CLEANUPRET:
711 llvm_unreachable("impossible");
715 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
716 int SPAdj, unsigned FIOperandNum,
717 RegScavenger *RS) const {
718 MachineInstr &MI = *II;
719 MachineBasicBlock &MBB = *MI.getParent();
720 MachineFunction &MF = *MBB.getParent();
721 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
722 bool IsEHFuncletEpilogue = MBBI == MBB.end() ? false
723 : isFuncletReturnInstr(*MBBI);
724 const X86FrameLowering *TFI = getFrameLowering(MF);
725 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
727 // Determine base register and offset.
731 assert((!needsStackRealignment(MF) ||
732 MF.getFrameInfo().isFixedObjectIndex(FrameIndex)) &&
733 "Return instruction can only reference SP relative frame objects");
734 FIOffset = TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0);
735 } else if (TFI->Is64Bit && (MBB.isEHFuncletEntry() || IsEHFuncletEpilogue)) {
736 FIOffset = TFI->getWin64EHFrameIndexRef(MF, FrameIndex, BasePtr);
738 FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, BasePtr);
741 // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
742 // simple FP case, and doesn't work with stack realignment. On 32-bit, the
743 // offset is from the traditional base pointer location. On 64-bit, the
744 // offset is from the SP at the end of the prologue, not the FP location. This
745 // matches the behavior of llvm.frameaddress.
746 unsigned Opc = MI.getOpcode();
747 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
748 MachineOperand &FI = MI.getOperand(FIOperandNum);
749 FI.ChangeToImmediate(FIOffset);
753 // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
754 // register as source operand, semantic is the same and destination is
755 // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
756 // Don't change BasePtr since it is used later for stack adjustment.
757 Register MachineBasePtr = BasePtr;
758 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
759 MachineBasePtr = getX86SubSuperRegister(BasePtr, 64);
761 // This must be part of a four operand memory reference. Replace the
762 // FrameIndex with base register. Add an offset to the offset.
763 MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr, false);
765 if (BasePtr == StackPtr)
768 // The frame index format for stackmaps and patchpoints is different from the
769 // X86 format. It only has a FI and an offset.
770 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
771 assert(BasePtr == FramePtr && "Expected the FP as base register");
772 int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
773 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
777 if (MI.getOperand(FIOperandNum+3).isImm()) {
778 // Offset is a 32-bit integer.
779 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
780 int Offset = FIOffset + Imm;
781 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
782 "Requesting 64-bit offset in 32-bit immediate!");
783 if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
784 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
786 // Offset is symbolic. This is extremely rare.
787 uint64_t Offset = FIOffset +
788 (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
789 MI.getOperand(FIOperandNum + 3).setOffset(Offset);
793 Register X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
794 const X86FrameLowering *TFI = getFrameLowering(MF);
795 return TFI->hasFP(MF) ? FramePtr : StackPtr;
799 X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
800 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
801 Register FrameReg = getFrameRegister(MF);
802 if (Subtarget.isTarget64BitILP32())
803 FrameReg = getX86SubSuperRegister(FrameReg, 32);
808 X86RegisterInfo::getPtrSizedStackRegister(const MachineFunction &MF) const {
809 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
810 Register StackReg = getStackRegister();
811 if (Subtarget.isTarget64BitILP32())
812 StackReg = getX86SubSuperRegister(StackReg, 32);