1 //=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the machine model for Broadwell to support instruction
10 // scheduling and other instruction cost heuristics.
12 //===----------------------------------------------------------------------===//
14 def BroadwellModel : SchedMachineModel {
15 // All x86 instructions are modeled as a single micro-op, and BW can decode 4
16 // instructions per cycle.
18 let MicroOpBufferSize = 192; // Based on the reorder buffer.
20 let MispredictPenalty = 16;
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23 let LoopMicroOpBufferSize = 50;
25 // This flag is set to allow the scheduler to assign a default model to
26 // unrecognized opcodes.
27 let CompleteModel = 0;
30 let SchedModel = BroadwellModel in {
32 // Broadwell can issue micro-ops to 8 different ports in one cycle.
34 // Ports 0, 1, 5, and 6 handle all computation.
35 // Port 4 gets the data half of stores. Store data can be available later than
36 // the store address, but since we don't model the latency of stores, we can
38 // Ports 2 and 3 are identical. They handle loads and the address half of
39 // stores. Port 7 can handle address calculations.
40 def BWPort0 : ProcResource<1>;
41 def BWPort1 : ProcResource<1>;
42 def BWPort2 : ProcResource<1>;
43 def BWPort3 : ProcResource<1>;
44 def BWPort4 : ProcResource<1>;
45 def BWPort5 : ProcResource<1>;
46 def BWPort6 : ProcResource<1>;
47 def BWPort7 : ProcResource<1>;
49 // Many micro-ops are capable of issuing on multiple ports.
50 def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>;
51 def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>;
52 def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;
53 def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>;
54 def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>;
55 def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>;
56 def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>;
57 def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>;
58 def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>;
59 def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;
60 def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;
61 def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;
63 // 60 Entry Unified Scheduler
64 def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,
65 BWPort5, BWPort6, BWPort7]> {
69 // Integer division issued on port 0.
70 def BWDivider : ProcResource<1>;
71 // FP division and sqrt on port 0.
72 def BWFPDivider : ProcResource<1>;
74 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
75 // cycles after the memory operand.
76 def : ReadAdvance<ReadAfterLd, 5>;
78 // Vector loads are 5/5/6 cycles, so ReadAfterVec*Ld registers needn't be available
79 // until 5/5/6 cycles after the memory operand.
80 def : ReadAdvance<ReadAfterVecLd, 5>;
81 def : ReadAdvance<ReadAfterVecXLd, 5>;
82 def : ReadAdvance<ReadAfterVecYLd, 6>;
84 def : ReadAdvance<ReadInt2Fpu, 0>;
86 // Many SchedWrites are defined in pairs with and without a folded load.
87 // Instructions with folded loads are usually micro-fused, so they only appear
88 // as two micro-ops when queued in the reservation station.
89 // This multiclass defines the resource usage for variants with and without
91 multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
92 list<ProcResourceKind> ExePorts,
93 int Lat, list<int> Res = [1], int UOps = 1,
95 // Register variant is using a single cycle on ExePort.
96 def : WriteRes<SchedRW, ExePorts> {
98 let ResourceCycles = Res;
99 let NumMicroOps = UOps;
102 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
103 // the latency (default = 5).
104 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
105 let Latency = !add(Lat, LoadLat);
106 let ResourceCycles = !listconcat([1], Res);
107 let NumMicroOps = !add(UOps, 1);
111 // A folded store needs a cycle on port 4 for the store data, and an extra port
112 // 2/3/7 cycle to recompute the address.
113 def : WriteRes<WriteRMW, [BWPort237,BWPort4]>;
116 defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op.
117 defm : BWWriteResPair<WriteADC, [BWPort06], 1>; // Integer ALU + flags op.
119 // Integer multiplication.
120 defm : BWWriteResPair<WriteIMul8, [BWPort1], 3>;
121 defm : BWWriteResPair<WriteIMul16, [BWPort1,BWPort06,BWPort0156], 4, [1,1,2], 4>;
122 defm : X86WriteRes<WriteIMul16Imm, [BWPort1,BWPort0156], 4, [1,1], 2>;
123 defm : X86WriteRes<WriteIMul16ImmLd, [BWPort1,BWPort0156,BWPort23], 8, [1,1,1], 3>;
124 defm : BWWriteResPair<WriteIMul16Reg, [BWPort1], 3>;
125 defm : BWWriteResPair<WriteIMul32, [BWPort1,BWPort06,BWPort0156], 4, [1,1,1], 3>;
126 defm : BWWriteResPair<WriteIMul32Imm, [BWPort1], 3>;
127 defm : BWWriteResPair<WriteIMul32Reg, [BWPort1], 3>;
128 defm : BWWriteResPair<WriteIMul64, [BWPort1,BWPort5], 4, [1,1], 2>;
129 defm : BWWriteResPair<WriteIMul64Imm, [BWPort1], 3>;
130 defm : BWWriteResPair<WriteIMul64Reg, [BWPort1], 3>;
131 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
133 // TODO: Why isn't the BWDivider used consistently?
134 defm : X86WriteRes<WriteDiv8, [BWPort0, BWDivider], 25, [1, 10], 1>;
135 defm : X86WriteRes<WriteDiv16, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>;
136 defm : X86WriteRes<WriteDiv32, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>;
137 defm : X86WriteRes<WriteDiv64, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>;
138 defm : X86WriteRes<WriteDiv8Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
139 defm : X86WriteRes<WriteDiv16Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
140 defm : X86WriteRes<WriteDiv32Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
141 defm : X86WriteRes<WriteDiv64Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
143 defm : X86WriteRes<WriteIDiv8, [BWPort0, BWDivider], 25, [1,10], 1>;
144 defm : X86WriteRes<WriteIDiv16, [BWPort0, BWDivider], 25, [1,10], 1>;
145 defm : X86WriteRes<WriteIDiv32, [BWPort0, BWDivider], 25, [1,10], 1>;
146 defm : X86WriteRes<WriteIDiv64, [BWPort0, BWDivider], 25, [1,10], 1>;
147 defm : X86WriteRes<WriteIDiv8Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
148 defm : X86WriteRes<WriteIDiv16Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
149 defm : X86WriteRes<WriteIDiv32Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
150 defm : X86WriteRes<WriteIDiv64Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
152 defm : X86WriteRes<WriteCMPXCHG,[BWPort06, BWPort0156], 5, [2, 3], 5>;
153 defm : X86WriteRes<WriteCMPXCHGRMW,[BWPort23, BWPort06, BWPort0156, BWPort237, BWPort4], 8, [1, 2, 1, 1, 1], 6>;
154 defm : X86WriteRes<WriteBSWAP32, [BWPort15], 1, [1], 1>;
155 defm : X86WriteRes<WriteBSWAP64, [BWPort06, BWPort15], 2, [1, 1], 2>;
156 defm : X86WriteRes<WriteXCHG, [BWPort0156], 2, [3], 3>;
158 defm : BWWriteResPair<WriteCRC32, [BWPort1], 3>;
160 def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
162 defm : BWWriteResPair<WriteCMOV, [BWPort06], 1>; // Conditional move.
163 defm : X86WriteRes<WriteFCMOV, [BWPort1], 3, [1], 1>; // x87 conditional move.
165 def : WriteRes<WriteSETCC, [BWPort06]>; // Setcc.
166 def : WriteRes<WriteSETCCStore, [BWPort06,BWPort4,BWPort237]> {
171 defm : X86WriteRes<WriteLAHFSAHF, [BWPort06], 1, [1], 1>;
172 defm : X86WriteRes<WriteBitTest, [BWPort06], 1, [1], 1>; // Bit Test instrs
173 defm : X86WriteRes<WriteBitTestImmLd, [BWPort06,BWPort23], 6, [1,1], 2>;
174 defm : X86WriteRes<WriteBitTestRegLd, [BWPort0156,BWPort23], 6, [1,1], 2>;
175 defm : X86WriteRes<WriteBitTestSet, [BWPort06], 1, [1], 1>; // Bit Test + Set instrs
176 defm : X86WriteRes<WriteBitTestSetImmLd, [BWPort06,BWPort23], 5, [1,1], 3>;
177 defm : X86WriteRes<WriteBitTestSetRegLd, [BWPort0156,BWPort23], 5, [1,1], 2>;
180 defm : BWWriteResPair<WriteBSF, [BWPort1], 3>;
181 defm : BWWriteResPair<WriteBSR, [BWPort1], 3>;
182 defm : BWWriteResPair<WriteLZCNT, [BWPort1], 3>;
183 defm : BWWriteResPair<WriteTZCNT, [BWPort1], 3>;
184 defm : BWWriteResPair<WritePOPCNT, [BWPort1], 3>;
186 // Integer shifts and rotates.
187 defm : BWWriteResPair<WriteShift, [BWPort06], 1>;
188 defm : BWWriteResPair<WriteShiftCL, [BWPort06,BWPort0156], 3, [2,1], 3>;
189 defm : BWWriteResPair<WriteRotate, [BWPort06], 1, [1], 1>;
190 defm : BWWriteResPair<WriteRotateCL, [BWPort06,BWPort0156], 3, [2,1], 3>;
193 defm : X86WriteRes<WriteSHDrri, [BWPort1], 3, [1], 1>;
194 defm : X86WriteRes<WriteSHDrrcl,[BWPort1,BWPort06,BWPort0156], 6, [1, 1, 2], 4>;
195 defm : X86WriteRes<WriteSHDmri, [BWPort1,BWPort23,BWPort237,BWPort0156], 9, [1, 1, 1, 1], 4>;
196 defm : X86WriteRes<WriteSHDmrcl,[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156], 11, [1, 1, 1, 1, 2], 6>;
198 // BMI1 BEXTR/BLS, BMI2 BZHI
199 defm : BWWriteResPair<WriteBEXTR, [BWPort06,BWPort15], 2, [1,1], 2>;
200 defm : BWWriteResPair<WriteBLS, [BWPort15], 1>;
201 defm : BWWriteResPair<WriteBZHI, [BWPort15], 1>;
203 // Loads, stores, and moves, not folded with other operations.
204 defm : X86WriteRes<WriteLoad, [BWPort23], 5, [1], 1>;
205 defm : X86WriteRes<WriteStore, [BWPort237, BWPort4], 1, [1,1], 1>;
206 defm : X86WriteRes<WriteStoreNT, [BWPort237, BWPort4], 1, [1,1], 2>;
207 defm : X86WriteRes<WriteMove, [BWPort0156], 1, [1], 1>;
209 // Idioms that clear a register, like xorps %xmm0, %xmm0.
210 // These can often bypass execution ports completely.
211 def : WriteRes<WriteZero, []>;
213 // Treat misc copies as a move.
214 def : InstRW<[WriteMove], (instrs COPY)>;
216 // Branches don't produce values, so they have no latency, but they still
217 // consume resources. Indirect branches can fold loads.
218 defm : BWWriteResPair<WriteJump, [BWPort06], 1>;
220 // Floating point. This covers both scalar and vector operations.
221 defm : X86WriteRes<WriteFLD0, [BWPort01], 1, [1], 1>;
222 defm : X86WriteRes<WriteFLD1, [BWPort01], 1, [2], 2>;
223 defm : X86WriteRes<WriteFLDC, [BWPort01], 1, [2], 2>;
224 defm : X86WriteRes<WriteFLoad, [BWPort23], 5, [1], 1>;
225 defm : X86WriteRes<WriteFLoadX, [BWPort23], 5, [1], 1>;
226 defm : X86WriteRes<WriteFLoadY, [BWPort23], 6, [1], 1>;
227 defm : X86WriteRes<WriteFMaskedLoad, [BWPort23,BWPort5], 7, [1,2], 3>;
228 defm : X86WriteRes<WriteFMaskedLoadY, [BWPort23,BWPort5], 8, [1,2], 3>;
229 defm : X86WriteRes<WriteFStore, [BWPort237,BWPort4], 1, [1,1], 2>;
230 defm : X86WriteRes<WriteFStoreX, [BWPort237,BWPort4], 1, [1,1], 2>;
231 defm : X86WriteRes<WriteFStoreY, [BWPort237,BWPort4], 1, [1,1], 2>;
232 defm : X86WriteRes<WriteFStoreNT, [BWPort237,BWPort4], 1, [1,1], 2>;
233 defm : X86WriteRes<WriteFStoreNTX, [BWPort237,BWPort4], 1, [1,1], 2>;
234 defm : X86WriteRes<WriteFStoreNTY, [BWPort237,BWPort4], 1, [1,1], 2>;
236 defm : X86WriteRes<WriteFMaskedStore32, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
237 defm : X86WriteRes<WriteFMaskedStore32Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
238 defm : X86WriteRes<WriteFMaskedStore64, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
239 defm : X86WriteRes<WriteFMaskedStore64Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
241 defm : X86WriteRes<WriteFMove, [BWPort5], 1, [1], 1>;
242 defm : X86WriteRes<WriteFMoveX, [BWPort5], 1, [1], 1>;
243 defm : X86WriteRes<WriteFMoveY, [BWPort5], 1, [1], 1>;
245 defm : BWWriteResPair<WriteFAdd, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub.
246 defm : BWWriteResPair<WriteFAddX, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub (XMM).
247 defm : BWWriteResPair<WriteFAddY, [BWPort1], 3, [1], 1, 6>; // Floating point add/sub (YMM/ZMM).
248 defm : X86WriteResPairUnsupported<WriteFAddZ>;
249 defm : BWWriteResPair<WriteFAdd64, [BWPort1], 3, [1], 1, 5>; // Floating point double add/sub.
250 defm : BWWriteResPair<WriteFAdd64X, [BWPort1], 3, [1], 1, 5>; // Floating point double add/sub (XMM).
251 defm : BWWriteResPair<WriteFAdd64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double add/sub (YMM/ZMM).
252 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
254 defm : BWWriteResPair<WriteFCmp, [BWPort1], 3, [1], 1, 5>; // Floating point compare.
255 defm : BWWriteResPair<WriteFCmpX, [BWPort1], 3, [1], 1, 5>; // Floating point compare (XMM).
256 defm : BWWriteResPair<WriteFCmpY, [BWPort1], 3, [1], 1, 6>; // Floating point compare (YMM/ZMM).
257 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
258 defm : BWWriteResPair<WriteFCmp64, [BWPort1], 3, [1], 1, 5>; // Floating point double compare.
259 defm : BWWriteResPair<WriteFCmp64X, [BWPort1], 3, [1], 1, 5>; // Floating point double compare (XMM).
260 defm : BWWriteResPair<WriteFCmp64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double compare (YMM/ZMM).
261 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
263 defm : BWWriteResPair<WriteFCom, [BWPort1], 3>; // Floating point compare to flags (X87).
264 defm : BWWriteResPair<WriteFComX, [BWPort1], 3>; // Floating point compare to flags (SSE).
266 defm : BWWriteResPair<WriteFMul, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication.
267 defm : BWWriteResPair<WriteFMulX, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication (XMM).
268 defm : BWWriteResPair<WriteFMulY, [BWPort01], 3, [1], 1, 6>; // Floating point multiplication (YMM/ZMM).
269 defm : X86WriteResPairUnsupported<WriteFMulZ>;
270 defm : BWWriteResPair<WriteFMul64, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication.
271 defm : BWWriteResPair<WriteFMul64X, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication (XMM).
272 defm : BWWriteResPair<WriteFMul64Y, [BWPort01], 3, [1], 1, 6>; // Floating point double multiplication (YMM/ZMM).
273 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
275 //defm : BWWriteResPair<WriteFDiv, [BWPort0,BWFPDivider], 11, [1,3], 1, 5>; // Floating point division.
276 defm : BWWriteResPair<WriteFDivX, [BWPort0,BWFPDivider], 11, [1,5], 1, 5>; // Floating point division (XMM).
277 defm : BWWriteResPair<WriteFDivY, [BWPort0,BWPort015,BWFPDivider], 17, [2,1,10], 3, 6>; // Floating point division (YMM).
278 defm : X86WriteResPairUnsupported<WriteFDivZ>;
279 //defm : BWWriteResPair<WriteFDiv64, [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division.
280 defm : BWWriteResPair<WriteFDiv64X, [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division (XMM).
281 defm : BWWriteResPair<WriteFDiv64Y, [BWPort0,BWPort015,BWFPDivider], 23, [2,1,16], 3, 6>; // Floating point division (YMM).
282 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
284 defm : X86WriteRes<WriteFSqrt, [BWPort0,BWFPDivider], 11, [1,4], 1>; // Floating point square root.
285 defm : X86WriteRes<WriteFSqrtLd, [BWPort0,BWPort23,BWFPDivider], 16, [1,1,7], 2>;
286 defm : BWWriteResPair<WriteFSqrtX, [BWPort0,BWFPDivider], 11, [1,7], 1, 5>; // Floating point square root (XMM).
287 defm : BWWriteResPair<WriteFSqrtY, [BWPort0,BWPort015,BWFPDivider], 21, [2,1,14], 3, 6>; // Floating point square root (YMM).
288 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
289 defm : X86WriteRes<WriteFSqrt64, [BWPort0,BWFPDivider], 16, [1,8], 1>; // Floating point double square root.
290 defm : X86WriteRes<WriteFSqrt64Ld, [BWPort0,BWPort23,BWFPDivider], 21, [1,1,14], 2>;
291 defm : BWWriteResPair<WriteFSqrt64X, [BWPort0,BWFPDivider], 16, [1,14],1, 5>; // Floating point double square root (XMM).
292 defm : BWWriteResPair<WriteFSqrt64Y, [BWPort0,BWPort015,BWFPDivider], 29, [2,1,28], 3, 6>; // Floating point double square root (YMM).
293 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
294 defm : BWWriteResPair<WriteFSqrt80, [BWPort0,BWFPDivider], 23, [1,9]>; // Floating point long double square root.
296 defm : BWWriteResPair<WriteFRcp, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal estimate.
297 defm : BWWriteResPair<WriteFRcpX, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal estimate (XMM).
298 defm : BWWriteResPair<WriteFRcpY, [BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal estimate (YMM/ZMM).
299 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
301 defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal square root estimate.
302 defm : BWWriteResPair<WriteFRsqrtX,[BWPort0], 5, [1], 1, 5>; // Floating point reciprocal square root estimate (XMM).
303 defm : BWWriteResPair<WriteFRsqrtY,[BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal square root estimate (YMM/ZMM).
304 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
306 defm : BWWriteResPair<WriteFMA, [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add.
307 defm : BWWriteResPair<WriteFMAX, [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add (XMM).
308 defm : BWWriteResPair<WriteFMAY, [BWPort01], 5, [1], 1, 6>; // Fused Multiply Add (YMM/ZMM).
309 defm : X86WriteResPairUnsupported<WriteFMAZ>;
310 defm : BWWriteResPair<WriteDPPD, [BWPort0,BWPort1,BWPort5], 9, [1,1,1], 3, 5>; // Floating point double dot product.
311 defm : BWWriteResPair<WriteDPPS, [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 5>; // Floating point single dot product.
312 defm : BWWriteResPair<WriteDPPSY, [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 6>; // Floating point single dot product (YMM).
313 defm : X86WriteResPairUnsupported<WriteDPPSZ>;
314 defm : BWWriteResPair<WriteFSign, [BWPort5], 1>; // Floating point fabs/fchs.
315 defm : X86WriteRes<WriteFRnd, [BWPort23], 6, [1], 1>; // Floating point rounding.
316 defm : X86WriteRes<WriteFRndY, [BWPort23], 6, [1], 1>; // Floating point rounding (YMM/ZMM).
317 defm : X86WriteResPairUnsupported<WriteFRndZ>;
318 defm : X86WriteRes<WriteFRndLd, [BWPort1,BWPort23], 11, [2,1], 3>;
319 defm : X86WriteRes<WriteFRndYLd, [BWPort1,BWPort23], 12, [2,1], 3>;
320 defm : BWWriteResPair<WriteFLogic, [BWPort5], 1, [1], 1, 5>; // Floating point and/or/xor logicals.
321 defm : BWWriteResPair<WriteFLogicY, [BWPort5], 1, [1], 1, 6>; // Floating point and/or/xor logicals (YMM/ZMM).
322 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
323 defm : BWWriteResPair<WriteFTest, [BWPort0], 1, [1], 1, 5>; // Floating point TEST instructions.
324 defm : BWWriteResPair<WriteFTestY, [BWPort0], 1, [1], 1, 6>; // Floating point TEST instructions (YMM/ZMM).
325 defm : X86WriteResPairUnsupported<WriteFTestZ>;
326 defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1, [1], 1, 5>; // Floating point vector shuffles.
327 defm : BWWriteResPair<WriteFShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector shuffles (YMM/ZMM).
328 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
329 defm : BWWriteResPair<WriteFVarShuffle, [BWPort5], 1, [1], 1, 5>; // Floating point vector variable shuffles.
330 defm : BWWriteResPair<WriteFVarShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles.
331 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
332 defm : BWWriteResPair<WriteFBlend, [BWPort015], 1, [1], 1, 5>; // Floating point vector blends.
333 defm : BWWriteResPair<WriteFBlendY, [BWPort015], 1, [1], 1, 6>; // Floating point vector blends.
334 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
335 defm : BWWriteResPair<WriteFVarBlend, [BWPort5], 2, [2], 2, 5>; // Fp vector variable blends.
336 defm : BWWriteResPair<WriteFVarBlendY, [BWPort5], 2, [2], 2, 6>; // Fp vector variable blends.
337 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
339 // FMA Scheduling helper class.
340 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
342 // Vector integer operations.
343 defm : X86WriteRes<WriteVecLoad, [BWPort23], 5, [1], 1>;
344 defm : X86WriteRes<WriteVecLoadX, [BWPort23], 5, [1], 1>;
345 defm : X86WriteRes<WriteVecLoadY, [BWPort23], 6, [1], 1>;
346 defm : X86WriteRes<WriteVecLoadNT, [BWPort23], 5, [1], 1>;
347 defm : X86WriteRes<WriteVecLoadNTY, [BWPort23], 6, [1], 1>;
348 defm : X86WriteRes<WriteVecMaskedLoad, [BWPort23,BWPort5], 7, [1,2], 3>;
349 defm : X86WriteRes<WriteVecMaskedLoadY, [BWPort23,BWPort5], 8, [1,2], 3>;
350 defm : X86WriteRes<WriteVecStore, [BWPort237,BWPort4], 1, [1,1], 2>;
351 defm : X86WriteRes<WriteVecStoreX, [BWPort237,BWPort4], 1, [1,1], 2>;
352 defm : X86WriteRes<WriteVecStoreY, [BWPort237,BWPort4], 1, [1,1], 2>;
353 defm : X86WriteRes<WriteVecStoreNT, [BWPort237,BWPort4], 1, [1,1], 2>;
354 defm : X86WriteRes<WriteVecStoreNTY, [BWPort237,BWPort4], 1, [1,1], 2>;
355 defm : X86WriteRes<WriteVecMaskedStore32, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
356 defm : X86WriteRes<WriteVecMaskedStore32Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
357 defm : X86WriteRes<WriteVecMaskedStore64, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
358 defm : X86WriteRes<WriteVecMaskedStore64Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
359 defm : X86WriteRes<WriteVecMove, [BWPort015], 1, [1], 1>;
360 defm : X86WriteRes<WriteVecMoveX, [BWPort015], 1, [1], 1>;
361 defm : X86WriteRes<WriteVecMoveY, [BWPort015], 1, [1], 1>;
362 defm : X86WriteRes<WriteVecMoveToGpr, [BWPort0], 1, [1], 1>;
363 defm : X86WriteRes<WriteVecMoveFromGpr, [BWPort5], 1, [1], 1>;
365 defm : X86WriteRes<WriteEMMS, [BWPort01,BWPort15,BWPort015,BWPort0156], 31, [8,1,21,1], 31>;
367 defm : BWWriteResPair<WriteVecALU, [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
368 defm : BWWriteResPair<WriteVecALUX, [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
369 defm : BWWriteResPair<WriteVecALUY, [BWPort15], 1, [1], 1, 6>; // Vector integer ALU op, no logicals (YMM/ZMM).
370 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
371 defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor.
372 defm : BWWriteResPair<WriteVecLogicX,[BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor.
373 defm : BWWriteResPair<WriteVecLogicY,[BWPort015], 1, [1], 1, 6>; // Vector integer and/or/xor (YMM/ZMM).
374 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
375 defm : BWWriteResPair<WriteVecTest, [BWPort0,BWPort5], 2, [1,1], 2, 5>; // Vector integer TEST instructions.
376 defm : BWWriteResPair<WriteVecTestY, [BWPort0,BWPort5], 4, [1,1], 2, 6>; // Vector integer TEST instructions (YMM/ZMM).
377 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
378 defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5, [1], 1, 5>; // Vector integer multiply.
379 defm : BWWriteResPair<WriteVecIMulX, [BWPort0], 5, [1], 1, 5>; // Vector integer multiply.
380 defm : BWWriteResPair<WriteVecIMulY, [BWPort0], 5, [1], 1, 6>; // Vector integer multiply.
381 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
382 defm : BWWriteResPair<WritePMULLD, [BWPort0], 10, [2], 2, 5>; // Vector PMULLD.
383 defm : BWWriteResPair<WritePMULLDY, [BWPort0], 10, [2], 2, 6>; // Vector PMULLD (YMM/ZMM).
384 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
385 defm : BWWriteResPair<WriteShuffle, [BWPort5], 1, [1], 1, 5>; // Vector shuffles.
386 defm : BWWriteResPair<WriteShuffleX, [BWPort5], 1, [1], 1, 5>; // Vector shuffles.
387 defm : BWWriteResPair<WriteShuffleY, [BWPort5], 1, [1], 1, 6>; // Vector shuffles (YMM/ZMM).
388 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
389 defm : BWWriteResPair<WriteVarShuffle, [BWPort5], 1, [1], 1, 5>; // Vector variable shuffles.
390 defm : BWWriteResPair<WriteVarShuffleX,[BWPort5], 1, [1], 1, 5>; // Vector variable shuffles.
391 defm : BWWriteResPair<WriteVarShuffleY,[BWPort5], 1, [1], 1, 6>; // Vector variable shuffles (YMM/ZMM).
392 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
393 defm : BWWriteResPair<WriteBlend, [BWPort5], 1, [1], 1, 5>; // Vector blends.
394 defm : BWWriteResPair<WriteBlendY, [BWPort5], 1, [1], 1, 6>; // Vector blends (YMM/ZMM).
395 defm : X86WriteResPairUnsupported<WriteBlendZ>;
396 defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2], 2, 5>; // Vector variable blends.
397 defm : BWWriteResPair<WriteVarBlendY, [BWPort5], 2, [2], 2, 6>; // Vector variable blends (YMM/ZMM).
398 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
399 defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 7, [1, 2], 3, 5>; // Vector MPSAD.
400 defm : BWWriteResPair<WriteMPSADY, [BWPort0, BWPort5], 7, [1, 2], 3, 6>; // Vector MPSAD.
401 defm : X86WriteResPairUnsupported<WriteMPSADZ>;
402 defm : BWWriteResPair<WritePSADBW, [BWPort0], 5, [1], 1, 5>; // Vector PSADBW.
403 defm : BWWriteResPair<WritePSADBWX, [BWPort0], 5, [1], 1, 5>; // Vector PSADBW.
404 defm : BWWriteResPair<WritePSADBWY, [BWPort0], 5, [1], 1, 6>; // Vector PSADBW (YMM/ZMM).
405 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
406 defm : BWWriteResPair<WritePHMINPOS, [BWPort0], 5>; // Vector PHMINPOS.
408 // Vector integer shifts.
409 defm : BWWriteResPair<WriteVecShift, [BWPort0], 1, [1], 1, 5>;
410 defm : BWWriteResPair<WriteVecShiftX, [BWPort0,BWPort5], 2, [1,1], 2, 5>;
411 defm : X86WriteRes<WriteVecShiftY, [BWPort0,BWPort5], 4, [1,1], 2>;
412 defm : X86WriteRes<WriteVecShiftYLd, [BWPort0,BWPort23], 7, [1,1], 2>;
413 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
415 defm : BWWriteResPair<WriteVecShiftImm, [BWPort0], 1, [1], 1, 5>;
416 defm : BWWriteResPair<WriteVecShiftImmX, [BWPort0], 1, [1], 1, 5>; // Vector integer immediate shifts (XMM).
417 defm : BWWriteResPair<WriteVecShiftImmY, [BWPort0], 1, [1], 1, 6>; // Vector integer immediate shifts (YMM/ZMM).
418 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
419 defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 3, [2,1], 3, 5>; // Variable vector shifts.
420 defm : BWWriteResPair<WriteVarVecShiftY, [BWPort0, BWPort5], 3, [2,1], 3, 6>; // Variable vector shifts (YMM/ZMM).
421 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
423 // Vector insert/extract operations.
424 def : WriteRes<WriteVecInsert, [BWPort5]> {
427 let ResourceCycles = [2];
429 def : WriteRes<WriteVecInsertLd, [BWPort5,BWPort23]> {
434 def : WriteRes<WriteVecExtract, [BWPort0,BWPort5]> {
438 def : WriteRes<WriteVecExtractSt, [BWPort4,BWPort5,BWPort237]> {
443 // Conversion between integer and float.
444 defm : BWWriteResPair<WriteCvtSS2I, [BWPort1], 3>;
445 defm : BWWriteResPair<WriteCvtPS2I, [BWPort1], 3>;
446 defm : BWWriteResPair<WriteCvtPS2IY, [BWPort1], 3>;
447 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
448 defm : BWWriteResPair<WriteCvtSD2I, [BWPort1], 3>;
449 defm : BWWriteResPair<WriteCvtPD2I, [BWPort1], 3>;
450 defm : BWWriteResPair<WriteCvtPD2IY, [BWPort1], 3>;
451 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
453 defm : BWWriteResPair<WriteCvtI2SS, [BWPort1], 4>;
454 defm : BWWriteResPair<WriteCvtI2PS, [BWPort1], 4>;
455 defm : BWWriteResPair<WriteCvtI2PSY, [BWPort1], 4>;
456 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
457 defm : BWWriteResPair<WriteCvtI2SD, [BWPort1], 4>;
458 defm : BWWriteResPair<WriteCvtI2PD, [BWPort1], 4>;
459 defm : BWWriteResPair<WriteCvtI2PDY, [BWPort1], 4>;
460 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
462 defm : BWWriteResPair<WriteCvtSS2SD, [BWPort1], 3>;
463 defm : BWWriteResPair<WriteCvtPS2PD, [BWPort1], 3>;
464 defm : BWWriteResPair<WriteCvtPS2PDY, [BWPort1], 3>;
465 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
466 defm : BWWriteResPair<WriteCvtSD2SS, [BWPort1], 3>;
467 defm : BWWriteResPair<WriteCvtPD2PS, [BWPort1], 3>;
468 defm : BWWriteResPair<WriteCvtPD2PSY, [BWPort1], 3>;
469 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
471 defm : X86WriteRes<WriteCvtPH2PS, [BWPort0,BWPort5], 2, [1,1], 2>;
472 defm : X86WriteRes<WriteCvtPH2PSY, [BWPort0,BWPort5], 2, [1,1], 2>;
473 defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
474 defm : X86WriteRes<WriteCvtPH2PSLd, [BWPort0,BWPort23], 6, [1,1], 2>;
475 defm : X86WriteRes<WriteCvtPH2PSYLd, [BWPort0,BWPort23], 6, [1,1], 2>;
476 defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
478 defm : X86WriteRes<WriteCvtPS2PH, [BWPort1,BWPort5], 4, [1,1], 2>;
479 defm : X86WriteRes<WriteCvtPS2PHY, [BWPort1,BWPort5], 6, [1,1], 2>;
480 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
481 defm : X86WriteRes<WriteCvtPS2PHSt, [BWPort1,BWPort4,BWPort237], 5, [1,1,1], 3>;
482 defm : X86WriteRes<WriteCvtPS2PHYSt, [BWPort1,BWPort4,BWPort237], 7, [1,1,1], 3>;
483 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
485 // Strings instructions.
487 // Packed Compare Implicit Length Strings, Return Mask
488 def : WriteRes<WritePCmpIStrM, [BWPort0]> {
491 let ResourceCycles = [3];
493 def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
496 let ResourceCycles = [3,1];
499 // Packed Compare Explicit Length Strings, Return Mask
500 def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
503 let ResourceCycles = [4,3,1,1];
505 def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
507 let NumMicroOps = 10;
508 let ResourceCycles = [4,3,1,1,1];
511 // Packed Compare Implicit Length Strings, Return Index
512 def : WriteRes<WritePCmpIStrI, [BWPort0]> {
515 let ResourceCycles = [3];
517 def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
520 let ResourceCycles = [3,1];
523 // Packed Compare Explicit Length Strings, Return Index
524 def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
527 let ResourceCycles = [4,3,1];
529 def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
532 let ResourceCycles = [4,3,1,1];
535 // MOVMSK Instructions.
536 def : WriteRes<WriteFMOVMSK, [BWPort0]> { let Latency = 3; }
537 def : WriteRes<WriteVecMOVMSK, [BWPort0]> { let Latency = 3; }
538 def : WriteRes<WriteVecMOVMSKY, [BWPort0]> { let Latency = 3; }
539 def : WriteRes<WriteMMXMOVMSK, [BWPort0]> { let Latency = 1; }
542 def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
545 let ResourceCycles = [1];
547 def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
550 let ResourceCycles = [1,1];
553 def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
556 let ResourceCycles = [2];
558 def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
561 let ResourceCycles = [2,1];
564 def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
566 let NumMicroOps = 11;
567 let ResourceCycles = [2,7,2];
569 def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
571 let NumMicroOps = 11;
572 let ResourceCycles = [2,7,1,1];
575 // Carry-less multiplication instructions.
576 defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>;
578 // Catch-all for expensive system instructions.
579 def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
582 defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector shuffles.
583 defm : BWWriteResPair<WriteFVarShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector variable shuffles.
584 defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3, [1], 1, 6>; // 256-bit width vector shuffles.
585 defm : BWWriteResPair<WriteVarShuffle256, [BWPort5], 3, [1], 1, 6>; // 256-bit width vector variable shuffles.
587 // Old microcoded instructions that nobody use.
588 def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
590 // Fence instructions.
591 def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
594 def : WriteRes<WriteLDMXCSR, [BWPort0,BWPort23,BWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
595 def : WriteRes<WriteSTMXCSR, [BWPort4,BWPort5,BWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
597 // Nop, not very useful expect it provides a model for nops!
598 def : WriteRes<WriteNop, []>;
600 ////////////////////////////////////////////////////////////////////////////////
601 // Horizontal add/sub instructions.
602 ////////////////////////////////////////////////////////////////////////////////
604 defm : BWWriteResPair<WriteFHAdd, [BWPort1,BWPort5], 5, [1,2], 3, 5>;
605 defm : BWWriteResPair<WriteFHAddY, [BWPort1,BWPort5], 5, [1,2], 3, 6>;
606 defm : BWWriteResPair<WritePHAdd, [BWPort5,BWPort15], 3, [2,1], 3, 5>;
607 defm : BWWriteResPair<WritePHAddX, [BWPort5,BWPort15], 3, [2,1], 3, 5>;
608 defm : BWWriteResPair<WritePHAddY, [BWPort5,BWPort15], 3, [2,1], 3, 6>;
612 def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
615 let ResourceCycles = [1];
617 def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQ(Y?)rr",
620 def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
623 let ResourceCycles = [1];
625 def: InstRW<[BWWriteResGroup2], (instregex "COM(P?)_FST0r",
628 def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
631 let ResourceCycles = [1];
633 def: InstRW<[BWWriteResGroup3], (instrs MMX_MOVQ2DQrr)>;
635 def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
638 let ResourceCycles = [1];
640 def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
642 def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
645 let ResourceCycles = [1];
647 def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>;
649 def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
652 let ResourceCycles = [1];
654 def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>;
656 def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
659 let ResourceCycles = [1];
661 def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr")>;
663 def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
666 let ResourceCycles = [1];
668 def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDD(Y?)rri")>;
670 def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
673 let ResourceCycles = [1];
675 def: InstRW<[BWWriteResGroup9], (instrs SGDT64m,
681 def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
684 let ResourceCycles = [1,1];
686 def: InstRW<[BWWriteResGroup10], (instrs FBSTPm)>;
687 def: InstRW<[BWWriteResGroup10], (instregex "ST_FP(32|64|80)m")>;
689 def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
692 let ResourceCycles = [2];
694 def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>;
696 def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
699 let ResourceCycles = [2];
701 def: InstRW<[BWWriteResGroup14], (instrs LFENCE,
706 def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {
709 let ResourceCycles = [1,1];
711 def: InstRW<[BWWriteResGroup15], (instregex "(V?)CVTPS2PDrr",
714 def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
717 let ResourceCycles = [1,1];
719 def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
721 def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
724 let ResourceCycles = [1,1];
726 def: InstRW<[BWWriteResGroup17], (instrs MMX_MOVDQ2Qrr)>;
728 def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
731 let ResourceCycles = [1,1];
733 def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>;
735 def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
738 let ResourceCycles = [1,1];
740 def: InstRW<[BWWriteResGroup20], (instrs CWD,
745 ADC64i32, SBB64i32)>;
747 def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
750 let ResourceCycles = [1,1,1];
752 def: InstRW<[BWWriteResGroup22], (instrs FNSTCW16m)>;
754 def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
757 let ResourceCycles = [1,1,1];
759 def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
761 def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
764 let ResourceCycles = [1,1,1];
766 def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
767 STOSB, STOSL, STOSQ, STOSW)>;
768 def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr")>;
770 def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
773 let ResourceCycles = [1];
775 def: InstRW<[BWWriteResGroup27], (instrs MMX_CVTPI2PSirr)>;
776 def: InstRW<[BWWriteResGroup27], (instregex "P(DEP|EXT)(32|64)rr",
777 "(V?)CVTDQ2PS(Y?)rr")>;
779 def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
782 let ResourceCycles = [1];
784 def: InstRW<[BWWriteResGroup28], (instrs VPBROADCASTBrr,
787 def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
790 let ResourceCycles = [2,1];
792 def: InstRW<[BWWriteResGroup33], (instrs MMX_PACKSSDWirr,
796 def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
799 let ResourceCycles = [1,2];
801 def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
803 def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
806 let ResourceCycles = [1,2];
808 def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r(1|i)",
809 "RCR(8|16|32|64)r(1|i)")>;
811 def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
814 let ResourceCycles = [1,1,1,1];
816 def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
818 def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
821 let ResourceCycles = [1,1,1,1];
823 def: InstRW<[BWWriteResGroup38], (instrs CALL64pcrel32)>;
825 def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
828 let ResourceCycles = [1,1];
830 def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI64rr",
831 "(V?)CVT(T?)SD2SIrr",
832 "(V?)CVT(T?)SS2SI64rr",
833 "(V?)CVT(T?)SS2SIrr")>;
835 def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
838 let ResourceCycles = [1,1];
840 def: InstRW<[BWWriteResGroup40], (instrs VCVTPS2PDYrr)>;
842 def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
845 let ResourceCycles = [1,1];
847 def: InstRW<[BWWriteResGroup41], (instrs FNSTSW16r)>;
849 def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
852 let ResourceCycles = [1,1];
854 def: InstRW<[BWWriteResGroup42], (instrs MMX_CVTPI2PDirr)>;
855 def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVT(T?)PD2PIirr",
856 "MMX_CVT(T?)PS2PIirr",
863 "(V?)CVT(T?)PD2DQrr")>;
865 def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
868 let ResourceCycles = [1,1,1];
870 def: InstRW<[BWWriteResGroup43], (instrs FNSTSWm)>;
872 def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
875 let ResourceCycles = [1,1,1];
877 def: InstRW<[BWWriteResGroup44], (instregex "IST(T?)_FP(16|32|64)m",
880 def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
883 let ResourceCycles = [4];
885 def: InstRW<[BWWriteResGroup45], (instrs FNCLEX)>;
887 def BWWriteResGroup46 : SchedWriteRes<[]> {
890 let ResourceCycles = [];
892 def: InstRW<[BWWriteResGroup46], (instrs VZEROUPPER)>;
894 def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
897 let ResourceCycles = [1];
899 def: InstRW<[BWWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
901 def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
904 let ResourceCycles = [1];
906 def: InstRW<[BWWriteResGroup49], (instregex "MOVSX(16|32|64)rm(8|16|32)",
907 "MOVZX(16|32|64)rm(8|16)")>;
908 def: InstRW<[BWWriteResGroup49], (instrs VBROADCASTSSrm,
909 VMOVDDUPrm, MOVDDUPrm,
910 VMOVSHDUPrm, MOVSHDUPrm,
911 VMOVSLDUPrm, MOVSLDUPrm,
915 def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
918 let ResourceCycles = [1,2];
920 def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr")>;
922 def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
925 let ResourceCycles = [1,1,1];
927 def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
929 def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
932 let ResourceCycles = [1,4];
934 def: InstRW<[BWWriteResGroup54], (instrs PAUSE)>;
936 def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
939 let ResourceCycles = [1,4];
941 def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>;
943 def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
946 let ResourceCycles = [1,1,4];
948 def: InstRW<[BWWriteResGroup57], (instregex "PUSHF(16|64)")>;
950 def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
953 let ResourceCycles = [1];
955 def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m")>;
956 def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128,
966 def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
969 let ResourceCycles = [1,1];
971 def: InstRW<[BWWriteResGroup59], (instrs CVTPS2PDrm, VCVTPS2PDrm,
972 CVTSS2SDrm, VCVTSS2SDrm,
973 CVTSS2SDrm_Int, VCVTSS2SDrm_Int,
977 def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
980 let ResourceCycles = [1,1];
982 def: InstRW<[BWWriteResGroup60], (instrs VCVTDQ2PDYrr,
987 def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
990 let ResourceCycles = [1,1];
992 def: InstRW<[BWWriteResGroup62], (instrs FARJMP64m)>;
993 def: InstRW<[BWWriteResGroup62], (instregex "JMP(16|32|64)m")>;
995 def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
998 let ResourceCycles = [1,1];
1000 def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
1001 "MOVBE(16|32|64)rm")>;
1003 def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
1005 let NumMicroOps = 2;
1006 let ResourceCycles = [1,1];
1008 def: InstRW<[BWWriteResGroup65], (instrs VINSERTF128rm,
1012 def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
1014 let NumMicroOps = 2;
1015 let ResourceCycles = [1,1];
1017 def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
1018 def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>;
1020 def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
1022 let NumMicroOps = 4;
1023 let ResourceCycles = [1,1,1,1];
1025 def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
1027 def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1029 let NumMicroOps = 4;
1030 let ResourceCycles = [1,1,1,1];
1032 def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)",
1033 "SHL(8|16|32|64)m(1|i)",
1034 "SHR(8|16|32|64)m(1|i)")>;
1036 def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1038 let NumMicroOps = 4;
1039 let ResourceCycles = [1,1,1,1];
1041 def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm",
1042 "PUSH(16|32|64)rmm")>;
1044 def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
1046 let NumMicroOps = 6;
1047 let ResourceCycles = [1,5];
1049 def: InstRW<[BWWriteResGroup71], (instrs STD)>;
1051 def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
1053 let NumMicroOps = 2;
1054 let ResourceCycles = [1,1];
1056 def: InstRW<[BWWriteResGroup73], (instrs VPSLLVQYrm,
1059 def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
1061 let NumMicroOps = 2;
1062 let ResourceCycles = [1,1];
1064 def: InstRW<[BWWriteResGroup74], (instregex "FCOM(P?)(32|64)m")>;
1066 def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
1068 let NumMicroOps = 2;
1069 let ResourceCycles = [1,1];
1071 def: InstRW<[BWWriteResGroup77], (instrs VPBLENDDYrmi)>;
1073 def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
1075 let NumMicroOps = 3;
1076 let ResourceCycles = [2,1];
1078 def: InstRW<[BWWriteResGroup79], (instrs MMX_PACKSSDWirm,
1082 def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
1084 let NumMicroOps = 3;
1085 let ResourceCycles = [1,2];
1087 def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64,
1088 SCASB, SCASL, SCASQ, SCASW)>;
1090 def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
1092 let NumMicroOps = 3;
1093 let ResourceCycles = [1,1,1];
1095 def: InstRW<[BWWriteResGroup82], (instrs FLDCW16m)>;
1097 def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1099 let NumMicroOps = 3;
1100 let ResourceCycles = [1,1,1];
1102 def: InstRW<[BWWriteResGroup84], (instrs LRETQ, RETQ)>;
1104 def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1106 let NumMicroOps = 5;
1107 let ResourceCycles = [1,1,1,2];
1109 def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)",
1110 "ROR(8|16|32|64)m(1|i)")>;
1112 def BWWriteResGroup87_1 : SchedWriteRes<[BWPort06]> {
1114 let NumMicroOps = 2;
1115 let ResourceCycles = [2];
1117 def: InstRW<[BWWriteResGroup87_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
1118 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
1120 def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1122 let NumMicroOps = 5;
1123 let ResourceCycles = [1,1,1,2];
1125 def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
1127 def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1129 let NumMicroOps = 5;
1130 let ResourceCycles = [1,1,1,1,1];
1132 def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m")>;
1133 def: InstRW<[BWWriteResGroup89], (instrs FARCALL64m)>;
1135 def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
1137 let NumMicroOps = 7;
1138 let ResourceCycles = [2,2,1,2];
1140 def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
1142 def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
1144 let NumMicroOps = 2;
1145 let ResourceCycles = [1,1];
1147 def: InstRW<[BWWriteResGroup91], (instrs MMX_CVTPI2PSirm,
1150 def: InstRW<[BWWriteResGroup91], (instregex "P(DEP|EXT)(32|64)rm")>;
1152 def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
1154 let NumMicroOps = 2;
1155 let ResourceCycles = [1,1];
1157 def: InstRW<[BWWriteResGroup92], (instrs VPMOVSXBDYrm,
1165 def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
1167 let NumMicroOps = 5;
1168 let ResourceCycles = [1,1,1,2];
1170 def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m(1|i)",
1171 "RCR(8|16|32|64)m(1|i)")>;
1173 def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1175 let NumMicroOps = 6;
1176 let ResourceCycles = [1,1,1,3];
1178 def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
1180 def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1182 let NumMicroOps = 6;
1183 let ResourceCycles = [1,1,1,2,1];
1185 def : SchedAlias<WriteADCRMW, BWWriteResGroup100>;
1186 def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL",
1187 "ROR(8|16|32|64)mCL",
1188 "SAR(8|16|32|64)mCL",
1189 "SHL(8|16|32|64)mCL",
1190 "SHR(8|16|32|64)mCL")>;
1192 def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
1194 let NumMicroOps = 2;
1195 let ResourceCycles = [1,1];
1197 def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1198 "ILD_F(16|32|64)m")>;
1199 def: InstRW<[BWWriteResGroup101], (instrs VCVTPS2DQYrm,
1202 def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1204 let NumMicroOps = 3;
1205 let ResourceCycles = [1,1,1];
1207 def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSS2SI(64)?rm",
1208 "(V?)CVT(T?)SD2SI64rm",
1209 "(V?)CVT(T?)SD2SIrm",
1211 "(V?)CVTTSS2SIrm")>;
1213 def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1215 let NumMicroOps = 3;
1216 let ResourceCycles = [1,1,1];
1218 def: InstRW<[BWWriteResGroup106], (instrs VCVTPS2PDYrm)>;
1220 def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
1222 let NumMicroOps = 3;
1223 let ResourceCycles = [1,1,1];
1225 def: InstRW<[BWWriteResGroup107], (instrs CVTPD2PSrm,
1229 def: InstRW<[BWWriteResGroup107], (instregex "MMX_CVT(T?)PD2PIirm",
1233 def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
1235 let NumMicroOps = 3;
1236 let ResourceCycles = [1,1,1];
1238 def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm",
1239 "VPBROADCASTW(Y?)rm")>;
1241 def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1243 let NumMicroOps = 5;
1244 let ResourceCycles = [1,1,3];
1246 def: InstRW<[BWWriteResGroup112], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;
1248 def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
1250 let NumMicroOps = 5;
1251 let ResourceCycles = [1,2,1,1];
1253 def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
1254 "LSL(16|32|64)rm")>;
1256 def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
1258 let NumMicroOps = 2;
1259 let ResourceCycles = [1,1];
1261 def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm")>;
1263 def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
1265 let NumMicroOps = 3;
1266 let ResourceCycles = [2,1];
1268 def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)(16|32)m")>;
1270 def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
1272 let NumMicroOps = 4;
1273 let ResourceCycles = [1,1,1,1];
1275 def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
1277 def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
1279 let NumMicroOps = 1;
1280 let ResourceCycles = [1,3]; // Really 2.5 cycle throughput
1282 def : SchedAlias<WriteFDiv, BWWriteResGroup122_1>; // TODO - convert to ZnWriteResFpuPair
1284 def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
1286 let NumMicroOps = 2;
1287 let ResourceCycles = [1,1];
1289 def: InstRW<[BWWriteResGroup123], (instregex "MUL_F(32|64)m")>;
1290 def: InstRW<[BWWriteResGroup123], (instrs VPCMPGTQYrm)>;
1292 def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
1294 let NumMicroOps = 3;
1295 let ResourceCycles = [1,1,1];
1297 def: InstRW<[BWWriteResGroup128], (instrs VCVTDQ2PDYrm)>;
1299 def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1301 let NumMicroOps = 7;
1302 let ResourceCycles = [2,2,3];
1304 def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
1305 "RCR(16|32|64)rCL")>;
1307 def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
1309 let NumMicroOps = 9;
1310 let ResourceCycles = [1,4,1,3];
1312 def: InstRW<[BWWriteResGroup132], (instrs RCL8rCL)>;
1314 def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
1316 let NumMicroOps = 11;
1317 let ResourceCycles = [2,9];
1319 def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
1320 def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
1322 def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
1324 let NumMicroOps = 3;
1325 let ResourceCycles = [2,1];
1327 def: InstRW<[BWWriteResGroup135], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1329 def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
1331 let NumMicroOps = 1;
1332 let ResourceCycles = [1,4];
1334 def : SchedAlias<WriteFDiv64, BWWriteResGroup139_1>; // TODO - convert to ZnWriteResFpuPair
1336 def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1338 let NumMicroOps = 3;
1339 let ResourceCycles = [1,1,1];
1341 def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI(16|32)m")>;
1343 def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
1345 let NumMicroOps = 8;
1346 let ResourceCycles = [2,2,1,3];
1348 def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
1350 def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
1352 let NumMicroOps = 10;
1353 let ResourceCycles = [2,3,1,4];
1355 def: InstRW<[BWWriteResGroup145], (instrs RCR8rCL)>;
1357 def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
1359 let NumMicroOps = 12;
1360 let ResourceCycles = [2,1,4,5];
1362 def: InstRW<[BWWriteResGroup146], (instrs XCH_F)>;
1364 def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
1366 let NumMicroOps = 1;
1367 let ResourceCycles = [1];
1369 def: InstRW<[BWWriteResGroup147], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1371 def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1373 let NumMicroOps = 10;
1374 let ResourceCycles = [1,1,1,4,1,2];
1376 def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
1378 def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
1380 let NumMicroOps = 2;
1381 let ResourceCycles = [1,1,5];
1383 def : SchedAlias<WriteFDivLd, BWWriteResGroup150>; // TODO - convert to ZnWriteResFpuPair
1385 def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1387 let NumMicroOps = 14;
1388 let ResourceCycles = [1,1,1,4,2,5];
1390 def: InstRW<[BWWriteResGroup153], (instrs CMPXCHG8B)>;
1392 def BWWriteResGroup154 : SchedWriteRes<[BWPort5,BWPort6]> {
1394 let NumMicroOps = 20;
1395 let ResourceCycles = [1,1];
1397 def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
1399 def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
1401 let NumMicroOps = 8;
1402 let ResourceCycles = [1,1,1,5];
1404 def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
1405 def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
1407 def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1409 let NumMicroOps = 11;
1410 let ResourceCycles = [2,1,1,3,1,3];
1412 def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
1414 def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
1416 let NumMicroOps = 2;
1417 let ResourceCycles = [1,1,8];
1419 def : SchedAlias<WriteFDiv64Ld, BWWriteResGroup161>; // TODO - convert to ZnWriteResFpuPair
1421 def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
1423 let NumMicroOps = 1;
1424 let ResourceCycles = [1];
1426 def: InstRW<[BWWriteResGroup165], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1428 def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1430 let NumMicroOps = 8;
1431 let ResourceCycles = [1,1,1,1,1,1,2];
1433 def: InstRW<[BWWriteResGroup167], (instrs INSB, INSL, INSW)>;
1435 def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
1437 let NumMicroOps = 2;
1438 let ResourceCycles = [1,1];
1440 def: InstRW<[BWWriteResGroup169], (instregex "DIV_F(32|64)m")>;
1442 def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1444 let NumMicroOps = 19;
1445 let ResourceCycles = [2,1,4,1,1,4,6];
1447 def: InstRW<[BWWriteResGroup171], (instrs CMPXCHG16B)>;
1449 def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1451 let NumMicroOps = 18;
1452 let ResourceCycles = [1,1,16];
1454 def: InstRW<[BWWriteResGroup172], (instrs POPF64)>;
1456 def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1458 let NumMicroOps = 19;
1459 let ResourceCycles = [3,1,15];
1461 def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
1463 def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1465 let NumMicroOps = 3;
1466 let ResourceCycles = [1,1,1];
1468 def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI(16|32)m")>;
1470 def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
1472 let NumMicroOps = 2;
1473 let ResourceCycles = [1,1];
1475 def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F(32|64)m")>;
1477 def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1479 let NumMicroOps = 3;
1480 let ResourceCycles = [1,1,1];
1482 def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI(16|32)m")>;
1484 def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1486 let NumMicroOps = 7;
1487 let ResourceCycles = [1,3,2,1];
1489 def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERDPDrm, VPGATHERDQrm,
1490 VGATHERQPDrm, VPGATHERQQrm)>;
1492 def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1494 let NumMicroOps = 9;
1495 let ResourceCycles = [1,3,4,1];
1497 def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
1498 VGATHERQPDYrm, VPGATHERQQYrm)>;
1500 def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1502 let NumMicroOps = 9;
1503 let ResourceCycles = [1,5,2,1];
1505 def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSrm, VPGATHERQDrm)>;
1507 def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1509 let NumMicroOps = 10;
1510 let ResourceCycles = [1,4,4,1];
1512 def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPSrm, VPGATHERDDrm,
1513 VGATHERQPSYrm, VPGATHERQDYrm)>;
1515 def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1517 let NumMicroOps = 14;
1518 let ResourceCycles = [1,4,8,1];
1520 def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;
1522 def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1524 let NumMicroOps = 27;
1525 let ResourceCycles = [1,5,1,1,19];
1527 def: InstRW<[BWWriteResGroup185], (instrs XSAVE64)>;
1529 def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1531 let NumMicroOps = 28;
1532 let ResourceCycles = [1,6,1,1,19];
1534 def: InstRW<[BWWriteResGroup186], (instrs XSAVE)>;
1535 def: InstRW<[BWWriteResGroup186], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
1537 def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
1539 let NumMicroOps = 23;
1540 let ResourceCycles = [1,5,3,4,10];
1542 def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
1545 def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1547 let NumMicroOps = 23;
1548 let ResourceCycles = [1,5,2,1,4,10];
1550 def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
1553 def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
1555 let NumMicroOps = 22;
1556 let ResourceCycles = [2,20];
1558 def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
1560 def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
1562 let NumMicroOps = 64;
1563 let ResourceCycles = [2,2,8,1,10,2,39];
1565 def: InstRW<[BWWriteResGroup197], (instrs FLDENVm)>;
1567 def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
1569 let NumMicroOps = 88;
1570 let ResourceCycles = [4,4,31,1,2,1,45];
1572 def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
1574 def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
1576 let NumMicroOps = 90;
1577 let ResourceCycles = [4,2,33,1,2,1,47];
1579 def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
1581 def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
1583 let NumMicroOps = 15;
1584 let ResourceCycles = [6,3,6];
1586 def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>;
1588 def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
1590 let NumMicroOps = 100;
1591 let ResourceCycles = [9,9,11,8,1,11,21,30];
1593 def: InstRW<[BWWriteResGroup202], (instrs FSTENVm)>;
1595 def: InstRW<[WriteZero], (instrs CLC)>;
1598 // Instruction variants handled by the renamer. These might not need execution
1599 // ports in certain conditions.
1600 // See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
1601 // section "Haswell and Broadwell Pipeline" > "Register allocation and
1603 // These can be investigated with llvm-exegesis, e.g.
1604 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1605 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1607 def BWWriteZeroLatency : SchedWriteRes<[]> {
1611 def BWWriteZeroIdiom : SchedWriteVariant<[
1612 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1613 SchedVar<NoSchedPred, [WriteALU]>
1615 def : InstRW<[BWWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
1618 def BWWriteFZeroIdiom : SchedWriteVariant<[
1619 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1620 SchedVar<NoSchedPred, [WriteFLogic]>
1622 def : InstRW<[BWWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr,
1625 def BWWriteFZeroIdiomY : SchedWriteVariant<[
1626 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1627 SchedVar<NoSchedPred, [WriteFLogicY]>
1629 def : InstRW<[BWWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>;
1631 def BWWriteVZeroIdiomLogicX : SchedWriteVariant<[
1632 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1633 SchedVar<NoSchedPred, [WriteVecLogicX]>
1635 def : InstRW<[BWWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>;
1637 def BWWriteVZeroIdiomLogicY : SchedWriteVariant<[
1638 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1639 SchedVar<NoSchedPred, [WriteVecLogicY]>
1641 def : InstRW<[BWWriteVZeroIdiomLogicY], (instrs VPXORYrr)>;
1643 def BWWriteVZeroIdiomALUX : SchedWriteVariant<[
1644 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1645 SchedVar<NoSchedPred, [WriteVecALUX]>
1647 def : InstRW<[BWWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr,
1651 PCMPGTBrr, VPCMPGTBrr,
1652 PCMPGTDrr, VPCMPGTDrr,
1653 PCMPGTWrr, VPCMPGTWrr)>;
1655 def BWWriteVZeroIdiomALUY : SchedWriteVariant<[
1656 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1657 SchedVar<NoSchedPred, [WriteVecALUY]>
1659 def : InstRW<[BWWriteVZeroIdiomALUY], (instrs VPSUBBYrr,
1667 def BWWritePCMPGTQ : SchedWriteRes<[BWPort0]> {
1669 let NumMicroOps = 1;
1670 let ResourceCycles = [1];
1673 def BWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
1674 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1675 SchedVar<NoSchedPred, [BWWritePCMPGTQ]>
1677 def : InstRW<[BWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
1681 // CMOVs that use both Z and C flag require an extra uop.
1682 def BWWriteCMOVA_CMOVBErr : SchedWriteRes<[BWPort06,BWPort0156]> {
1684 let ResourceCycles = [1,1];
1685 let NumMicroOps = 2;
1688 def BWWriteCMOVA_CMOVBErm : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1690 let ResourceCycles = [1,1,1];
1691 let NumMicroOps = 3;
1694 def BWCMOVA_CMOVBErr : SchedWriteVariant<[
1695 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [BWWriteCMOVA_CMOVBErr]>,
1696 SchedVar<NoSchedPred, [WriteCMOV]>
1699 def BWCMOVA_CMOVBErm : SchedWriteVariant<[
1700 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [BWWriteCMOVA_CMOVBErm]>,
1701 SchedVar<NoSchedPred, [WriteCMOV.Folded]>
1704 def : InstRW<[BWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
1705 def : InstRW<[BWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
1707 // SETCCs that use both Z and C flag require an extra uop.
1708 def BWWriteSETA_SETBEr : SchedWriteRes<[BWPort06,BWPort0156]> {
1710 let ResourceCycles = [1,1];
1711 let NumMicroOps = 2;
1714 def BWWriteSETA_SETBEm : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
1716 let ResourceCycles = [1,1,1,1];
1717 let NumMicroOps = 4;
1720 def BWSETA_SETBErr : SchedWriteVariant<[
1721 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [BWWriteSETA_SETBEr]>,
1722 SchedVar<NoSchedPred, [WriteSETCC]>
1725 def BWSETA_SETBErm : SchedWriteVariant<[
1726 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [BWWriteSETA_SETBEm]>,
1727 SchedVar<NoSchedPred, [WriteSETCCStore]>
1730 def : InstRW<[BWSETA_SETBErr], (instrs SETCCr)>;
1731 def : InstRW<[BWSETA_SETBErm], (instrs SETCCm)>;