1 //=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the machine model for Haswell to support instruction
10 // scheduling and other instruction cost heuristics.
12 // Note that we define some instructions here that are not supported by haswell,
13 // but we still have to define them because KNL uses the HSW model.
14 // They are currently tagged with a comment `Unsupported = 1`.
15 // FIXME: Use Unsupported = 1 once KNL has its own model.
17 //===----------------------------------------------------------------------===//
19 def HaswellModel : SchedMachineModel {
20 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
21 // instructions per cycle.
23 let MicroOpBufferSize = 192; // Based on the reorder buffer.
25 let MispredictPenalty = 16;
27 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
28 let LoopMicroOpBufferSize = 50;
30 // This flag is set to allow the scheduler to assign a default model to
31 // unrecognized opcodes.
32 let CompleteModel = 0;
35 let SchedModel = HaswellModel in {
37 // Haswell can issue micro-ops to 8 different ports in one cycle.
39 // Ports 0, 1, 5, and 6 handle all computation.
40 // Port 4 gets the data half of stores. Store data can be available later than
41 // the store address, but since we don't model the latency of stores, we can
43 // Ports 2 and 3 are identical. They handle loads and the address half of
44 // stores. Port 7 can handle address calculations.
45 def HWPort0 : ProcResource<1>;
46 def HWPort1 : ProcResource<1>;
47 def HWPort2 : ProcResource<1>;
48 def HWPort3 : ProcResource<1>;
49 def HWPort4 : ProcResource<1>;
50 def HWPort5 : ProcResource<1>;
51 def HWPort6 : ProcResource<1>;
52 def HWPort7 : ProcResource<1>;
54 // Many micro-ops are capable of issuing on multiple ports.
55 def HWPort01 : ProcResGroup<[HWPort0, HWPort1]>;
56 def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>;
57 def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>;
58 def HWPort04 : ProcResGroup<[HWPort0, HWPort4]>;
59 def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>;
60 def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>;
61 def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>;
62 def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>;
63 def HWPort56 : ProcResGroup<[HWPort5, HWPort6]>;
64 def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
65 def HWPort056 : ProcResGroup<[HWPort0, HWPort5, HWPort6]>;
66 def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
68 // 60 Entry Unified Scheduler
69 def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4,
70 HWPort5, HWPort6, HWPort7]> {
74 // Integer division issued on port 0.
75 def HWDivider : ProcResource<1>;
76 // FP division and sqrt on port 0.
77 def HWFPDivider : ProcResource<1>;
79 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
80 // cycles after the memory operand.
81 def : ReadAdvance<ReadAfterLd, 5>;
83 // Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available
84 // until 5/6/7 cycles after the memory operand.
85 def : ReadAdvance<ReadAfterVecLd, 5>;
86 def : ReadAdvance<ReadAfterVecXLd, 6>;
87 def : ReadAdvance<ReadAfterVecYLd, 7>;
89 def : ReadAdvance<ReadInt2Fpu, 0>;
91 // Many SchedWrites are defined in pairs with and without a folded load.
92 // Instructions with folded loads are usually micro-fused, so they only appear
93 // as two micro-ops when queued in the reservation station.
94 // This multiclass defines the resource usage for variants with and without
96 multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
97 list<ProcResourceKind> ExePorts,
98 int Lat, list<int> Res = [1], int UOps = 1,
100 // Register variant is using a single cycle on ExePort.
101 def : WriteRes<SchedRW, ExePorts> {
103 let ResourceCycles = Res;
104 let NumMicroOps = UOps;
107 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
108 // the latency (default = 5).
109 def : WriteRes<SchedRW.Folded, !listconcat([HWPort23], ExePorts)> {
110 let Latency = !add(Lat, LoadLat);
111 let ResourceCycles = !listconcat([1], Res);
112 let NumMicroOps = !add(UOps, 1);
116 // A folded store needs a cycle on port 4 for the store data, and an extra port
117 // 2/3/7 cycle to recompute the address.
118 def : WriteRes<WriteRMW, [HWPort237,HWPort4]>;
120 // Store_addr on 237.
122 defm : X86WriteRes<WriteStore, [HWPort237, HWPort4], 1, [1,1], 1>;
123 defm : X86WriteRes<WriteStoreNT, [HWPort237, HWPort4], 1, [1,1], 2>;
124 defm : X86WriteRes<WriteLoad, [HWPort23], 5, [1], 1>;
125 defm : X86WriteRes<WriteMove, [HWPort0156], 1, [1], 1>;
126 def : WriteRes<WriteZero, []>;
129 defm : HWWriteResPair<WriteALU, [HWPort0156], 1>;
130 defm : HWWriteResPair<WriteADC, [HWPort06, HWPort0156], 2, [1,1], 2>;
132 // Integer multiplication.
133 defm : HWWriteResPair<WriteIMul8, [HWPort1], 3>;
134 defm : HWWriteResPair<WriteIMul16, [HWPort1,HWPort06,HWPort0156], 4, [1,1,2], 4>;
135 defm : X86WriteRes<WriteIMul16Imm, [HWPort1,HWPort0156], 4, [1,1], 2>;
136 defm : X86WriteRes<WriteIMul16ImmLd, [HWPort1,HWPort0156,HWPort23], 8, [1,1,1], 3>;
137 defm : HWWriteResPair<WriteIMul16Reg, [HWPort1], 3>;
138 defm : HWWriteResPair<WriteIMul32, [HWPort1,HWPort06,HWPort0156], 4, [1,1,1], 3>;
139 defm : HWWriteResPair<WriteIMul32Imm, [HWPort1], 3>;
140 defm : HWWriteResPair<WriteIMul32Reg, [HWPort1], 3>;
141 defm : HWWriteResPair<WriteIMul64, [HWPort1,HWPort6], 4, [1,1], 2>;
142 defm : HWWriteResPair<WriteIMul64Imm, [HWPort1], 3>;
143 defm : HWWriteResPair<WriteIMul64Reg, [HWPort1], 3>;
144 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
146 defm : X86WriteRes<WriteBSWAP32, [HWPort15], 1, [1], 1>;
147 defm : X86WriteRes<WriteBSWAP64, [HWPort06, HWPort15], 2, [1,1], 2>;
148 defm : X86WriteRes<WriteCMPXCHG,[HWPort06, HWPort0156], 5, [2,3], 5>;
149 defm : X86WriteRes<WriteCMPXCHGRMW,[HWPort23,HWPort06,HWPort0156,HWPort237,HWPort4], 9, [1,2,1,1,1], 6>;
150 defm : X86WriteRes<WriteXCHG, [HWPort0156], 2, [3], 3>;
152 // Integer shifts and rotates.
153 defm : HWWriteResPair<WriteShift, [HWPort06], 1>;
154 defm : HWWriteResPair<WriteShiftCL, [HWPort06, HWPort0156], 3, [2,1], 3>;
155 defm : HWWriteResPair<WriteRotate, [HWPort06], 1, [1], 1>;
156 defm : HWWriteResPair<WriteRotateCL, [HWPort06, HWPort0156], 3, [2,1], 3>;
159 defm : X86WriteRes<WriteSHDrri, [HWPort1], 3, [1], 1>;
160 defm : X86WriteRes<WriteSHDrrcl,[HWPort1, HWPort06, HWPort0156], 6, [1, 1, 2], 4>;
161 defm : X86WriteRes<WriteSHDmri, [HWPort1, HWPort23, HWPort237, HWPort0156], 10, [1, 1, 1, 1], 4>;
162 defm : X86WriteRes<WriteSHDmrcl,[HWPort1, HWPort23, HWPort237, HWPort06, HWPort0156], 12, [1, 1, 1, 1, 2], 6>;
164 defm : HWWriteResPair<WriteJump, [HWPort06], 1>;
165 defm : HWWriteResPair<WriteCRC32, [HWPort1], 3>;
167 defm : HWWriteResPair<WriteCMOV, [HWPort06,HWPort0156], 2, [1,1], 2>; // Conditional move.
168 defm : X86WriteRes<WriteFCMOV, [HWPort1], 3, [1], 1>; // x87 conditional move.
169 def : WriteRes<WriteSETCC, [HWPort06]>; // Setcc.
170 def : WriteRes<WriteSETCCStore, [HWPort06,HWPort4,HWPort237]> {
175 defm : X86WriteRes<WriteLAHFSAHF, [HWPort06], 1, [1], 1>;
176 defm : X86WriteRes<WriteBitTest, [HWPort06], 1, [1], 1>;
177 defm : X86WriteRes<WriteBitTestImmLd, [HWPort06,HWPort23], 6, [1,1], 2>;
178 defm : X86WriteRes<WriteBitTestRegLd, [], 1, [], 10>;
179 defm : X86WriteRes<WriteBitTestSet, [HWPort06], 1, [1], 1>;
180 defm : X86WriteRes<WriteBitTestSetImmLd, [HWPort06,HWPort23], 6, [1,1], 3>;
181 //defm : X86WriteRes<WriteBitTestSetRegLd, [], 1, [], 11>;
183 // This is for simple LEAs with one or two input operands.
184 // The complex ones can only execute on port 1, and they require two cycles on
185 // the port to read all inputs. We don't model that.
186 def : WriteRes<WriteLEA, [HWPort15]>;
189 defm : HWWriteResPair<WriteBSF, [HWPort1], 3>;
190 defm : HWWriteResPair<WriteBSR, [HWPort1], 3>;
191 defm : HWWriteResPair<WriteLZCNT, [HWPort1], 3>;
192 defm : HWWriteResPair<WriteTZCNT, [HWPort1], 3>;
193 defm : HWWriteResPair<WritePOPCNT, [HWPort1], 3>;
195 // BMI1 BEXTR/BLS, BMI2 BZHI
196 defm : HWWriteResPair<WriteBEXTR, [HWPort06,HWPort15], 2, [1,1], 2>;
197 defm : HWWriteResPair<WriteBLS, [HWPort15], 1>;
198 defm : HWWriteResPair<WriteBZHI, [HWPort15], 1>;
200 // TODO: Why isn't the HWDivider used?
201 defm : X86WriteRes<WriteDiv8, [HWPort0,HWPort1,HWPort5,HWPort6], 22, [], 9>;
202 defm : X86WriteRes<WriteDiv16, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>;
203 defm : X86WriteRes<WriteDiv32, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>;
204 defm : X86WriteRes<WriteDiv64, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>;
205 defm : X86WriteRes<WriteDiv8Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
206 defm : X86WriteRes<WriteDiv16Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
207 defm : X86WriteRes<WriteDiv32Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
208 defm : X86WriteRes<WriteDiv64Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
210 defm : X86WriteRes<WriteIDiv8, [HWPort0,HWPort1,HWPort5,HWPort6], 23, [], 9>;
211 defm : X86WriteRes<WriteIDiv16, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>;
212 defm : X86WriteRes<WriteIDiv32, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>;
213 defm : X86WriteRes<WriteIDiv64, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>;
214 defm : X86WriteRes<WriteIDiv8Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
215 defm : X86WriteRes<WriteIDiv16Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
216 defm : X86WriteRes<WriteIDiv32Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
217 defm : X86WriteRes<WriteIDiv64Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
219 // Scalar and vector floating point.
220 defm : X86WriteRes<WriteFLD0, [HWPort01], 1, [1], 1>;
221 defm : X86WriteRes<WriteFLD1, [HWPort01], 1, [2], 2>;
222 defm : X86WriteRes<WriteFLDC, [HWPort01], 1, [2], 2>;
223 defm : X86WriteRes<WriteFLoad, [HWPort23], 5, [1], 1>;
224 defm : X86WriteRes<WriteFLoadX, [HWPort23], 6, [1], 1>;
225 defm : X86WriteRes<WriteFLoadY, [HWPort23], 7, [1], 1>;
226 defm : X86WriteRes<WriteFMaskedLoad, [HWPort23,HWPort5], 8, [1,2], 3>;
227 defm : X86WriteRes<WriteFMaskedLoadY, [HWPort23,HWPort5], 9, [1,2], 3>;
228 defm : X86WriteRes<WriteFStore, [HWPort237,HWPort4], 1, [1,1], 2>;
229 defm : X86WriteRes<WriteFStoreX, [HWPort237,HWPort4], 1, [1,1], 2>;
230 defm : X86WriteRes<WriteFStoreY, [HWPort237,HWPort4], 1, [1,1], 2>;
231 defm : X86WriteRes<WriteFStoreNT, [HWPort237,HWPort4], 1, [1,1], 2>;
232 defm : X86WriteRes<WriteFStoreNTX, [HWPort237,HWPort4], 1, [1,1], 2>;
233 defm : X86WriteRes<WriteFStoreNTY, [HWPort237,HWPort4], 1, [1,1], 2>;
235 defm : X86WriteRes<WriteFMaskedStore32, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
236 defm : X86WriteRes<WriteFMaskedStore32Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
237 defm : X86WriteRes<WriteFMaskedStore64, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
238 defm : X86WriteRes<WriteFMaskedStore64Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
240 defm : X86WriteRes<WriteFMove, [HWPort5], 1, [1], 1>;
241 defm : X86WriteRes<WriteFMoveX, [HWPort5], 1, [1], 1>;
242 defm : X86WriteRes<WriteFMoveY, [HWPort5], 1, [1], 1>;
243 defm : X86WriteRes<WriteEMMS, [HWPort01,HWPort15,HWPort015,HWPort0156], 31, [8,1,21,1], 31>;
245 defm : HWWriteResPair<WriteFAdd, [HWPort1], 3, [1], 1, 5>;
246 defm : HWWriteResPair<WriteFAddX, [HWPort1], 3, [1], 1, 6>;
247 defm : HWWriteResPair<WriteFAddY, [HWPort1], 3, [1], 1, 7>;
248 defm : HWWriteResPair<WriteFAddZ, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1
249 defm : HWWriteResPair<WriteFAdd64, [HWPort1], 3, [1], 1, 5>;
250 defm : HWWriteResPair<WriteFAdd64X, [HWPort1], 3, [1], 1, 6>;
251 defm : HWWriteResPair<WriteFAdd64Y, [HWPort1], 3, [1], 1, 7>;
252 defm : HWWriteResPair<WriteFAdd64Z, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1
254 defm : HWWriteResPair<WriteFCmp, [HWPort1], 3, [1], 1, 5>;
255 defm : HWWriteResPair<WriteFCmpX, [HWPort1], 3, [1], 1, 6>;
256 defm : HWWriteResPair<WriteFCmpY, [HWPort1], 3, [1], 1, 7>;
257 defm : HWWriteResPair<WriteFCmpZ, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1
258 defm : HWWriteResPair<WriteFCmp64, [HWPort1], 3, [1], 1, 5>;
259 defm : HWWriteResPair<WriteFCmp64X, [HWPort1], 3, [1], 1, 6>;
260 defm : HWWriteResPair<WriteFCmp64Y, [HWPort1], 3, [1], 1, 7>;
261 defm : HWWriteResPair<WriteFCmp64Z, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1
263 defm : HWWriteResPair<WriteFCom, [HWPort1], 3>;
264 defm : HWWriteResPair<WriteFComX, [HWPort1], 3>;
266 defm : HWWriteResPair<WriteFMul, [HWPort01], 5, [1], 1, 5>;
267 defm : HWWriteResPair<WriteFMulX, [HWPort01], 5, [1], 1, 6>;
268 defm : HWWriteResPair<WriteFMulY, [HWPort01], 5, [1], 1, 7>;
269 defm : HWWriteResPair<WriteFMulZ, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1
270 defm : HWWriteResPair<WriteFMul64, [HWPort01], 5, [1], 1, 5>;
271 defm : HWWriteResPair<WriteFMul64X, [HWPort01], 5, [1], 1, 6>;
272 defm : HWWriteResPair<WriteFMul64Y, [HWPort01], 5, [1], 1, 7>;
273 defm : HWWriteResPair<WriteFMul64Z, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1
275 defm : HWWriteResPair<WriteFDiv, [HWPort0,HWFPDivider], 13, [1,7], 1, 5>;
276 defm : HWWriteResPair<WriteFDivX, [HWPort0,HWFPDivider], 13, [1,7], 1, 6>;
277 defm : HWWriteResPair<WriteFDivY, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>;
278 defm : HWWriteResPair<WriteFDivZ, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1
279 defm : HWWriteResPair<WriteFDiv64, [HWPort0,HWFPDivider], 20, [1,14], 1, 5>;
280 defm : HWWriteResPair<WriteFDiv64X, [HWPort0,HWFPDivider], 20, [1,14], 1, 6>;
281 defm : HWWriteResPair<WriteFDiv64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>;
282 defm : HWWriteResPair<WriteFDiv64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1
284 defm : HWWriteResPair<WriteFRcp, [HWPort0], 5, [1], 1, 5>;
285 defm : HWWriteResPair<WriteFRcpX, [HWPort0], 5, [1], 1, 6>;
286 defm : HWWriteResPair<WriteFRcpY, [HWPort0,HWPort015], 11, [2,1], 3, 7>;
287 defm : HWWriteResPair<WriteFRcpZ, [HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1
289 defm : HWWriteResPair<WriteFRsqrt, [HWPort0], 5, [1], 1, 5>;
290 defm : HWWriteResPair<WriteFRsqrtX,[HWPort0], 5, [1], 1, 6>;
291 defm : HWWriteResPair<WriteFRsqrtY,[HWPort0,HWPort015], 11, [2,1], 3, 7>;
292 defm : HWWriteResPair<WriteFRsqrtZ,[HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1
294 defm : HWWriteResPair<WriteFSqrt, [HWPort0,HWFPDivider], 11, [1,7], 1, 5>;
295 defm : HWWriteResPair<WriteFSqrtX, [HWPort0,HWFPDivider], 11, [1,7], 1, 6>;
296 defm : HWWriteResPair<WriteFSqrtY, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>;
297 defm : HWWriteResPair<WriteFSqrtZ, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1
298 defm : HWWriteResPair<WriteFSqrt64, [HWPort0,HWFPDivider], 16, [1,14], 1, 5>;
299 defm : HWWriteResPair<WriteFSqrt64X, [HWPort0,HWFPDivider], 16, [1,14], 1, 6>;
300 defm : HWWriteResPair<WriteFSqrt64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>;
301 defm : HWWriteResPair<WriteFSqrt64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1
302 defm : HWWriteResPair<WriteFSqrt80, [HWPort0,HWFPDivider], 23, [1,17]>;
304 defm : HWWriteResPair<WriteFMA, [HWPort01], 5, [1], 1, 5>;
305 defm : HWWriteResPair<WriteFMAX, [HWPort01], 5, [1], 1, 6>;
306 defm : HWWriteResPair<WriteFMAY, [HWPort01], 5, [1], 1, 7>;
307 defm : HWWriteResPair<WriteFMAZ, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1
308 defm : HWWriteResPair<WriteDPPD, [HWPort0,HWPort1,HWPort5], 9, [1,1,1], 3, 6>;
309 defm : HWWriteResPair<WriteDPPS, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 6>;
310 defm : HWWriteResPair<WriteDPPSY, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 7>;
311 defm : HWWriteResPair<WriteDPPSZ, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 7>; // Unsupported = 1
312 defm : HWWriteResPair<WriteFSign, [HWPort0], 1>;
313 defm : X86WriteRes<WriteFRnd, [HWPort23], 6, [1], 1>;
314 defm : X86WriteRes<WriteFRndY, [HWPort23], 6, [1], 1>;
315 defm : X86WriteRes<WriteFRndZ, [HWPort23], 6, [1], 1>; // Unsupported = 1
316 defm : X86WriteRes<WriteFRndLd, [HWPort1,HWPort23], 12, [2,1], 3>;
317 defm : X86WriteRes<WriteFRndYLd, [HWPort1,HWPort23], 13, [2,1], 3>;
318 defm : X86WriteRes<WriteFRndZLd, [HWPort1,HWPort23], 13, [2,1], 3>; // Unsupported = 1
319 defm : HWWriteResPair<WriteFLogic, [HWPort5], 1, [1], 1, 6>;
320 defm : HWWriteResPair<WriteFLogicY, [HWPort5], 1, [1], 1, 7>;
321 defm : HWWriteResPair<WriteFLogicZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1
322 defm : HWWriteResPair<WriteFTest, [HWPort0], 1, [1], 1, 6>;
323 defm : HWWriteResPair<WriteFTestY, [HWPort0], 1, [1], 1, 7>;
324 defm : HWWriteResPair<WriteFTestZ, [HWPort0], 1, [1], 1, 7>; // Unsupported = 1
325 defm : HWWriteResPair<WriteFShuffle, [HWPort5], 1, [1], 1, 6>;
326 defm : HWWriteResPair<WriteFShuffleY, [HWPort5], 1, [1], 1, 7>;
327 defm : HWWriteResPair<WriteFShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1
328 defm : HWWriteResPair<WriteFVarShuffle, [HWPort5], 1, [1], 1, 6>;
329 defm : HWWriteResPair<WriteFVarShuffleY, [HWPort5], 1, [1], 1, 7>;
330 defm : HWWriteResPair<WriteFVarShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1
331 defm : HWWriteResPair<WriteFBlend, [HWPort015], 1, [1], 1, 6>;
332 defm : HWWriteResPair<WriteFBlendY, [HWPort015], 1, [1], 1, 7>;
333 defm : HWWriteResPair<WriteFBlendZ, [HWPort015], 1, [1], 1, 7>; // Unsupported = 1
334 defm : HWWriteResPair<WriteFShuffle256, [HWPort5], 3, [1], 1, 7>;
335 defm : HWWriteResPair<WriteFVarShuffle256, [HWPort5], 3, [1], 1, 7>;
336 defm : HWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2], 2, 6>;
337 defm : HWWriteResPair<WriteFVarBlendY, [HWPort5], 2, [2], 2, 7>;
338 defm : HWWriteResPair<WriteFVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1
340 // Conversion between integer and float.
341 defm : HWWriteResPair<WriteCvtSD2I, [HWPort1], 3>;
342 defm : HWWriteResPair<WriteCvtPD2I, [HWPort1], 3>;
343 defm : HWWriteResPair<WriteCvtPD2IY, [HWPort1], 3>;
344 defm : HWWriteResPair<WriteCvtPD2IZ, [HWPort1], 3>; // Unsupported = 1
345 defm : HWWriteResPair<WriteCvtSS2I, [HWPort1], 3>;
346 defm : HWWriteResPair<WriteCvtPS2I, [HWPort1], 3>;
347 defm : HWWriteResPair<WriteCvtPS2IY, [HWPort1], 3>;
348 defm : HWWriteResPair<WriteCvtPS2IZ, [HWPort1], 3>; // Unsupported = 1
350 defm : HWWriteResPair<WriteCvtI2SD, [HWPort1], 4>;
351 defm : HWWriteResPair<WriteCvtI2PD, [HWPort1], 4>;
352 defm : HWWriteResPair<WriteCvtI2PDY, [HWPort1], 4>;
353 defm : HWWriteResPair<WriteCvtI2PDZ, [HWPort1], 4>; // Unsupported = 1
354 defm : HWWriteResPair<WriteCvtI2SS, [HWPort1], 4>;
355 defm : HWWriteResPair<WriteCvtI2PS, [HWPort1], 4>;
356 defm : HWWriteResPair<WriteCvtI2PSY, [HWPort1], 4>;
357 defm : HWWriteResPair<WriteCvtI2PSZ, [HWPort1], 4>; // Unsupported = 1
359 defm : HWWriteResPair<WriteCvtSS2SD, [HWPort1], 3>;
360 defm : HWWriteResPair<WriteCvtPS2PD, [HWPort1], 3>;
361 defm : HWWriteResPair<WriteCvtPS2PDY, [HWPort1], 3>;
362 defm : HWWriteResPair<WriteCvtPS2PDZ, [HWPort1], 3>; // Unsupported = 1
363 defm : HWWriteResPair<WriteCvtSD2SS, [HWPort1], 3>;
364 defm : HWWriteResPair<WriteCvtPD2PS, [HWPort1], 3>;
365 defm : HWWriteResPair<WriteCvtPD2PSY, [HWPort1], 3>;
366 defm : HWWriteResPair<WriteCvtPD2PSZ, [HWPort1], 3>; // Unsupported = 1
368 defm : X86WriteRes<WriteCvtPH2PS, [HWPort0,HWPort5], 2, [1,1], 2>;
369 defm : X86WriteRes<WriteCvtPH2PSY, [HWPort0,HWPort5], 2, [1,1], 2>;
370 defm : X86WriteRes<WriteCvtPH2PSZ, [HWPort0,HWPort5], 2, [1,1], 2>; // Unsupported = 1
371 defm : X86WriteRes<WriteCvtPH2PSLd, [HWPort0,HWPort23], 6, [1,1], 2>;
372 defm : X86WriteRes<WriteCvtPH2PSYLd, [HWPort0,HWPort23], 7, [1,1], 2>;
373 defm : X86WriteRes<WriteCvtPH2PSZLd, [HWPort0,HWPort23], 7, [1,1], 2>; // Unsupported = 1
375 defm : X86WriteRes<WriteCvtPS2PH, [HWPort1,HWPort5], 4, [1,1], 2>;
376 defm : X86WriteRes<WriteCvtPS2PHY, [HWPort1,HWPort5], 6, [1,1], 2>;
377 defm : X86WriteRes<WriteCvtPS2PHZ, [HWPort1,HWPort5], 6, [1,1], 2>; // Unsupported = 1
378 defm : X86WriteRes<WriteCvtPS2PHSt, [HWPort1,HWPort4,HWPort5,HWPort237], 5, [1,1,1,1], 4>;
379 defm : X86WriteRes<WriteCvtPS2PHYSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>;
380 defm : X86WriteRes<WriteCvtPS2PHZSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>; // Unsupported = 1
382 // Vector integer operations.
383 defm : X86WriteRes<WriteVecLoad, [HWPort23], 5, [1], 1>;
384 defm : X86WriteRes<WriteVecLoadX, [HWPort23], 6, [1], 1>;
385 defm : X86WriteRes<WriteVecLoadY, [HWPort23], 7, [1], 1>;
386 defm : X86WriteRes<WriteVecLoadNT, [HWPort23], 6, [1], 1>;
387 defm : X86WriteRes<WriteVecLoadNTY, [HWPort23], 7, [1], 1>;
388 defm : X86WriteRes<WriteVecMaskedLoad, [HWPort23,HWPort5], 8, [1,2], 3>;
389 defm : X86WriteRes<WriteVecMaskedLoadY, [HWPort23,HWPort5], 9, [1,2], 3>;
390 defm : X86WriteRes<WriteVecStore, [HWPort237,HWPort4], 1, [1,1], 2>;
391 defm : X86WriteRes<WriteVecStoreX, [HWPort237,HWPort4], 1, [1,1], 2>;
392 defm : X86WriteRes<WriteVecStoreY, [HWPort237,HWPort4], 1, [1,1], 2>;
393 defm : X86WriteRes<WriteVecStoreNT, [HWPort237,HWPort4], 1, [1,1], 2>;
394 defm : X86WriteRes<WriteVecStoreNTY, [HWPort237,HWPort4], 1, [1,1], 2>;
395 defm : X86WriteRes<WriteVecMaskedStore32, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
396 defm : X86WriteRes<WriteVecMaskedStore32Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
397 defm : X86WriteRes<WriteVecMaskedStore64, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
398 defm : X86WriteRes<WriteVecMaskedStore64Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
399 defm : X86WriteRes<WriteVecMove, [HWPort015], 1, [1], 1>;
400 defm : X86WriteRes<WriteVecMoveX, [HWPort015], 1, [1], 1>;
401 defm : X86WriteRes<WriteVecMoveY, [HWPort015], 1, [1], 1>;
402 defm : X86WriteRes<WriteVecMoveToGpr, [HWPort0], 1, [1], 1>;
403 defm : X86WriteRes<WriteVecMoveFromGpr, [HWPort5], 1, [1], 1>;
405 defm : HWWriteResPair<WriteVecLogic, [HWPort015], 1, [1], 1, 5>;
406 defm : HWWriteResPair<WriteVecLogicX,[HWPort015], 1, [1], 1, 6>;
407 defm : HWWriteResPair<WriteVecLogicY,[HWPort015], 1, [1], 1, 7>;
408 defm : HWWriteResPair<WriteVecLogicZ,[HWPort015], 1, [1], 1, 7>; // Unsupported = 1
409 defm : HWWriteResPair<WriteVecTest, [HWPort0,HWPort5], 2, [1,1], 2, 6>;
410 defm : HWWriteResPair<WriteVecTestY, [HWPort0,HWPort5], 4, [1,1], 2, 7>;
411 defm : HWWriteResPair<WriteVecTestZ, [HWPort0,HWPort5], 4, [1,1], 2, 7>; // Unsupported = 1
412 defm : HWWriteResPair<WriteVecALU, [HWPort15], 1, [1], 1, 5>;
413 defm : HWWriteResPair<WriteVecALUX, [HWPort15], 1, [1], 1, 6>;
414 defm : HWWriteResPair<WriteVecALUY, [HWPort15], 1, [1], 1, 7>;
415 defm : HWWriteResPair<WriteVecALUZ, [HWPort15], 1, [1], 1, 7>; // Unsupported = 1
416 defm : HWWriteResPair<WriteVecIMul, [HWPort0], 5, [1], 1, 5>;
417 defm : HWWriteResPair<WriteVecIMulX, [HWPort0], 5, [1], 1, 6>;
418 defm : HWWriteResPair<WriteVecIMulY, [HWPort0], 5, [1], 1, 7>;
419 defm : HWWriteResPair<WriteVecIMulZ, [HWPort0], 5, [1], 1, 7>; // Unsupported = 1
420 defm : HWWriteResPair<WritePMULLD, [HWPort0], 10, [2], 2, 6>;
421 defm : HWWriteResPair<WritePMULLDY, [HWPort0], 10, [2], 2, 7>;
422 defm : HWWriteResPair<WritePMULLDZ, [HWPort0], 10, [2], 2, 7>; // Unsupported = 1
423 defm : HWWriteResPair<WriteShuffle, [HWPort5], 1, [1], 1, 5>;
424 defm : HWWriteResPair<WriteShuffleX, [HWPort5], 1, [1], 1, 6>;
425 defm : HWWriteResPair<WriteShuffleY, [HWPort5], 1, [1], 1, 7>;
426 defm : HWWriteResPair<WriteShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1
427 defm : HWWriteResPair<WriteVarShuffle, [HWPort5], 1, [1], 1, 5>;
428 defm : HWWriteResPair<WriteVarShuffleX,[HWPort5], 1, [1], 1, 6>;
429 defm : HWWriteResPair<WriteVarShuffleY,[HWPort5], 1, [1], 1, 7>;
430 defm : HWWriteResPair<WriteVarShuffleZ,[HWPort5], 1, [1], 1, 7>; // Unsupported = 1
431 defm : HWWriteResPair<WriteBlend, [HWPort5], 1, [1], 1, 6>;
432 defm : HWWriteResPair<WriteBlendY, [HWPort5], 1, [1], 1, 7>;
433 defm : HWWriteResPair<WriteBlendZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1
434 defm : HWWriteResPair<WriteShuffle256, [HWPort5], 3, [1], 1, 7>;
435 defm : HWWriteResPair<WriteVarShuffle256, [HWPort5], 3, [1], 1, 7>;
436 defm : HWWriteResPair<WriteVarBlend, [HWPort5], 2, [2], 2, 6>;
437 defm : HWWriteResPair<WriteVarBlendY, [HWPort5], 2, [2], 2, 7>;
438 defm : HWWriteResPair<WriteVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1
439 defm : HWWriteResPair<WriteMPSAD, [HWPort0, HWPort5], 7, [1, 2], 3, 6>;
440 defm : HWWriteResPair<WriteMPSADY, [HWPort0, HWPort5], 7, [1, 2], 3, 7>;
441 defm : HWWriteResPair<WriteMPSADZ, [HWPort0, HWPort5], 7, [1, 2], 3, 7>; // Unsupported = 1
442 defm : HWWriteResPair<WritePSADBW, [HWPort0], 5, [1], 1, 5>;
443 defm : HWWriteResPair<WritePSADBWX, [HWPort0], 5, [1], 1, 6>;
444 defm : HWWriteResPair<WritePSADBWY, [HWPort0], 5, [1], 1, 7>;
445 defm : HWWriteResPair<WritePSADBWZ, [HWPort0], 5, [1], 1, 7>; // Unsupported = 1
446 defm : HWWriteResPair<WritePHMINPOS, [HWPort0], 5, [1], 1, 6>;
448 // Vector integer shifts.
449 defm : HWWriteResPair<WriteVecShift, [HWPort0], 1, [1], 1, 5>;
450 defm : HWWriteResPair<WriteVecShiftX, [HWPort0,HWPort5], 2, [1,1], 2, 6>;
451 defm : X86WriteRes<WriteVecShiftY, [HWPort0,HWPort5], 4, [1,1], 2>;
452 defm : X86WriteRes<WriteVecShiftZ, [HWPort0,HWPort5], 4, [1,1], 2>; // Unsupported = 1
453 defm : X86WriteRes<WriteVecShiftYLd, [HWPort0,HWPort23], 8, [1,1], 2>;
454 defm : X86WriteRes<WriteVecShiftZLd, [HWPort0,HWPort23], 8, [1,1], 2>; // Unsupported = 1
456 defm : HWWriteResPair<WriteVecShiftImm, [HWPort0], 1, [1], 1, 5>;
457 defm : HWWriteResPair<WriteVecShiftImmX, [HWPort0], 1, [1], 1, 6>;
458 defm : HWWriteResPair<WriteVecShiftImmY, [HWPort0], 1, [1], 1, 7>;
459 defm : HWWriteResPair<WriteVecShiftImmZ, [HWPort0], 1, [1], 1, 7>; // Unsupported = 1
460 defm : HWWriteResPair<WriteVarVecShift, [HWPort0, HWPort5], 3, [2,1], 3, 6>;
461 defm : HWWriteResPair<WriteVarVecShiftY, [HWPort0, HWPort5], 3, [2,1], 3, 7>;
462 defm : HWWriteResPair<WriteVarVecShiftZ, [HWPort0, HWPort5], 3, [2,1], 3, 7>; // Unsupported = 1
464 // Vector insert/extract operations.
465 def : WriteRes<WriteVecInsert, [HWPort5]> {
468 let ResourceCycles = [2];
470 def : WriteRes<WriteVecInsertLd, [HWPort5,HWPort23]> {
474 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
476 def : WriteRes<WriteVecExtract, [HWPort0,HWPort5]> {
480 def : WriteRes<WriteVecExtractSt, [HWPort4,HWPort5,HWPort237]> {
485 // String instructions.
487 // Packed Compare Implicit Length Strings, Return Mask
488 def : WriteRes<WritePCmpIStrM, [HWPort0]> {
491 let ResourceCycles = [3];
493 def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> {
496 let ResourceCycles = [3,1];
499 // Packed Compare Explicit Length Strings, Return Mask
500 def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort5, HWPort015, HWPort0156]> {
503 let ResourceCycles = [4,3,1,1];
505 def : WriteRes<WritePCmpEStrMLd, [HWPort0, HWPort5, HWPort23, HWPort015, HWPort0156]> {
507 let NumMicroOps = 10;
508 let ResourceCycles = [4,3,1,1,1];
511 // Packed Compare Implicit Length Strings, Return Index
512 def : WriteRes<WritePCmpIStrI, [HWPort0]> {
515 let ResourceCycles = [3];
517 def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> {
520 let ResourceCycles = [3,1];
523 // Packed Compare Explicit Length Strings, Return Index
524 def : WriteRes<WritePCmpEStrI, [HWPort0, HWPort5, HWPort0156]> {
527 let ResourceCycles = [4,3,1];
529 def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort5, HWPort23, HWPort0156]> {
532 let ResourceCycles = [4,3,1,1];
535 // MOVMSK Instructions.
536 def : WriteRes<WriteFMOVMSK, [HWPort0]> { let Latency = 3; }
537 def : WriteRes<WriteVecMOVMSK, [HWPort0]> { let Latency = 3; }
538 def : WriteRes<WriteVecMOVMSKY, [HWPort0]> { let Latency = 3; }
539 def : WriteRes<WriteMMXMOVMSK, [HWPort0]> { let Latency = 1; }
542 def : WriteRes<WriteAESDecEnc, [HWPort5]> {
545 let ResourceCycles = [1];
547 def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {
550 let ResourceCycles = [1,1];
553 def : WriteRes<WriteAESIMC, [HWPort5]> {
556 let ResourceCycles = [2];
558 def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> {
561 let ResourceCycles = [2,1];
564 def : WriteRes<WriteAESKeyGen, [HWPort0,HWPort5,HWPort015]> {
566 let NumMicroOps = 11;
567 let ResourceCycles = [2,7,2];
569 def : WriteRes<WriteAESKeyGenLd, [HWPort0,HWPort5,HWPort23,HWPort015]> {
571 let NumMicroOps = 11;
572 let ResourceCycles = [2,7,1,1];
575 // Carry-less multiplication instructions.
576 def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> {
579 let ResourceCycles = [2,1];
581 def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> {
584 let ResourceCycles = [2,1,1];
588 def : WriteRes<WriteLDMXCSR, [HWPort0,HWPort23,HWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
589 def : WriteRes<WriteSTMXCSR, [HWPort4,HWPort5,HWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
591 def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; }
592 def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }
593 def : WriteRes<WriteFence, [HWPort23, HWPort4]>;
594 def : WriteRes<WriteNop, []>;
596 //================ Exceptions ================//
598 //-- Specific Scheduling Models --//
601 def HWWriteP0 : SchedWriteRes<[HWPort0]>;
603 def HWWriteP01 : SchedWriteRes<[HWPort01]>;
605 def HWWrite2P01 : SchedWriteRes<[HWPort01]> {
608 def HWWrite3P01 : SchedWriteRes<[HWPort01]> {
612 def HWWriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
616 def HWWrite2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
618 let ResourceCycles = [2, 1];
622 def HWWriteP1 : SchedWriteRes<[HWPort1]>;
625 def HWWrite2P1 : SchedWriteRes<[HWPort1]> {
627 let ResourceCycles = [2];
632 // - mm: 64 bit mmx register.
633 // - x = 128 bit xmm register.
634 // - (x)mm = mmx or xmm register.
635 // - y = 256 bit ymm register.
636 // - v = any vector register.
639 //=== Integer Instructions ===//
640 //-- Move instructions --//
643 def HWWriteXLAT : SchedWriteRes<[]> {
647 def : InstRW<[HWWriteXLAT], (instrs XLAT)>;
650 def HWWritePushA : SchedWriteRes<[]> {
651 let NumMicroOps = 19;
653 def : InstRW<[HWWritePushA], (instregex "PUSHA(16|32)")>;
656 def HWWritePopA : SchedWriteRes<[]> {
657 let NumMicroOps = 18;
659 def : InstRW<[HWWritePopA], (instregex "POPA(16|32)")>;
661 //-- Arithmetic instructions --//
665 def HWWriteBTRSCmr : SchedWriteRes<[]> {
666 let NumMicroOps = 11;
668 def : SchedAlias<WriteBitTestSetRegRMW, HWWriteBTRSCmr>;
670 //-- Control transfer instructions --//
674 def HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {
676 let ResourceCycles = [1, 2, 1];
678 def : InstRW<[HWWriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>;
682 def HWWriteBOUND : SchedWriteRes<[]> {
683 let NumMicroOps = 15;
685 def : InstRW<[HWWriteBOUND], (instregex "BOUNDS(16|32)rm")>;
688 def HWWriteINTO : SchedWriteRes<[]> {
691 def : InstRW<[HWWriteINTO], (instrs INTO)>;
693 //-- String instructions --//
696 def : InstRW<[HWWrite2P0156_P23], (instregex "LODS(B|W)")>;
699 def : InstRW<[HWWriteP0156_P23], (instregex "LODS(L|Q)")>;
702 def HWWriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> {
705 let ResourceCycles = [2, 1, 2];
707 def : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>;
710 def HWWriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> {
713 let ResourceCycles = [2, 3];
715 def : InstRW<[HWWriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
720 def HWWriteRDPMC : SchedWriteRes<[]> {
721 let NumMicroOps = 34;
723 def : InstRW<[HWWriteRDPMC], (instrs RDPMC)>;
726 def HWWriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> {
727 let NumMicroOps = 17;
728 let ResourceCycles = [1, 16];
730 def : InstRW<[HWWriteRDRAND], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;
732 //=== Floating Point x87 Instructions ===//
733 //-- Move instructions --//
737 def : InstRW<[HWWriteP01], (instrs LD_Frr)>;
741 def HWWriteFBLD : SchedWriteRes<[]> {
743 let NumMicroOps = 43;
745 def : InstRW<[HWWriteFBLD], (instrs FBLDm)>;
749 def : InstRW<[HWWriteP01], (instregex "ST_(F|FP)rr")>;
752 def : InstRW<[HWWriteP01], (instregex "FFREE")>;
755 def HWWriteFNSAVE : SchedWriteRes<[]> {
756 let NumMicroOps = 147;
758 def : InstRW<[HWWriteFNSAVE], (instrs FSAVEm)>;
761 def HWWriteFRSTOR : SchedWriteRes<[]> {
762 let NumMicroOps = 90;
764 def : InstRW<[HWWriteFRSTOR], (instrs FRSTORm)>;
766 //-- Arithmetic instructions --//
770 def : InstRW<[HWWrite2P01], (instrs FCOMPP, UCOM_FPPr)>;
772 // FCOMI(P) FUCOMI(P).
774 def : InstRW<[HWWrite3P01], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
777 def : InstRW<[HWWriteP1], (instregex "TST_F")>;
780 def : InstRW<[HWWrite2P1], (instrs FXAM)>;
783 def HWWriteFPREM : SchedWriteRes<[]> {
785 let NumMicroOps = 28;
787 def : InstRW<[HWWriteFPREM], (instrs FPREM)>;
790 def HWWriteFPREM1 : SchedWriteRes<[]> {
792 let NumMicroOps = 41;
794 def : InstRW<[HWWriteFPREM1], (instrs FPREM1)>;
797 def HWWriteFRNDINT : SchedWriteRes<[]> {
799 let NumMicroOps = 17;
801 def : InstRW<[HWWriteFRNDINT], (instrs FRNDINT)>;
803 //-- Math instructions --//
806 def HWWriteFSCALE : SchedWriteRes<[]> {
807 let Latency = 75; // 49-125
808 let NumMicroOps = 50; // 25-75
810 def : InstRW<[HWWriteFSCALE], (instrs FSCALE)>;
813 def HWWriteFXTRACT : SchedWriteRes<[]> {
815 let NumMicroOps = 17;
817 def : InstRW<[HWWriteFXTRACT], (instrs FXTRACT)>;
819 ////////////////////////////////////////////////////////////////////////////////
820 // Horizontal add/sub instructions.
821 ////////////////////////////////////////////////////////////////////////////////
823 defm : HWWriteResPair<WriteFHAdd, [HWPort1, HWPort5], 5, [1,2], 3, 6>;
824 defm : HWWriteResPair<WriteFHAddY, [HWPort1, HWPort5], 5, [1,2], 3, 7>;
825 defm : HWWriteResPair<WritePHAdd, [HWPort5, HWPort15], 3, [2,1], 3, 5>;
826 defm : HWWriteResPair<WritePHAddX, [HWPort5, HWPort15], 3, [2,1], 3, 6>;
827 defm : HWWriteResPair<WritePHAddY, [HWPort5, HWPort15], 3, [2,1], 3, 7>;
829 //=== Floating Point XMM and YMM Instructions ===//
833 def HWWriteResGroup0 : SchedWriteRes<[HWPort23]> {
836 let ResourceCycles = [1];
838 def: InstRW<[HWWriteResGroup0], (instrs VBROADCASTSSrm)>;
839 def: InstRW<[HWWriteResGroup0], (instregex "(V?)MOVSHDUPrm",
841 "VPBROADCAST(D|Q)rm")>;
843 def HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> {
846 let ResourceCycles = [1];
848 def: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128,
855 def: InstRW<[HWWriteResGroup0_1], (instregex "LD_F(32|64|80)m",
856 "VPBROADCAST(D|Q)Yrm")>;
858 def HWWriteResGroup0_2 : SchedWriteRes<[HWPort23]> {
861 let ResourceCycles = [1];
863 def: InstRW<[HWWriteResGroup0_2], (instregex "MOVSX(16|32|64)rm(8|16|32)",
864 "MOVZX(16|32|64)rm(8|16)",
867 def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> {
870 let ResourceCycles = [1,1];
872 def: InstRW<[HWWriteResGroup1], (instrs FBSTPm, VMPTRSTm)>;
873 def: InstRW<[HWWriteResGroup1], (instregex "ST_FP(32|64|80)m")>;
875 def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> {
878 let ResourceCycles = [1];
880 def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQ(Y?)rr",
883 def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> {
886 let ResourceCycles = [1];
888 def: InstRW<[HWWriteResGroup3], (instregex "COM(P?)_FST0r",
891 def HWWriteResGroup4 : SchedWriteRes<[HWPort5]> {
894 let ResourceCycles = [1];
896 def: InstRW<[HWWriteResGroup4], (instrs MMX_MOVQ2DQrr)>;
898 def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> {
901 let ResourceCycles = [1];
903 def: InstRW<[HWWriteResGroup5], (instregex "JMP(16|32|64)r")>;
905 def HWWriteResGroup6 : SchedWriteRes<[HWPort01]> {
908 let ResourceCycles = [1];
910 def: InstRW<[HWWriteResGroup6], (instrs FINCSTP, FNOP)>;
912 def HWWriteResGroup7 : SchedWriteRes<[HWPort06]> {
915 let ResourceCycles = [1];
917 def: InstRW<[HWWriteResGroup7], (instrs CDQ, CQO)>;
919 def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {
922 let ResourceCycles = [1];
924 def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr")>;
926 def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> {
929 let ResourceCycles = [1];
931 def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDD(Y?)rri")>;
933 def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
936 let ResourceCycles = [1];
938 def: InstRW<[HWWriteResGroup10], (instrs CBW, CWDE, CDQE,
946 def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> {
949 let ResourceCycles = [1,1];
951 def: InstRW<[HWWriteResGroup11], (instregex "(V?)CVTPS2PDrm")>;
953 def HWWriteResGroup11_1 : SchedWriteRes<[HWPort0,HWPort23]> {
956 let ResourceCycles = [1,1];
958 def: InstRW<[HWWriteResGroup11_1], (instrs VPSLLVQrm, VPSRLVQrm)>;
959 def: InstRW<[HWWriteResGroup11_1], (instregex "(V?)CVTSS2SDrm")>;
961 def HWWriteResGroup11_2 : SchedWriteRes<[HWPort0,HWPort23]> {
964 let ResourceCycles = [1,1];
966 def: InstRW<[HWWriteResGroup11_2], (instrs VPSLLVQYrm, VPSRLVQYrm)>;
968 def HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> {
971 let ResourceCycles = [1,1];
973 def: InstRW<[HWWriteResGroup12], (instrs MMX_CVTPI2PSirm)>;
974 def: InstRW<[HWWriteResGroup12], (instregex "P(DEP|EXT)(32|64)rm")>;
976 def HWWriteResGroup13 : SchedWriteRes<[HWPort5,HWPort23]> {
979 let ResourceCycles = [1,1];
981 def: InstRW<[HWWriteResGroup13], (instregex "(V?)PMOV(SX|ZX)BDrm",
982 "(V?)PMOV(SX|ZX)BQrm",
983 "(V?)PMOV(SX|ZX)BWrm",
984 "(V?)PMOV(SX|ZX)DQrm",
985 "(V?)PMOV(SX|ZX)WDrm",
986 "(V?)PMOV(SX|ZX)WQrm")>;
988 def HWWriteResGroup13_1 : SchedWriteRes<[HWPort5,HWPort23]> {
991 let ResourceCycles = [1,1];
993 def: InstRW<[HWWriteResGroup13_1], (instrs VPMOVSXBDYrm,
997 def HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> {
1000 let ResourceCycles = [1,1];
1002 def: InstRW<[HWWriteResGroup14], (instrs FARJMP64m)>;
1003 def: InstRW<[HWWriteResGroup14], (instregex "JMP(16|32|64)m")>;
1005 def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> {
1007 let NumMicroOps = 2;
1008 let ResourceCycles = [1,1];
1010 def: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm",
1011 "MOVBE(16|32|64)rm")>;
1013 def HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort015]> {
1015 let NumMicroOps = 2;
1016 let ResourceCycles = [1,1];
1018 def: InstRW<[HWWriteResGroup17], (instrs VINSERTF128rm,
1022 def HWWriteResGroup17_2 : SchedWriteRes<[HWPort23,HWPort015]> {
1024 let NumMicroOps = 2;
1025 let ResourceCycles = [1,1];
1027 def: InstRW<[HWWriteResGroup17_2], (instrs VPBLENDDYrmi)>;
1029 def HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> {
1031 let NumMicroOps = 2;
1032 let ResourceCycles = [1,1];
1034 def: InstRW<[HWWriteResGroup18], (instrs POP16r, POP32r, POP64r)>;
1035 def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>;
1037 def HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> {
1039 let NumMicroOps = 2;
1040 let ResourceCycles = [1,1];
1042 def: InstRW<[HWWriteResGroup19], (instrs SFENCE)>;
1044 def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> {
1046 let NumMicroOps = 3;
1047 let ResourceCycles = [1,1,1];
1049 def: InstRW<[HWWriteResGroup21], (instrs FNSTCW16m)>;
1051 def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> {
1053 let NumMicroOps = 3;
1054 let ResourceCycles = [1,1,1];
1056 def: InstRW<[HWWriteResGroup23], (instregex "MOVBE(32|64)mr")>;
1058 def HWWriteResGroup23_16 : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
1060 let NumMicroOps = 3;
1061 let ResourceCycles = [1,1,1];
1063 def: InstRW<[HWWriteResGroup23_16], (instrs MOVBE16mr)>;
1065 def HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {
1067 let NumMicroOps = 3;
1068 let ResourceCycles = [1,1,1];
1070 def: InstRW<[HWWriteResGroup24], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
1071 STOSB, STOSL, STOSQ, STOSW)>;
1072 def: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)rmr")>;
1074 def HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
1076 let NumMicroOps = 4;
1077 let ResourceCycles = [1,1,1,1];
1079 def: InstRW<[HWWriteResGroup25], (instregex "SAR(8|16|32|64)m(1|i)",
1080 "SHL(8|16|32|64)m(1|i)",
1081 "SHR(8|16|32|64)m(1|i)")>;
1083 def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
1085 let NumMicroOps = 4;
1086 let ResourceCycles = [1,1,1,1];
1088 def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm",
1089 "PUSH(16|32|64)rmm")>;
1091 def HWWriteResGroup28 : SchedWriteRes<[HWPort01]> {
1093 let NumMicroOps = 2;
1094 let ResourceCycles = [2];
1096 def: InstRW<[HWWriteResGroup28], (instrs FDECSTP)>;
1098 def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> {
1100 let NumMicroOps = 2;
1101 let ResourceCycles = [2];
1103 def: InstRW<[HWWriteResGroup30], (instrs LFENCE,
1108 def HWWriteResGroup31 : SchedWriteRes<[HWPort0,HWPort5]> {
1110 let NumMicroOps = 2;
1111 let ResourceCycles = [1,1];
1113 def: InstRW<[HWWriteResGroup31], (instregex "(V?)CVTPS2PDrr",
1116 def HWWriteResGroup32 : SchedWriteRes<[HWPort6,HWPort0156]> {
1118 let NumMicroOps = 2;
1119 let ResourceCycles = [1,1];
1121 def: InstRW<[HWWriteResGroup32], (instregex "CLFLUSH")>;
1123 def HWWriteResGroup33 : SchedWriteRes<[HWPort01,HWPort015]> {
1125 let NumMicroOps = 2;
1126 let ResourceCycles = [1,1];
1128 def: InstRW<[HWWriteResGroup33], (instrs MMX_MOVDQ2Qrr)>;
1130 def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
1132 let NumMicroOps = 2;
1133 let ResourceCycles = [1,1];
1135 def: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>;
1137 def HWWriteResGroup36_2 : SchedWriteRes<[HWPort5,HWPort23]> {
1139 let NumMicroOps = 3;
1140 let ResourceCycles = [2,1];
1142 def: InstRW<[HWWriteResGroup36_2], (instrs MMX_PACKSSDWirm,
1146 def HWWriteResGroup37 : SchedWriteRes<[HWPort23,HWPort0156]> {
1148 let NumMicroOps = 3;
1149 let ResourceCycles = [1,2];
1151 def: InstRW<[HWWriteResGroup37], (instrs LEAVE, LEAVE64,
1152 SCASB, SCASL, SCASQ, SCASW)>;
1154 def HWWriteResGroup39 : SchedWriteRes<[HWPort0,HWPort01,HWPort23]> {
1156 let NumMicroOps = 3;
1157 let ResourceCycles = [1,1,1];
1159 def: InstRW<[HWWriteResGroup39], (instrs FLDCW16m)>;
1161 def HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
1163 let NumMicroOps = 3;
1164 let ResourceCycles = [1,1,1];
1166 def: InstRW<[HWWriteResGroup41], (instrs LRETQ, RETL, RETQ)>;
1168 def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> {
1170 let NumMicroOps = 4;
1171 let ResourceCycles = [1,1,1,1];
1173 def: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>;
1175 def HWWriteResGroup45 : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> {
1177 let NumMicroOps = 4;
1178 let ResourceCycles = [1,1,1,1];
1180 def: InstRW<[HWWriteResGroup45], (instrs CALL64pcrel32)>;
1182 def HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
1184 let NumMicroOps = 5;
1185 let ResourceCycles = [1,1,1,2];
1187 def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m(1|i)",
1188 "ROR(8|16|32|64)m(1|i)")>;
1190 def HWWriteResGroup46_1 : SchedWriteRes<[HWPort06]> {
1192 let NumMicroOps = 2;
1193 let ResourceCycles = [2];
1195 def: InstRW<[HWWriteResGroup46_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
1196 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
1198 def HWWriteResGroup47 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
1200 let NumMicroOps = 5;
1201 let ResourceCycles = [1,1,1,2];
1203 def: InstRW<[HWWriteResGroup47], (instregex "XADD(8|16|32|64)rm")>;
1205 def HWWriteResGroup48 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
1207 let NumMicroOps = 5;
1208 let ResourceCycles = [1,1,1,1,1];
1210 def: InstRW<[HWWriteResGroup48], (instregex "CALL(16|32|64)m")>;
1211 def: InstRW<[HWWriteResGroup48], (instrs FARCALL64m)>;
1213 def HWWriteResGroup50 : SchedWriteRes<[HWPort1]> {
1215 let NumMicroOps = 1;
1216 let ResourceCycles = [1];
1218 def: InstRW<[HWWriteResGroup50], (instrs MMX_CVTPI2PSirr)>;
1219 def: InstRW<[HWWriteResGroup50], (instregex "P(DEP|EXT)(32|64)rr",
1220 "(V?)CVTDQ2PS(Y?)rr")>;
1222 def HWWriteResGroup51 : SchedWriteRes<[HWPort5]> {
1224 let NumMicroOps = 1;
1225 let ResourceCycles = [1];
1227 def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCAST(B|W)rr")>;
1229 def HWWriteResGroup52 : SchedWriteRes<[HWPort1,HWPort23]> {
1231 let NumMicroOps = 2;
1232 let ResourceCycles = [1,1];
1234 def: InstRW<[HWWriteResGroup52], (instregex "(V?)CVTPS2DQrm",
1235 "(V?)CVTTPS2DQrm")>;
1237 def HWWriteResGroup52_1 : SchedWriteRes<[HWPort1,HWPort23]> {
1239 let NumMicroOps = 2;
1240 let ResourceCycles = [1,1];
1242 def: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1243 "ILD_F(16|32|64)m")>;
1244 def: InstRW<[HWWriteResGroup52_1], (instrs VCVTDQ2PSYrm,
1248 def HWWriteResGroup53_1 : SchedWriteRes<[HWPort5,HWPort23]> {
1250 let NumMicroOps = 2;
1251 let ResourceCycles = [1,1];
1253 def: InstRW<[HWWriteResGroup53_1], (instrs VPMOVSXBWYrm,
1258 def HWWriteResGroup57 : SchedWriteRes<[HWPort5,HWPort0156]> {
1260 let NumMicroOps = 3;
1261 let ResourceCycles = [2,1];
1263 def: InstRW<[HWWriteResGroup57], (instrs MMX_PACKSSDWirr,
1267 def HWWriteResGroup58 : SchedWriteRes<[HWPort6,HWPort0156]> {
1269 let NumMicroOps = 3;
1270 let ResourceCycles = [1,2];
1272 def: InstRW<[HWWriteResGroup58], (instregex "CLD")>;
1274 def HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> {
1276 let NumMicroOps = 3;
1277 let ResourceCycles = [1,2];
1279 def: InstRW<[HWWriteResGroup59], (instregex "RCL(8|16|32|64)r(1|i)",
1280 "RCR(8|16|32|64)r(1|i)")>;
1282 def HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> {
1284 let NumMicroOps = 3;
1285 let ResourceCycles = [1,1,1];
1287 def: InstRW<[HWWriteResGroup61], (instrs FNSTSWm)>;
1289 def HWWriteResGroup62 : SchedWriteRes<[HWPort1,HWPort4,HWPort237]> {
1291 let NumMicroOps = 3;
1292 let ResourceCycles = [1,1,1];
1294 def: InstRW<[HWWriteResGroup62], (instregex "IST(T?)_FP(16|32|64)m",
1297 def HWWriteResGroup66 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> {
1299 let NumMicroOps = 5;
1300 let ResourceCycles = [1,1,1,2];
1302 def: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)m(1|i)",
1303 "RCR(8|16|32|64)m(1|i)")>;
1305 def HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
1307 let NumMicroOps = 6;
1308 let ResourceCycles = [1,1,1,3];
1310 def: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>;
1312 def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> {
1314 let NumMicroOps = 6;
1315 let ResourceCycles = [1,1,1,2,1];
1317 def: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL",
1318 "ROR(8|16|32|64)mCL",
1319 "SAR(8|16|32|64)mCL",
1320 "SHL(8|16|32|64)mCL",
1321 "SHR(8|16|32|64)mCL")>;
1322 def: SchedAlias<WriteADCRMW, HWWriteResGroup69>;
1324 def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> {
1326 let NumMicroOps = 2;
1327 let ResourceCycles = [1,1];
1329 def: InstRW<[HWWriteResGroup70], (instregex "(V?)CVT(T?)SD2SI(64)?rr",
1330 "(V?)CVT(T?)SS2SI(64)?rr")>;
1332 def HWWriteResGroup71 : SchedWriteRes<[HWPort0,HWPort5]> {
1334 let NumMicroOps = 2;
1335 let ResourceCycles = [1,1];
1337 def: InstRW<[HWWriteResGroup71], (instrs VCVTPS2PDYrr)>;
1339 def HWWriteResGroup72 : SchedWriteRes<[HWPort0,HWPort0156]> {
1341 let NumMicroOps = 2;
1342 let ResourceCycles = [1,1];
1344 def: InstRW<[HWWriteResGroup72], (instrs FNSTSW16r)>;
1346 def HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> {
1348 let NumMicroOps = 2;
1349 let ResourceCycles = [1,1];
1351 def: InstRW<[HWWriteResGroup73], (instrs MMX_CVTPI2PDirr,
1356 def: InstRW<[HWWriteResGroup73], (instregex "(V?)CVTDQ2PDrr",
1359 "(V?)CVTSI(64)?2SDrr",
1361 "(V?)CVT(T?)PD2DQrr")>;
1363 def HWWriteResGroup75 : SchedWriteRes<[HWPort1,HWPort23]> {
1365 let NumMicroOps = 3;
1366 let ResourceCycles = [2,1];
1368 def: InstRW<[HWWriteResGroup75], (instregex "FICOM(P?)(16|32)m")>;
1370 def HWWriteResGroup76 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
1372 let NumMicroOps = 3;
1373 let ResourceCycles = [1,1,1];
1375 def: InstRW<[HWWriteResGroup76], (instregex "(V?)CVTSD2SI(64)?rm",
1376 "(V?)CVTSS2SI(64)?rm",
1377 "(V?)CVTTSD2SI(64)?rm",
1379 "(V?)CVTTSS2SIrm")>;
1381 def HWWriteResGroup77 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
1383 let NumMicroOps = 3;
1384 let ResourceCycles = [1,1,1];
1386 def: InstRW<[HWWriteResGroup77], (instrs VCVTPS2PDYrm)>;
1388 def HWWriteResGroup78 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
1390 let NumMicroOps = 3;
1391 let ResourceCycles = [1,1,1];
1393 def: InstRW<[HWWriteResGroup78], (instrs CVTPD2PSrm,
1401 def HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
1403 let NumMicroOps = 3;
1404 let ResourceCycles = [1,1,1];
1406 def: InstRW<[HWWriteResGroup78_1], (instrs MMX_CVTPI2PDirm,
1407 CVTSD2SSrm, CVTSD2SSrm_Int,
1408 VCVTSD2SSrm, VCVTSD2SSrm_Int)>;
1410 def HWWriteResGroup80 : SchedWriteRes<[HWPort5,HWPort23,HWPort015]> {
1412 let NumMicroOps = 3;
1413 let ResourceCycles = [1,1,1];
1415 def: InstRW<[HWWriteResGroup80], (instregex "VPBROADCAST(B|W)(Y?)rm")>;
1417 def HWWriteResGroup81 : SchedWriteRes<[HWPort0156]> {
1419 let NumMicroOps = 4;
1420 let ResourceCycles = [4];
1422 def: InstRW<[HWWriteResGroup81], (instrs FNCLEX)>;
1424 def HWWriteResGroup82 : SchedWriteRes<[]> {
1426 let NumMicroOps = 4;
1427 let ResourceCycles = [];
1429 def: InstRW<[HWWriteResGroup82], (instrs VZEROUPPER)>;
1431 def HWWriteResGroup83 : SchedWriteRes<[HWPort1,HWPort6,HWPort0156]> {
1433 let NumMicroOps = 4;
1434 let ResourceCycles = [1,1,2];
1436 def: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>;
1438 def HWWriteResGroup87 : SchedWriteRes<[HWPort1,HWPort6,HWPort23,HWPort0156]> {
1440 let NumMicroOps = 5;
1441 let ResourceCycles = [1,2,1,1];
1443 def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm",
1444 "LSL(16|32|64)rm")>;
1446 def HWWriteResGroup88 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {
1448 let NumMicroOps = 6;
1449 let ResourceCycles = [1,1,4];
1451 def: InstRW<[HWWriteResGroup88], (instregex "PUSHF(16|64)")>;
1453 def HWWriteResGroup89 : SchedWriteRes<[HWPort0]> {
1455 let NumMicroOps = 1;
1456 let ResourceCycles = [1];
1458 def: InstRW<[HWWriteResGroup89], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
1460 def HWWriteResGroup91_2 : SchedWriteRes<[HWPort0,HWPort23]> {
1462 let NumMicroOps = 2;
1463 let ResourceCycles = [1,1];
1465 def: InstRW<[HWWriteResGroup91_2], (instregex "(V?)PCMPGTQrm")>;
1467 def HWWriteResGroup91_3 : SchedWriteRes<[HWPort0,HWPort23]> {
1469 let NumMicroOps = 2;
1470 let ResourceCycles = [1,1];
1472 def: InstRW<[HWWriteResGroup91_3], (instregex "MUL_F(32|64)m")>;
1473 def: InstRW<[HWWriteResGroup91_3], (instrs VPCMPGTQYrm)>;
1475 def HWWriteResGroup93 : SchedWriteRes<[HWPort1,HWPort5]> {
1477 let NumMicroOps = 3;
1478 let ResourceCycles = [1,2];
1480 def: InstRW<[HWWriteResGroup93], (instregex "(V?)CVTSI642SSrr")>;
1482 def HWWriteResGroup94 : SchedWriteRes<[HWPort1,HWPort6,HWPort06]> {
1484 let NumMicroOps = 3;
1485 let ResourceCycles = [1,1,1];
1487 def: InstRW<[HWWriteResGroup94], (instregex "STR(16|32|64)r")>;
1489 def HWWriteResGroup97 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> {
1491 let NumMicroOps = 4;
1492 let ResourceCycles = [1,1,1,1];
1494 def: InstRW<[HWWriteResGroup97], (instregex "CVTTSS2SI64rm")>;
1496 def HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> {
1498 let NumMicroOps = 5;
1499 let ResourceCycles = [1,4];
1501 def: InstRW<[HWWriteResGroup99], (instrs PAUSE)>;
1503 def HWWriteResGroup100 : SchedWriteRes<[HWPort06,HWPort0156]> {
1505 let NumMicroOps = 5;
1506 let ResourceCycles = [1,4];
1508 def: InstRW<[HWWriteResGroup100], (instrs XSETBV)>;
1510 def HWWriteResGroup102 : SchedWriteRes<[HWPort1,HWPort5]> {
1512 let NumMicroOps = 2;
1513 let ResourceCycles = [1,1];
1515 def: InstRW<[HWWriteResGroup102], (instrs VCVTDQ2PDYrr,
1520 def HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> {
1522 let NumMicroOps = 3;
1523 let ResourceCycles = [2,1];
1525 def: InstRW<[HWWriteResGroup103], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1527 def HWWriteResGroup104 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
1529 let NumMicroOps = 3;
1530 let ResourceCycles = [1,1,1];
1532 def: InstRW<[HWWriteResGroup104], (instrs VCVTDQ2PDYrm)>;
1534 def HWWriteResGroup107 : SchedWriteRes<[HWPort1,HWPort6,HWPort06,HWPort0156]> {
1536 let NumMicroOps = 4;
1537 let ResourceCycles = [1,1,1,1];
1539 def: InstRW<[HWWriteResGroup107], (instregex "SLDT(16|32|64)r")>;
1541 def HWWriteResGroup108 : SchedWriteRes<[HWPort6,HWPort0156]> {
1543 let NumMicroOps = 6;
1544 let ResourceCycles = [1,5];
1546 def: InstRW<[HWWriteResGroup108], (instrs STD)>;
1548 def HWWriteResGroup114 : SchedWriteRes<[HWPort6,HWPort06,HWPort15,HWPort0156]> {
1550 let NumMicroOps = 7;
1551 let ResourceCycles = [2,2,1,2];
1553 def: InstRW<[HWWriteResGroup114], (instrs LOOP)>;
1555 def HWWriteResGroup115 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
1557 let NumMicroOps = 3;
1558 let ResourceCycles = [1,1,1];
1560 def: InstRW<[HWWriteResGroup115], (instregex "MUL_FI(16|32)m")>;
1562 def HWWriteResGroup120 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
1564 let NumMicroOps = 10;
1565 let ResourceCycles = [1,1,1,4,1,2];
1567 def: InstRW<[HWWriteResGroup120], (instregex "RCL(8|16|32|64)mCL")>;
1569 def HWWriteResGroup129 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {
1571 let NumMicroOps = 7;
1572 let ResourceCycles = [2,2,3];
1574 def: InstRW<[HWWriteResGroup129], (instregex "RCL(16|32|64)rCL",
1575 "RCR(16|32|64)rCL")>;
1577 def HWWriteResGroup130 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> {
1579 let NumMicroOps = 9;
1580 let ResourceCycles = [1,4,1,3];
1582 def: InstRW<[HWWriteResGroup130], (instrs RCL8rCL)>;
1584 def HWWriteResGroup131 : SchedWriteRes<[HWPort06,HWPort0156]> {
1586 let NumMicroOps = 11;
1587 let ResourceCycles = [2,9];
1589 def: InstRW<[HWWriteResGroup131], (instrs LOOPE, LOOPNE)>;
1591 def HWWriteResGroup132 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
1593 let NumMicroOps = 14;
1594 let ResourceCycles = [1,1,1,4,2,5];
1596 def: InstRW<[HWWriteResGroup132], (instrs CMPXCHG8B)>;
1598 def HWWriteResGroup135 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
1600 let NumMicroOps = 11;
1601 let ResourceCycles = [2,1,1,3,1,3];
1603 def: InstRW<[HWWriteResGroup135], (instregex "RCR(8|16|32|64)mCL")>;
1605 def HWWriteResGroup142 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> {
1607 let NumMicroOps = 10;
1608 let ResourceCycles = [2,3,1,4];
1610 def: InstRW<[HWWriteResGroup142], (instrs RCR8rCL)>;
1612 def HWWriteResGroup143 : SchedWriteRes<[HWPort23,HWPort0156]> {
1614 let NumMicroOps = 15;
1615 let ResourceCycles = [1,14];
1617 def: InstRW<[HWWriteResGroup143], (instrs POPF16)>;
1619 def HWWriteResGroup144 : SchedWriteRes<[HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> {
1621 let NumMicroOps = 8;
1622 let ResourceCycles = [1,1,1,1,1,1,2];
1624 def: InstRW<[HWWriteResGroup144], (instrs INSB, INSL, INSW)>;
1626 def HWWriteResGroup145 : SchedWriteRes<[HWPort5, HWPort6]> {
1628 let NumMicroOps = 20;
1629 let ResourceCycles = [1,1];
1631 def: InstRW<[HWWriteResGroup145], (instrs VZEROALL)>;
1633 def HWWriteResGroup146 : SchedWriteRes<[HWPort0,HWPort4,HWPort5,HWPort23,HWPort237,HWPort06,HWPort0156]> {
1635 let NumMicroOps = 19;
1636 let ResourceCycles = [2,1,4,1,1,4,6];
1638 def: InstRW<[HWWriteResGroup146], (instrs CMPXCHG16B)>;
1640 def HWWriteResGroup147 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> {
1642 let NumMicroOps = 15;
1643 let ResourceCycles = [2,1,2,4,2,4];
1645 def: InstRW<[HWWriteResGroup147], (instrs XCH_F)>;
1647 def HWWriteResGroup149 : SchedWriteRes<[HWPort5,HWPort6,HWPort06,HWPort0156]> {
1649 let NumMicroOps = 8;
1650 let ResourceCycles = [1,1,1,5];
1652 def: InstRW<[HWWriteResGroup149], (instrs CPUID, RDTSC)>;
1654 def HWWriteResGroup151 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
1656 let NumMicroOps = 19;
1657 let ResourceCycles = [3,1,15];
1659 def: InstRW<[HWWriteResGroup151], (instregex "XRSTOR(64)?")>;
1661 def HWWriteResGroup154 : SchedWriteRes<[HWPort0]> {
1663 let NumMicroOps = 1;
1664 let ResourceCycles = [1];
1666 def: InstRW<[HWWriteResGroup154], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1668 def HWWriteResGroup155 : SchedWriteRes<[HWPort0,HWPort23]> {
1670 let NumMicroOps = 2;
1671 let ResourceCycles = [1,1];
1673 def: InstRW<[HWWriteResGroup155], (instregex "DIVR_F(32|64)m")>;
1675 def HWWriteResGroup156 : SchedWriteRes<[HWPort5,HWPort6,HWPort0156]> {
1677 let NumMicroOps = 10;
1678 let ResourceCycles = [1,2,7];
1680 def: InstRW<[HWWriteResGroup156], (instrs MWAITrr)>;
1682 def HWWriteResGroup161 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
1684 let NumMicroOps = 3;
1685 let ResourceCycles = [1,1,1];
1687 def: InstRW<[HWWriteResGroup161], (instregex "DIVR_FI(16|32)m")>;
1689 def HWWriteResGroup162 : SchedWriteRes<[HWPort0]> {
1691 let NumMicroOps = 1;
1692 let ResourceCycles = [1];
1694 def: InstRW<[HWWriteResGroup162], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1696 def HWWriteResGroup163 : SchedWriteRes<[HWPort0,HWPort23]> {
1698 let NumMicroOps = 2;
1699 let ResourceCycles = [1,1];
1701 def: InstRW<[HWWriteResGroup163], (instregex "DIV_F(32|64)m")>;
1703 def HWWriteResGroup164 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
1705 let NumMicroOps = 27;
1706 let ResourceCycles = [1,5,1,1,19];
1708 def: InstRW<[HWWriteResGroup164], (instrs XSAVE64)>;
1710 def HWWriteResGroup165 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
1712 let NumMicroOps = 28;
1713 let ResourceCycles = [1,6,1,1,19];
1715 def: InstRW<[HWWriteResGroup165], (instrs XSAVE)>;
1716 def: InstRW<[HWWriteResGroup165], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
1718 def HWWriteResGroup166 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
1720 let NumMicroOps = 3;
1721 let ResourceCycles = [1,1,1];
1723 def: InstRW<[HWWriteResGroup166], (instregex "DIV_FI(16|32)m")>;
1725 def HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort0156]> {
1727 let NumMicroOps = 23;
1728 let ResourceCycles = [1,5,3,4,10];
1730 def: InstRW<[HWWriteResGroup170], (instregex "IN(8|16|32)ri",
1733 def HWWriteResGroup171 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> {
1735 let NumMicroOps = 23;
1736 let ResourceCycles = [1,5,2,1,4,10];
1738 def: InstRW<[HWWriteResGroup171], (instregex "OUT(8|16|32)ir",
1741 def HWWriteResGroup175 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort15,HWPort0156]> {
1743 let NumMicroOps = 18;
1744 let ResourceCycles = [1,1,2,3,1,1,1,8];
1746 def: InstRW<[HWWriteResGroup175], (instrs VMCLEARm)>;
1748 def HWWriteResGroup176 : SchedWriteRes<[HWPort5,HWPort0156]> {
1750 let NumMicroOps = 22;
1751 let ResourceCycles = [2,20];
1753 def: InstRW<[HWWriteResGroup176], (instrs RDTSCP)>;
1755 def HWWriteResGroup177 : SchedWriteRes<[HWPort0,HWPort01,HWPort23,HWPort05,HWPort06,HWPort015,HWPort0156]> {
1757 let NumMicroOps = 64;
1758 let ResourceCycles = [2,2,8,1,10,2,39];
1760 def: InstRW<[HWWriteResGroup177], (instrs FLDENVm)>;
1762 def HWWriteResGroup178 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> {
1764 let NumMicroOps = 88;
1765 let ResourceCycles = [4,4,31,1,2,1,45];
1767 def: InstRW<[HWWriteResGroup178], (instrs FXRSTOR64)>;
1769 def HWWriteResGroup179 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> {
1771 let NumMicroOps = 90;
1772 let ResourceCycles = [4,2,33,1,2,1,47];
1774 def: InstRW<[HWWriteResGroup179], (instrs FXRSTOR)>;
1776 def HWWriteResGroup180 : SchedWriteRes<[HWPort5,HWPort01,HWPort0156]> {
1778 let NumMicroOps = 15;
1779 let ResourceCycles = [6,3,6];
1781 def: InstRW<[HWWriteResGroup180], (instrs FNINIT)>;
1783 def HWWriteResGroup183 : SchedWriteRes<[HWPort0,HWPort1,HWPort4,HWPort5,HWPort6,HWPort237,HWPort06,HWPort0156]> {
1785 let NumMicroOps = 100;
1786 let ResourceCycles = [9,9,11,8,1,11,21,30];
1788 def: InstRW<[HWWriteResGroup183], (instrs FSTENVm)>;
1790 def HWWriteResGroup184 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
1792 let NumMicroOps = 12;
1793 let ResourceCycles = [2,2,2,1,3,2];
1795 def: InstRW<[HWWriteResGroup184], (instrs VGATHERDPDrm, VPGATHERDQrm)>;
1797 def HWWriteResGroup185 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
1799 let NumMicroOps = 20;
1800 let ResourceCycles = [3,3,4,1,5,4];
1802 def: InstRW<[HWWriteResGroup185], (instrs VGATHERDPDYrm, VPGATHERDQYrm)>;
1804 def HWWriteResGroup186 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
1806 let NumMicroOps = 20;
1807 let ResourceCycles = [3,3,4,1,5,4];
1809 def: InstRW<[HWWriteResGroup186], (instrs VGATHERDPSrm, VPGATHERDDrm)>;
1811 def HWWriteResGroup187 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
1813 let NumMicroOps = 34;
1814 let ResourceCycles = [5,3,8,1,9,8];
1816 def: InstRW<[HWWriteResGroup187], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;
1818 def HWWriteResGroup188 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
1820 let NumMicroOps = 14;
1821 let ResourceCycles = [3,3,2,1,3,2];
1823 def: InstRW<[HWWriteResGroup188], (instrs VGATHERQPDrm, VPGATHERQQrm)>;
1825 def HWWriteResGroup189 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
1827 let NumMicroOps = 22;
1828 let ResourceCycles = [5,3,4,1,5,4];
1830 def: InstRW<[HWWriteResGroup189], (instrs VGATHERQPDYrm, VPGATHERQQYrm,
1831 VGATHERQPSYrm, VPGATHERQDYrm)>;
1833 def HWWriteResGroup190 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
1835 let NumMicroOps = 15;
1836 let ResourceCycles = [3,3,2,1,4,2];
1838 def: InstRW<[HWWriteResGroup190], (instrs VGATHERQPSrm, VPGATHERQDrm)>;
1840 def: InstRW<[WriteZero], (instrs CLC)>;
1843 // Instruction variants handled by the renamer. These might not need execution
1844 // ports in certain conditions.
1845 // See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
1846 // section "Haswell and Broadwell Pipeline" > "Register allocation and
1848 // These can be investigated with llvm-exegesis, e.g.
1849 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1850 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1852 def HWWriteZeroLatency : SchedWriteRes<[]> {
1856 def HWWriteZeroIdiom : SchedWriteVariant<[
1857 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1858 SchedVar<NoSchedPred, [WriteALU]>
1860 def : InstRW<[HWWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
1863 def HWWriteFZeroIdiom : SchedWriteVariant<[
1864 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1865 SchedVar<NoSchedPred, [WriteFLogic]>
1867 def : InstRW<[HWWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr,
1870 def HWWriteFZeroIdiomY : SchedWriteVariant<[
1871 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1872 SchedVar<NoSchedPred, [WriteFLogicY]>
1874 def : InstRW<[HWWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>;
1876 def HWWriteVZeroIdiomLogicX : SchedWriteVariant<[
1877 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1878 SchedVar<NoSchedPred, [WriteVecLogicX]>
1880 def : InstRW<[HWWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>;
1882 def HWWriteVZeroIdiomLogicY : SchedWriteVariant<[
1883 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1884 SchedVar<NoSchedPred, [WriteVecLogicY]>
1886 def : InstRW<[HWWriteVZeroIdiomLogicY], (instrs VPXORYrr)>;
1888 def HWWriteVZeroIdiomALUX : SchedWriteVariant<[
1889 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1890 SchedVar<NoSchedPred, [WriteVecALUX]>
1892 def : InstRW<[HWWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr,
1896 PCMPGTBrr, VPCMPGTBrr,
1897 PCMPGTDrr, VPCMPGTDrr,
1898 PCMPGTWrr, VPCMPGTWrr)>;
1900 def HWWriteVZeroIdiomALUY : SchedWriteVariant<[
1901 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1902 SchedVar<NoSchedPred, [WriteVecALUY]>
1904 def : InstRW<[HWWriteVZeroIdiomALUY], (instrs VPSUBBYrr,
1912 def HWWritePCMPGTQ : SchedWriteRes<[HWPort0]> {
1914 let NumMicroOps = 1;
1915 let ResourceCycles = [1];
1918 def HWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
1919 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1920 SchedVar<NoSchedPred, [HWWritePCMPGTQ]>
1922 def : InstRW<[HWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
1926 // The 0x83 ADC/SBB opcodes have special support for immediate 0 to only require
1927 // a single uop. It does not apply to the GR8 encoding. And only applies to the
1928 // 8-bit immediate since using larger immediate for 0 would be silly.
1929 // Unfortunately, this optimization does not apply to the AX/EAX/RAX short
1930 // encodings we convert to in MCInstLowering so we exclude AX/EAX/RAX here since
1931 // we schedule before that point.
1932 // TODO: Should we disable using the short encodings on these CPUs?
1933 def HWFastADC0 : MCSchedPredicate<
1935 CheckImmOperand<2, 0>, // Second MCOperand is Imm and has value 0.
1936 CheckNot<CheckRegOperand<1, AX>>, // First MCOperand is not register AX
1937 CheckNot<CheckRegOperand<1, EAX>>, // First MCOperand is not register EAX
1938 CheckNot<CheckRegOperand<1, RAX>> // First MCOperand is not register RAX
1942 def HWWriteADC0 : SchedWriteRes<[HWPort06]> {
1944 let NumMicroOps = 1;
1945 let ResourceCycles = [1];
1948 def HWWriteADC : SchedWriteVariant<[
1949 SchedVar<HWFastADC0, [HWWriteADC0]>,
1950 SchedVar<NoSchedPred, [WriteADC]>
1953 def : InstRW<[HWWriteADC], (instrs ADC16ri8, ADC32ri8, ADC64ri8,
1954 SBB16ri8, SBB32ri8, SBB64ri8)>;
1956 // CMOVs that use both Z and C flag require an extra uop.
1957 def HWWriteCMOVA_CMOVBErr : SchedWriteRes<[HWPort06,HWPort0156]> {
1959 let ResourceCycles = [1,2];
1960 let NumMicroOps = 3;
1963 def HWWriteCMOVA_CMOVBErm : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {
1965 let ResourceCycles = [1,1,2];
1966 let NumMicroOps = 4;
1969 def HWCMOVA_CMOVBErr : SchedWriteVariant<[
1970 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [HWWriteCMOVA_CMOVBErr]>,
1971 SchedVar<NoSchedPred, [WriteCMOV]>
1974 def HWCMOVA_CMOVBErm : SchedWriteVariant<[
1975 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [HWWriteCMOVA_CMOVBErm]>,
1976 SchedVar<NoSchedPred, [WriteCMOV.Folded]>
1979 def : InstRW<[HWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
1980 def : InstRW<[HWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
1982 // SETCCs that use both Z and C flag require an extra uop.
1983 def HWWriteSETA_SETBEr : SchedWriteRes<[HWPort06,HWPort0156]> {
1985 let ResourceCycles = [1,1];
1986 let NumMicroOps = 2;
1989 def HWWriteSETA_SETBEm : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> {
1991 let ResourceCycles = [1,1,1,1];
1992 let NumMicroOps = 4;
1995 def HWSETA_SETBErr : SchedWriteVariant<[
1996 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [HWWriteSETA_SETBEr]>,
1997 SchedVar<NoSchedPred, [WriteSETCC]>
2000 def HWSETA_SETBErm : SchedWriteVariant<[
2001 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [HWWriteSETA_SETBEm]>,
2002 SchedVar<NoSchedPred, [WriteSETCCStore]>
2005 def : InstRW<[HWSETA_SETBErr], (instrs SETCCr)>;
2006 def : InstRW<[HWSETA_SETBErm], (instrs SETCCm)>;